diff options
Diffstat (limited to 'src/arch/arm/v7/opdefs/add_A884.d')
| -rw-r--r-- | src/arch/arm/v7/opdefs/add_A884.d | 97 |
1 files changed, 39 insertions, 58 deletions
diff --git a/src/arch/arm/v7/opdefs/add_A884.d b/src/arch/arm/v7/opdefs/add_A884.d index fb79567..8b624a7 100644 --- a/src/arch/arm/v7/opdefs/add_A884.d +++ b/src/arch/arm/v7/opdefs/add_A884.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2014 Cyrille Bagard + * Copyright (C) 2015 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,95 +23,76 @@ @title ADD (immediate, Thumb) -@encoding(t1) { +@desc This instruction adds an immediate value to a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - @half 0 0 0 1 1 1 0 imm3(3) Rn(3) Rd(3) +@encoding (t1) { - @syntax <Rd> <Rn> <const> + @half 0 0 0 1 1 1 0 imm3(3) Rn(3) Rd(3) - @conv { + @syntax "adds" <reg_D> <reg_N> <imm32> - Rd = Register(Rd) - Rn = Register(Rn) - const = ZeroExtend(imm3, 3, 32); + @conv { - } + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm3, 32) - @rules { - - //setflags = !InITBlock(); - - } + } } -@encoding(t2) { - - @half 0 0 1 1 0 Rdn(3) imm8(8) - - @syntax <Rdn> <const> - - @conv { +@encoding (t2) { - Rdn = Register(Rdn) - const = ZeroExtend(imm8, 8, 32); + @half 0 0 1 1 0 Rdn(3) imm8(8) - } + @syntax "adds" <reg_DN> <imm32> - @rules { + @conv { - //setflags = !InITBlock(); + reg_DN = Register(Rdn) + imm32 = ZeroExtend(imm8, 32) - } + } } -@encoding(T3) { +@encoding (T3) { - @word 1 1 1 1 0 i(1) 0 1 0 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) + @word 1 1 1 1 0 i(1) 0 1 0 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - @syntax {S} ".W" <Rd> <Rn> <const> + @syntax <reg_D> <reg_N> <imm32> - @conv { + @conv { - S = SetFlags(S) - Rd = Register(Rd) - Rn = Register(Rn) - const = ThumbExpandImm_C(i:imm3:imm8, i) + reg_D = Register(Rd) + reg_N = Register(Rn) + setflags = (S == '1') + imm32 = ThumbExpandImm(i:imm3:imm8) - } + } - @rules { + @rules { - //if Rd == '1111' && S == '1' then SEE CMN (immediate); - //if Rn == '1101' then SEE ADD (SP plus immediate); - //if d == 13 || (d == 15 && S == '0') || n == 15 then UNPREDICTABLE; + if (setflags); chk_call ExtendKeyword("s") + chk_call ExtendKeyword(".w") - } + } } -@encoding(T4) { +@encoding (T4) { - @word 1 1 1 1 0 i(1) 1 0 0 0 0 0 Rn(4) 0 imm3(3) Rd(4) imm8(8) + @word 1 1 1 1 0 i(1) 1 0 0 0 0 0 Rn(4) 0 imm3(3) Rd(4) imm8(8) - @syntax "addw" <Rd> <Rn> <const> + @syntax "addw" <reg_D> <reg_N> <imm32> - @conv { + @conv { - Rd = Register(Rd) - Rn = Register(Rn) - const = ZeroExtend(i:imm3:imm8, 12, 32) + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ZeroExtend(i:imm3:imm8, 32) - } - - @rules { - - //if Rn == '1111' then SEE ADR; - //if Rn == '1101' then SEE ADD (SP plus immediate); - //setflags = FALSE - //if d IN {13,15} then UNPREDICTABLE; - - } + } } + |