1 files changed, 33 insertions, 40 deletions
diff --git a/src/arch/arm/v7/opdefs/add_A886.d b/src/arch/arm/v7/opdefs/add_A886.d
index fd8f7a4..e4f9e00 100644
--- a/src/arch/arm/v7/opdefs/add_A886.d
+++ b/src/arch/arm/v7/opdefs/add_A886.d
@@ -2,7 +2,7 @@
 /* Chrysalide - Outil d'analyse de fichiers binaires
  * ##FILE## - traduction d'instructions ARMv7
  *
- * Copyright (C) 2014 Cyrille Bagard
+ * Copyright (C) 2015 Cyrille Bagard
  *
  *  This file is part of Chrysalide.
  *
@@ -23,68 +23,61 @@
 
 @title ADD (register, Thumb)
 
-@encoding(t1) {
+@desc This instruction adds a register value and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result.
 
-    @half 0 0 0 1 1 0 0 Rm(3) Rn(3) Rd(3)
+@encoding (t1) {
 
-    @syntax <Rd> <Rn> <Rm>
+	@half 0 0 0 1 1 0 0 Rm(3) Rn(3) Rd(3)
 
-    @conv {
+	@syntax "adds" <reg_D> <reg_N> <reg_M>
 
-        Rd = Register(Rd)
-        Rn = Register(Rn)
-        Rm = Register(Rm)
+	@conv {
 
-    }
+		reg_D = Register(Rd)
+		reg_N = Register(Rn)
+		reg_M = Register(Rm)
 
-}
-
-@encoding(t2) {
-
-    @half 0 1 0 0 0 1 0 0 DN(1) Rm(4) Rdn(3)
+	}
 
-    @syntax <Rdn> <Rm>
+}
 
-    @conv {
+@encoding (t2) {
 
-        Rdn = Register(DN:Rdn)
-        Rm = Register(Rm)
+	@half 0 1 0 0 0 1 0 0 DN(1) Rm(4) Rdn(3)
 
-    }
+	@syntax <reg_DN> <reg_M>
 
-    @rules {
+	@conv {
 
-        //if (DN:Rdn) == '1101' || Rm == '1101' then SEE ADD (SP plus register);
-        //if n == 15 && m == 15 then UNPREDICTABLE;
-        //if d == 15 && InITBlock() && !LastInITBlock() then UNPREDICTABLE;
+		reg_DN = Register(DN:Rdn)
+		reg_M = Register(Rm)
 
-    }
+	}
 
 }
 
-@encoding(T3) {
-
-    @word 1 1 1 0 1 0 1 1 0 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4)
+@encoding (T3) {
 
-    @syntax {S} ".W" <Rd> <Rn> <Rm> <?shift>
+	@word 1 1 1 0 1 0 1 1 0 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4)
 
-    @conv {
+	@syntax <reg_D> <reg_N> <reg_M> <?shift>
 
-        S = SetFlags(S)
-        Rd = Register(Rd)
-        Rn = Register(Rn)
-        Rm = Register(Rm)
-        shift = DecodeImmShift(type, imm3:imm2)
+	@conv {
 
-    }
+		reg_D = Register(Rd)
+		reg_N = Register(Rn)
+		reg_M = Register(Rm)
+		setflags = (S == '1')
+		shift = DecodeImmShift(type, imm3:imm2)
 
-    @rules {
+	}
 
-        //if Rd == '1111' && S == '1' then SEE CMN (register);
-        //if Rn == '1101' then SEE ADD (SP plus register);
-        //if d == 13 || (d == 15 && S == '0') || n == 15 || m IN {13,15} then UNPREDICTABLE;
+	@rules {
 
+		if (setflags); chk_call ExtendKeyword("s")
+		chk_call ExtendKeyword(".w")
 
-    }
+	}
 
 }
+