diff options
Diffstat (limited to 'src/arch/arm/v7/opdefs/add_A887.d')
| -rw-r--r-- | src/arch/arm/v7/opdefs/add_A887.d | 34 |
1 files changed, 18 insertions, 16 deletions
diff --git a/src/arch/arm/v7/opdefs/add_A887.d b/src/arch/arm/v7/opdefs/add_A887.d index 17bbe7f..18400a6 100644 --- a/src/arch/arm/v7/opdefs/add_A887.d +++ b/src/arch/arm/v7/opdefs/add_A887.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2014 Cyrille Bagard + * Copyright (C) 2015 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,28 +23,30 @@ @title ADD (register, ARM) -@encoding(A1) { +@desc This instruction adds a register value and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - @word cond(4) 0 0 0 0 1 0 0 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) +@encoding (A1) { - @syntax {S} {c} <Rd> <Rn> <Rm> <?shift> + @word cond(4) 0 0 0 0 1 0 0 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) - @conv { + @syntax <reg_D> <reg_N> <reg_M> <?shift> - S = SetFlags(S) - c = Condition(cond) - Rd = Register(Rd) - Rn = Register(Rn) - Rm = Register(Rm) - shift = DecodeImmShift(type, imm5) + @conv { - } + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + shift = DecodeImmShift(type, imm5) - @rules { + } - //if ((Rd == '1111') && (S == '1')) ; see SUBS PC, LR and related instructions - //if Rn == '1101' then SEE ADD (SP plus register); + @rules { - } + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } } + |