diff options
Diffstat (limited to 'src/arch/arm/v7/opdefs/adr_A8812.d')
| -rw-r--r-- | src/arch/arm/v7/opdefs/adr_A8812.d | 98 |
1 files changed, 48 insertions, 50 deletions
diff --git a/src/arch/arm/v7/opdefs/adr_A8812.d b/src/arch/arm/v7/opdefs/adr_A8812.d index 38ad6af..16615cb 100644 --- a/src/arch/arm/v7/opdefs/adr_A8812.d +++ b/src/arch/arm/v7/opdefs/adr_A8812.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2014 Cyrille Bagard + * Copyright (C) 2015 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,94 +23,92 @@ @title ADR -@encoding(t1) { +@desc This instruction adds an immediate value to the PC value to form a PC-relative address, and writes the result to the destination register. - @half 1 0 1 0 0 Rd(3) imm8(8) +@encoding (t1) { - @syntax "add" <Rd> <PC> <imm32> + @half 1 0 1 0 0 Rd(3) imm8(8) - @conv { + @syntax <reg_D> <imm32> - Rd = Register(Rd) - PC = Register(15) - imm32 = ZeroExtend(imm8:'00', 10, 32) + @conv { - } + reg_D = Register(Rd) + imm32 = ZeroExtend(imm8:'00', 32) + + } } -@encoding(T2) { +@encoding (T2) { - @word 1 1 1 1 0 i(1) 1 0 1 0 1 0 1 1 1 1 0 imm3(3) Rd(4) imm8(8) + @word 1 1 1 1 0 i(1) 1 0 1 0 1 0 1 1 1 1 0 imm3(3) Rd(4) imm8(8) - @syntax "sub" <Rd> <PC> <imm32> + @syntax ".W" <reg_D> <imm32> - @conv { + @conv { - Rd = Register(Rd) - PC = Register(15) - imm32 = ZeroExtend(i:imm3:imm8, 12, 32) + reg_D = Register(Rd) + imm32 = ZeroExtend(i:imm3:imm8, 32) - } + } - @rules { +} - //if d IN {13,15} then UNPREDICTABLE; +@encoding (T3) { - } + @word 1 1 1 1 0 i(1) 1 0 0 0 0 0 1 1 1 1 0 imm3(3) Rd(4) imm8(8) -} + @syntax ".W" <reg_D> <imm32> -@encoding(T3) { + @conv { - @word 1 1 1 1 0 i(1) 1 0 0 0 0 0 1 1 1 1 0 imm3(3) Rd(4) imm8(8) + reg_D = Register(Rd) + imm32 = ZeroExtend(i:imm3:imm8, 32) - @syntax "add" <Rd> <PC> <imm32> + } - @conv { +} - Rd = Register(Rd) - PC = Register(15) - imm32 = ZeroExtend(i:imm3:imm8, 12, 32) +@encoding (A1) { - } + @word cond(4) 0 0 1 0 1 0 0 0 1 1 1 1 Rd(4) imm12(12) - @rules { + @syntax <reg_D> <imm32> - //if d IN {13,15} then UNPREDICTABLE; + @conv { - } + reg_D = Register(Rd) + imm32 = ARMExpandImm(imm12) -} + } -@encoding(A1) { + @rules { - @word cond(4) 0 0 1 0 1 0 0 0 1 1 1 1 Rd(4) imm12(12) + chk_call StoreCondition(cond) - @syntax "add" <Rd> <PC> <const> + } - @conv { +} - Rd = Register(Rd) - PC = Register(15) - const = ARMExpandImm(imm12) +@encoding (A2) { - } + @word cond(4) 0 0 1 0 0 1 0 0 1 1 1 1 Rd(4) imm12(12) -} + @syntax <reg_D> <imm32> -@encoding(A2) { + @conv { - @word cond(4) 0 0 1 0 0 1 0 0 1 1 1 1 Rd(4) imm12(12) + reg_D = Register(Rd) + imm32 = ARMExpandImm(imm12) - @syntax "sub" <Rd> <PC> <const> + } - @conv { + @rules { - Rd = Register(Rd) - PC = Register(15) - const = ARMExpandImm(imm12) + chk_call StoreCondition(cond) - } + } } + |