diff options
Diffstat (limited to 'src/arch/arm/v7/opdefs/eor_A8847.d')
| -rw-r--r-- | src/arch/arm/v7/opdefs/eor_A8847.d | 75 |
1 files changed, 39 insertions, 36 deletions
diff --git a/src/arch/arm/v7/opdefs/eor_A8847.d b/src/arch/arm/v7/opdefs/eor_A8847.d index 3d7f5b5..66643a1 100644 --- a/src/arch/arm/v7/opdefs/eor_A8847.d +++ b/src/arch/arm/v7/opdefs/eor_A8847.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2014 Cyrille Bagard + * Copyright (C) 2015 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,67 +23,70 @@ @title EOR (register) -@encoding(t1) { +@desc Bitwise Exclusive OR (register) performs a bitwise Exclusive OR of a register value and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - @half 0 1 0 0 0 0 0 0 0 1 Rm(3) Rdn(3) +@encoding (t1) { - @syntax <Rdn> <Rm> + @half 0 1 0 0 0 0 0 0 0 1 Rm(3) Rdn(3) - @conv { + @syntax "eors" <reg_DN> <reg_M> - Rdn = Register(Rdn) - Rm = Register(Rm) + @conv { - } + reg_DN = Register(Rdn) + reg_M = Register(Rm) + + } } -@encoding(T2) { +@encoding (T2) { - @word 1 1 1 0 1 0 1 0 1 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) + @word 1 1 1 0 1 0 1 0 1 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - @syntax {S} <Rd> <Rn> <Rm> <?shift> + @syntax <reg_D> <reg_N> <reg_M> <?shift> - @conv { + @conv { - S = SetFlags(S) - Rd = Register(Rd) - Rn = Register(Rn) - Rm = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + shift = DecodeImmShift(type, imm3:imm2) - } + } - @rules { + @rules { - //if ((Rd == '1111') && (S == '1')) ; see TEQ (register) - //if ((d == 13) || ((d == 15) && (S == '0')) || (n IN {13,15})) ; unpredictable + if (setflags); chk_call ExtendKeyword("s") + chk_call ExtendKeyword(".w") - } + } } -@encoding(A1) { +@encoding (A1) { - @word cond(4) 0 0 0 0 0 0 1 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) + @word cond(4) 0 0 0 0 0 0 1 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) - @syntax {S} {c} <Rd> <Rn> <Rm> <?shift> + @syntax <reg_D> <reg_N> <reg_M> <?shift> - @conv { + @conv { - S = SetFlags(S) - c = Condition(cond) - Rd = Register(Rd) - Rn = Register(Rn) - Rm = Register(Rm) - shift = DecodeImmShift(type, imm5) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + shift = DecodeImmShift(type, imm5) - } + } - @rules { + @rules { - //if ((Rd == '1111') && (S == '1')) ; see SUBS PC, LR and related instructions + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) - } + } } + |