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-rw-r--r--src/arch/arm/v7/opdefs/ldr_A8864.d89
1 files changed, 40 insertions, 49 deletions
diff --git a/src/arch/arm/v7/opdefs/ldr_A8864.d b/src/arch/arm/v7/opdefs/ldr_A8864.d
index bd7ed50..74afa2d 100644
--- a/src/arch/arm/v7/opdefs/ldr_A8864.d
+++ b/src/arch/arm/v7/opdefs/ldr_A8864.d
@@ -2,7 +2,7 @@
/* Chrysalide - Outil d'analyse de fichiers binaires
* ##FILE## - traduction d'instructions ARMv7
*
- * Copyright (C) 2014 Cyrille Bagard
+ * Copyright (C) 2015 Cyrille Bagard
*
* This file is part of Chrysalide.
*
@@ -23,86 +23,77 @@
@title LDR (literal)
-@encoding(t1) {
+@desc Load Register (literal) calculates an address from the PC value and an immediate offset, loads a word from memory, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294.
- @half 0 1 0 0 1 Rt(3) imm8(8)
+@encoding (t1) {
- @syntax <Rgt> <label>
+ @half 0 1 0 0 1 Rt(3) imm8(8)
- @conv {
+ @syntax <reg_T> <imm32>
- Rgt = Register(Rt)
- imm32 = ZeroExtend(imm8:'00', 10, 32)
- label = MakeAccessOffset(1, imm32)
+ @conv {
- }
+ reg_T = Register(Rt)
+ imm32 = ZeroExtend(imm8:'00', 32)
- @hooks {
+ }
- fetch = help_fetching_with_instruction_ldr_literal_from_thumb
- post = post_process_ldr_instructions
+ @hooks {
- }
+ fetch = help_fetching_with_instruction_ldr_literal_from_thumb
+ post = post_process_ldr_instructions
-}
-
-@encoding(T2) {
-
- @word 1 1 1 1 1 0 0 0 U(1) 1 0 1 1 1 1 1 Rt(4) imm12(12)
+ }
- @syntax <Rgt> <label>
+}
- @conv {
+@encoding (T2) {
- Rgt = Register(Rt)
- imm32 = ZeroExtend(imm12, 12, 32)
- label = MakeAccessOffset(U, imm32)
+ @word 1 1 1 1 1 0 0 0 U(1) 1 0 1 1 1 1 1 Rt(4) imm12(12)
- }
+ @syntax ".W" <reg_T> <imm32>
- @hooks {
+ @conv {
- fetch = help_fetching_with_instruction_ldr_literal_from_thumb
- post = post_process_ldr_instructions
+ reg_T = Register(Rt)
+ imm32 = ZeroExtend(imm12, 32)
- }
+ }
- @rules {
+ @hooks {
- //if t == 15 && InITBlock() && !LastInITBlock() then UNPREDICTABLE;
- if (Rt == '1111'); chk_call SetInsFlag(AIF_RETURN_POINT)
+ fetch = help_fetching_with_instruction_ldr_literal_from_thumb
+ post = post_process_ldr_instructions
- }
+ }
}
-@encoding(A1) {
+@encoding (A1) {
- @word cond(4) 0 1 0 1 U(1) 0 0 1 1 1 1 1 Rt(4) imm12(12)
+ @word cond(4) 0 1 0 1 U(1) 0 0 1 1 1 1 1 Rt(4) imm12(12)
- @syntax {c} <Rgt> <label>
+ @syntax <reg_T> <imm32>
- @conv {
+ @conv {
- c = Condition(cond)
- Rgt = Register(Rt)
- imm32 = ZeroExtend(imm12, 12, 32)
- label = MakeAccessOffset(U, imm32)
+ reg_T = Register(Rt)
+ imm32 = ZeroExtend(imm12, 32)
- }
+ }
- @hooks {
+ @rules {
- fetch = help_fetching_with_instruction_ldr_literal_from_arm
- post = post_process_ldr_instructions
+ chk_call StoreCondition(cond)
- }
+ }
- @rules {
+ @hooks {
- //if t == 15 && InITBlock() && !LastInITBlock() then UNPREDICTABLE;
- if (Rt == '1111'); chk_call SetInsFlag(AIF_RETURN_POINT)
+ fetch = help_fetching_with_instruction_ldr_literal_from_arm
+ post = post_process_ldr_instructions
- }
+ }
}
+