diff options
Diffstat (limited to 'src/arch/arm/v7/opdefs/ldrb_A8867.d')
| -rw-r--r-- | src/arch/arm/v7/opdefs/ldrb_A8867.d | 109 |
1 files changed, 33 insertions, 76 deletions
diff --git a/src/arch/arm/v7/opdefs/ldrb_A8867.d b/src/arch/arm/v7/opdefs/ldrb_A8867.d index c772b08..2dea64e 100644 --- a/src/arch/arm/v7/opdefs/ldrb_A8867.d +++ b/src/arch/arm/v7/opdefs/ldrb_A8867.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2014 Cyrille Bagard + * Copyright (C) 2015 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,102 +23,59 @@ @title LDRB (immediate, Thumb) -@encoding(t1) { +@desc Load Register Byte (immediate) calculates an address from a base register value and an immediate offset, loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. - @half 0 1 1 1 1 imm5(5) Rn(3) Rt(3) +@encoding (t1) { - @syntax <Rgt>, <access> + @half 0 1 1 1 1 imm5(5) Rn(3) Rt(3) - @conv { + @syntax <reg_T> <mem_access> - Rgt = Register(Rt) - Rgn = Register(Rn) - imm32 = ZeroExtend(imm5, 5, 32) - access = MakeMemoryAccess(Rgn, imm32, 1, 0) + @conv { - } + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm5, 32) + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) -} - -@encoding(T2) { - - @word 1 1 1 1 1 0 0 0 1 0 0 1 Rn(4) Rt(4) imm12(12) - - @syntax "ldrb.W" <Rgt>, <access> - - @conv { - - Rgt = Register(Rt) - Rgn = Register(Rn) - imm32 = ZeroExtend(imm12, 12, 32) - access = MakeMemoryAccess(Rgn, imm32, 1, 0) - - } - - @rules { - - //if Rt == '1111' then SEE PLD; - //if Rn == '1111' then SEE LDRB (literal); - //if t == 13 then UNPREDICTABLE; - if (Rt == '1111'); chk_call SetInsFlag(AIF_RETURN_POINT) - - } + } } -@encoding(T31) { - - @word 1 1 1 1 1 0 0 0 0 0 0 1 Rn(4) Rt(4) 1 1 U(1) W(1) imm8(8) - - @syntax <Rgt> <access> - - @conv { +@encoding (T2) { - Rgt = Register(Rt) - Rgn = Register(Rn) - imm32 = ZeroExtend(imm8, 8, 32); - access = MakeMemoryAccess(Rgn, imm32, U, W) + @word 1 1 1 1 1 0 0 0 1 0 0 1 Rn(4) Rt(4) imm12(12) - } + @syntax ".W" <reg_T> <mem_access> - @rules { + @conv { - //if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE PLD, PLDW (immediate); - //if Rn == '1111' then SEE LDRB (literal); - //if P == '1' && U == '1' && W == '0' then SEE LDRBT; - //if P == '0' && W == '0' then UNDEFINED; - //if t == 13 || (t == 15 && W == '1') || (wback && n == t) then UNPREDICTABLE; - if (Rt == '1111'); chk_call SetInsFlag(AIF_RETURN_POINT) + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) - } + } } -@encoding(T32) { +@encoding (T3) { - @word 1 1 1 1 1 0 0 0 0 0 0 1 Rn(4) Rt(4) 1 0 U(1) W(1) imm8(8) + @word 1 1 1 1 1 0 0 0 0 0 0 1 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) - @syntax <Rgt> <base> <offset> + @syntax <reg_T> <mem_access> - @conv { + @conv { - Rgt = Register(Rt) - Rgn = Register(Rn) - imm32 = ZeroExtend(imm8, 8, 32); - base = MakeMemoryNotIndexed(Rgn, W) - offset = MakeAccessOffset(U, imm32) + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + index = (P == '1') + add = (U == '1') + wback = (W == '1') + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) - } - - @rules { - - //if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE PLD, PLDW (immediate); - //if Rn == '1111' then SEE LDRB (literal); - //if P == '1' && U == '1' && W == '0' then SEE LDRBT; - //if P == '0' && W == '0' then UNDEFINED; - //if t == 13 || (t == 15 && W == '1') || (wback && n == t) then UNPREDICTABLE; - if (Rt == '1111'); chk_call SetInsFlag(AIF_RETURN_POINT) - - } + } } + |