diff options
Diffstat (limited to 'src/arch/arm/v7/opdefs/ldrb_A8870.d')
| -rw-r--r-- | src/arch/arm/v7/opdefs/ldrb_A8870.d | 114 |
1 files changed, 37 insertions, 77 deletions
diff --git a/src/arch/arm/v7/opdefs/ldrb_A8870.d b/src/arch/arm/v7/opdefs/ldrb_A8870.d index 2b6f2e9..35f95ab 100644 --- a/src/arch/arm/v7/opdefs/ldrb_A8870.d +++ b/src/arch/arm/v7/opdefs/ldrb_A8870.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2014 Cyrille Bagard + * Copyright (C) 2015 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,107 +23,67 @@ @title LDRB (register) -@encoding(t1) { +@desc Load Register Byte (register) calculates an address from a base register value and an offset register value, loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. The offset register value can optionally be shifted. For information about memory accesses see Memory accesses on page A8-294. - @half 0 1 0 1 1 1 0 Rm(3) Rn(3) Rt(3) +@encoding (t1) { - @syntax <Rgt> <access> + @half 0 1 0 1 1 1 0 Rm(3) Rn(3) Rt(3) - @conv { + @syntax <reg_T> <mem_access> - Rgt = Register(Rt) - Rgn = Register(Rn) - Rgm = Register(Rm) - access = _MakeMemoryAccess(Rgn, Rgm, 0) + @conv { - } + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, true, true, false) - @rules { - - } + } } -@encoding(T2) { - - @word 1 1 1 1 1 0 0 0 0 0 0 1 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) - - @syntax "ldrb.W" <Rgt>, <access> - - @conv { +@encoding (T2) { - Rgt = Register(Rt) - Rgn = Register(Rn) - Rgm = Register(Rm) - shift = DecodeImmShift(0, imm2) - access = MakeShiftedMemoryAccess(Rgn, Rgm, shift, 0) + @word 1 1 1 1 1 0 0 0 0 0 0 1 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) - } + @syntax ".W" <reg_T> <mem_access> - @rules { + @conv { - //if Rn == '1111' then UNDEFINED; - //if t IN {13,15} || m IN {13,15} then UNPREDICTABLE; + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(0, imm2) + mem_access = MakeMemoryAccess(reg_N, reg_M, shift, true, true, false) - if (Rt == '1111'); chk_call SetInsFlag(AIF_RETURN_POINT) - - } + } } -@encoding(A11) { +@encoding (A1) { - @word cond(4) 0 1 1 1 U(1) 1 W(1) 1 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) + @word cond(4) 0 1 1 P(1) U(1) 1 W(1) 1 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) - @syntax <Rgt> <access> + @syntax <reg_T> <mem_access> - @conv { + @conv { - Rgt = Register(Rt) - Rgn = Register(Rn) - Rgm = Register(Rm) - shift = DecodeImmShift(type, imm5) - access = MakeShiftedMemoryAccess(Rgn, Rgm, shift, W) + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + index = (P == '1') + add = (U == '1') + wback = (P == '0') || (W == '1') + shift = DecodeImmShift(type, imm5) + mem_access = MakeMemoryAccess(reg_N, reg_M, shift, index, add, wback) - } + } - @rules { + @rules { - //if P == '0' && W == '1' then SEE LDRBT; - //if t == 15 || m == 15 then UNPREDICTABLE; - //if wback && (n == 15 || n == t) then UNPREDICTABLE; - //if ArchVersion() < 6 && wback && m == n then UNPREDICTABLE; - if (Rt == '1111'); chk_call SetInsFlag(AIF_RETURN_POINT) + chk_call StoreCondition(cond) - } + } } -@encoding(A12) { - - @word cond(4) 0 1 1 0 U(1) 1 W(1) 1 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) - - @syntax <Rgt> <base> <offset> <?shift> - - @conv { - - Rgt = Register(Rt) - Rgn = Register(Rn) - Rgm = Register(Rm) - base = MakeMemoryNotIndexed(Rgn, 1) - offset = MakeAccessOffset(U, Rgm) - shift = DecodeImmShift(type, imm5) - - } - - @rules { - - //if P == '0' && W == '1' then SEE LDRBT; - //if t == 15 || m == 15 then UNPREDICTABLE; - //if wback && (n == 15 || n == t) then UNPREDICTABLE; - //if ArchVersion() < 6 && wback && m == n then UNPREDICTABLE; - if (Rt == '1111'); chk_call SetInsFlag(AIF_RETURN_POINT) - - } - -} |