diff options
Diffstat (limited to 'src/arch/arm/v7/opdefs/lsl_A8894.d')
| -rw-r--r-- | src/arch/arm/v7/opdefs/lsl_A8894.d | 81 |
1 files changed, 37 insertions, 44 deletions
diff --git a/src/arch/arm/v7/opdefs/lsl_A8894.d b/src/arch/arm/v7/opdefs/lsl_A8894.d index 59ac3e8..89924c6 100644 --- a/src/arch/arm/v7/opdefs/lsl_A8894.d +++ b/src/arch/arm/v7/opdefs/lsl_A8894.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2014 Cyrille Bagard + * Copyright (C) 2015 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,76 +23,69 @@ @title LSL (immediate) -@encoding(t1) { +@desc Logical Shift Left (immediate) shifts a register value left by an immediate number of bits, shifting in zeros, and writes the result to the destination register. It can optionally update the condition flags based on the result. - @half 0 0 0 0 0 imm5(5) Rm(3) Rd(3) +@encoding (t1) { - @syntax <Rgd> <Rgm> <shiftv> + @half 0 0 0 0 0 imm5(5) Rm(3) Rd(3) - @conv { + @syntax "lsls" <reg_D> <reg_M> <shift_imm> - Rgd = Register(Rd) - Rgm = Register(Rm) - shiftv = DecodeImmShiftValue(imm5) + @conv { - } + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_imm = DecodeImmShift('00', imm5) - @rules { - - if (imm5 == '00000') ; see MOV (register, Thumb) - //if (imm5 == '00000') ; see MOV (register) - - } + } } -@encoding(T2) { +@encoding (T2) { - @word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm2(2) 0 0 Rm(4) + @word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm2(2) 0 0 Rm(4) - @syntax {s} <Rgd> <Rgm> <shiftv> + @syntax <reg_D> <reg_M> <shift_imm> - @conv { + @conv { - S = SetFlags(S) - Rgd = Register(Rd) - Rgm = Register(Rm) - shiftv = DecodeImmShiftValue(imm3:imm2) + reg_D = Register(Rd) + reg_M = Register(Rm) + setflags = (S == '1') + shift_imm = DecodeImmShift('00', imm3:imm2) - } + } - @rules { + @rules { - if ((imm3 == '000') && (imm2 == '00')) ; see MOV (register, Thumb) - //if ((imm3 == '000') && (imm2 == '00')) ; see MOV (register, Thumb) - //if (imm3:imm2) == '00000' then SEE MOV (register); - //if d IN {13,15} || m IN {13,15} then UNPREDICTABLE; + if (setflags); chk_call ExtendKeyword("s") + chk_call ExtendKeyword(".w") - } + } } -@encoding(A1) { +@encoding (A1) { - @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) imm5(5) 0 0 0 Rm(4) + @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) imm5(5) 0 0 0 Rm(4) - @syntax {S} {c} <Rgd> <Rgm> <shiftv> + @syntax <reg_D> <reg_M> <shift_imm> - @conv { + @conv { - S = SetFlags(S) - c = Condition(cond) - Rgd = Register(Rd) - Rgm = Register(Rm) - shiftv = DecodeImmShiftValue(imm5) + reg_D = Register(Rd) + reg_M = Register(Rm) + setflags = (S == '1') + shift_imm = DecodeImmShift('00', imm5) - } + } - @rules { + @rules { - //if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions; - //if imm5 == '00000' then SEE MOV (register); + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) - } + } } + |