1 files changed, 26 insertions, 30 deletions
diff --git a/src/arch/arm/v7/opdefs/mla_A88100.d b/src/arch/arm/v7/opdefs/mla_A88100.d
index 2683e3a..5d4b4e4 100644
--- a/src/arch/arm/v7/opdefs/mla_A88100.d
+++ b/src/arch/arm/v7/opdefs/mla_A88100.d
@@ -2,7 +2,7 @@
 /* Chrysalide - Outil d'analyse de fichiers binaires
  * ##FILE## - traduction d'instructions ARMv7
  *
- * Copyright (C) 2014 Cyrille Bagard
+ * Copyright (C) 2015 Cyrille Bagard
  *
  *  This file is part of Chrysalide.
  *
@@ -23,51 +23,47 @@
 
 @title MLA
 
-@encoding(T1) {
+@desc Multiply Accumulate multiplies two register values, and adds a third register value. The least significant 32 bits of the result are written to the destination register. These 32 bits do not depend on whether the source register values are considered to be signed values or unsigned values. In an ARM instruction, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many processor implementations.
 
-    @word 1 1 1 1 1 0 1 1 0 0 0 0 Rn(4) Ra(4) Rd(4) 0 0 0 0 Rm(4)
+@encoding (T1) {
 
-    @syntax <Rd> <Rn> <Rm> <Ra>
+	@word 1 1 1 1 1 0 1 1 0 0 0 0 Rn(4) Ra(4) Rd(4) 0 0 0 0 Rm(4)
 
-    @conv {
+	@syntax <reg_D> <reg_N> <reg_M> <reg_A>
 
-        Rd = Register(Rd)
-        Rn = Register(Rn)
-        Rm = Register(Rm)
-        Ra = Register(Ra)
+	@conv {
 
-    }
+		reg_D = Register(Rd)
+		reg_N = Register(Rn)
+		reg_M = Register(Rm)
+		reg_A = Register(Ra)
 
-    @rules {
-
-        //if (Ra == '1111') ; see MUL
-        //if d IN {13,15} || n IN {13,15} || m IN {13,15} then UNPREDICTABLE
-
-    }
+	}
 
 }
 
-@encoding(A1) {
+@encoding (A1) {
 
-    @word cond(4) 0 0 0 0 0 0 1 S(1) Rd(4) Ra(4) Rm(4) 1 0 0 1 Rn(4)
+	@word cond(4) 0 0 0 0 0 0 1 S(1) Rd(4) Ra(4) Rm(4) 1 0 0 1 Rn(4)
 
-    @syntax {S} {c} <Rd> <Rn> <Rm> <Ra>
+	@syntax <reg_D> <reg_N> <reg_M> <reg_A>
 
-    @conv {
+	@conv {
 
-        S = SetFlags(S)
-        c = Condition(cond)
-        Rd = Register(Rd)
-        Rn = Register(Rn)
-        Rm = Register(Rm)
-        Ra = Register(Ra)
+		reg_D = Register(Rd)
+		reg_N = Register(Rn)
+		reg_M = Register(Rm)
+		reg_A = Register(Ra)
+		setflags = (S == '1')
 
-    }
+	}
 
-    @rules {
+	@rules {
 
-        //if d == 15 || n == 15 || m == 15 || a == 15 then UNPREDICTABLE
+		if (setflags); chk_call ExtendKeyword("s")
+		chk_call StoreCondition(cond)
 
-    }
+	}
 
 }
+