diff options
Diffstat (limited to 'src/arch/arm/v7/opdefs/mov_A88102.d')
| -rw-r--r-- | src/arch/arm/v7/opdefs/mov_A88102.d | 107 |
1 files changed, 52 insertions, 55 deletions
diff --git a/src/arch/arm/v7/opdefs/mov_A88102.d b/src/arch/arm/v7/opdefs/mov_A88102.d index ae67b22..d96baab 100644 --- a/src/arch/arm/v7/opdefs/mov_A88102.d +++ b/src/arch/arm/v7/opdefs/mov_A88102.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2014 Cyrille Bagard + * Copyright (C) 2015 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,105 +23,102 @@ @title MOV (immediate) -@encoding(t1) { +@desc Move (immediate) writes an immediate value to the destination register. It can optionally update the condition flags based on the value. - @half 0 0 1 0 0 Rd(3) imm8(8) +@encoding (t1) { - @syntax <Rd> <const> + @half 0 0 1 0 0 Rd(3) imm8(8) - @conv { + @syntax "movs" <reg_D> <imm32> - Rd = Register(Rd) - const = ZeroExtend(imm8, 8, 32) + @conv { - } + reg_D = Register(Rd) + imm32 = ZeroExtend(imm8, 32) + + } } -@encoding(T2) { +@encoding (T2) { - @word 1 1 1 1 0 i(1) 0 0 0 1 0 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm8(8) + @word 1 1 1 1 0 i(1) 0 0 0 1 0 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm8(8) - @syntax {S} ".W" <Rd> <const> + @syntax <reg_D> <imm32> - @conv { + @conv { - S = SetFlags(S) - Rd = Register(Rd) - const = ThumbExpandImm_C(i:imm3:imm8, 0) + reg_D = Register(Rd) + setflags = (S == '1') + imm32 = ThumbExpandImm_C(i:imm3:imm8, 0) - } + } - @rules { + @rules { - //if d IN {13,15} then UNPREDICTABLE; + if (setflags); chk_call ExtendKeyword("s") + chk_call ExtendKeyword(".w") - } + } } -@encoding(T3) { - - @word 1 1 1 1 0 i(1) 1 0 0 1 0 0 imm4(4) 0 imm3(3) Rd(4) imm8(8) - - @syntax <Rd> <const> +@encoding (T3) { - @conv { + @word 1 1 1 1 0 i(1) 1 0 0 1 0 0 imm4(4) 0 imm3(3) Rd(4) imm8(8) - Rd = Register(Rd) - const = ZeroExtend(imm4:i:imm3:imm8, 12, 32) + @syntax "movw" <reg_D> <imm32> - } + @conv { - @rules { + reg_D = Register(Rd) + imm32 = ZeroExtend(imm4:i:imm3:imm8, 32) - //if d IN {13,15} then UNPREDICTABLE; - - } + } } -@encoding(A1) { +@encoding (A1) { - @word cond(4) 0 0 1 1 1 0 1 S(1) 0 0 0 0 Rd(4) imm12(12) + @word cond(4) 0 0 1 1 1 0 1 S(1) 0 0 0 0 Rd(4) imm12(12) - @syntax {S} {c} <Rd> <const> + @syntax <reg_D> <imm32> - @conv { + @conv { - S = SetFlags(S) - c = Condition(cond) - Rd = Register(Rd) - const = ARMExpandImm_C(imm12, 0) + reg_D = Register(Rd) + setflags = (S == '1') + imm32 = ARMExpandImm_C(imm12, 0) - } + } - @rules { + @rules { - if ((Rd == '1111') && (S == '1')) ; see SUBS PC, LR and related instructions (ARM) + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) - } + } } -@encoding(A2) { +@encoding (A2) { - @word cond(4) 0 0 1 1 0 0 0 0 imm4(4) Rd(4) imm12(12) + @word cond(4) 0 0 1 1 0 0 0 0 imm4(4) Rd(4) imm12(12) - @syntax "movw" {c} <Rd> <const> + @syntax "movw" <reg_D> <imm32> - @conv { + @conv { - c = Condition(cond) - Rd = Register(Rd) - const = ZeroExtend(imm4:imm12, 16, 32) + reg_D = Register(Rd) + imm32 = ZeroExtend(imm4:imm12, 32) - } + } - @rules { + @rules { - //if d == 15 then UNPREDICTABLE; + chk_call StoreCondition(cond) - } + } } + |