diff options
Diffstat (limited to 'src/arch/arm/v7/opdefs/mul_A88114.d')
| -rw-r--r-- | src/arch/arm/v7/opdefs/mul_A88114.d | 68 |
1 files changed, 33 insertions, 35 deletions
diff --git a/src/arch/arm/v7/opdefs/mul_A88114.d b/src/arch/arm/v7/opdefs/mul_A88114.d index fb4fb43..fa250b7 100644 --- a/src/arch/arm/v7/opdefs/mul_A88114.d +++ b/src/arch/arm/v7/opdefs/mul_A88114.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2014 Cyrille Bagard + * Copyright (C) 2015 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,63 +23,61 @@ @title MUL -@encoding(t1) { +@desc Multiply multiplies two register values. The least significant 32 bits of the result are written to the destination register. These 32 bits do not depend on whether the source register values are considered to be signed values or unsigned values. Optionally, it can update the condition flags based on the result. In the Thumb instruction set, this option is limited to only a few forms of the instruction. Use of this option adversely affects performance on many processor implementations. - @half 0 1 0 0 0 0 1 1 0 1 Rn(3) Rdm(3) +@encoding (t1) { - @syntax <Rdm> <Rn> <Rdm> + @half 0 1 0 0 0 0 1 1 0 1 Rn(3) Rdm(3) - @conv { + @syntax "muls" <reg_DM_1> <reg_N> <reg_DM_2> - Rdm = Register(Rdm) - Rn = Register(Rn) + @conv { - } + reg_N = Register(Rn) + reg_DM_1 = Register(Rdm) + reg_DM_2 = Register(Rdm) -} - -@encoding(T2) { - - @word 1 1 1 1 1 0 1 1 0 0 0 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) + } - @syntax <Rd> <Rn> <Rm> +} - @conv { +@encoding (T2) { - Rd = Register(Rd) - Rn = Register(Rn) - Rm = Register(Rm) + @word 1 1 1 1 1 0 1 1 0 0 0 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) - } + @syntax <reg_D> <reg_N> <reg_M> - @rules { + @conv { - //if d IN {13,15} || n IN {13,15} || m IN {13,15} then UNPREDICTABLE + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } } -@encoding(A1) { +@encoding (A1) { - @word cond(4) 0 0 0 0 0 0 0 S(1) Rd(4) 0 0 0 0 Rm(4) 1 0 0 1 Rn(4) + @word cond(4) 0 0 0 0 0 0 0 S(1) Rd(4) 0 0 0 0 Rm(4) 1 0 0 1 Rn(4) - @syntax {S} {c} <Rd> <Rn> <Rm> + @syntax <reg_D> <reg_N> <reg_M> - @conv { + @conv { - S = SetFlags(S) - c = Condition(cond) - Rd = Register(Rd) - Rn = Register(Rn) - Rm = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') - } + } - @rules { + @rules { - //if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) - } + } } + |