diff options
Diffstat (limited to 'src/arch/arm/v7/opdefs/mvn_A88116.d')
| -rw-r--r-- | src/arch/arm/v7/opdefs/mvn_A88116.d | 70 |
1 files changed, 37 insertions, 33 deletions
diff --git a/src/arch/arm/v7/opdefs/mvn_A88116.d b/src/arch/arm/v7/opdefs/mvn_A88116.d index 3c97db4..1f3f390 100644 --- a/src/arch/arm/v7/opdefs/mvn_A88116.d +++ b/src/arch/arm/v7/opdefs/mvn_A88116.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2014 Cyrille Bagard + * Copyright (C) 2015 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,64 +23,68 @@ @title MVN (register) -@encoding(t1) { +@desc Bitwise NOT (register) writes the bitwise inverse of a register value to the destination register. It can optionally update the condition flags based on the result. - @half 0 1 0 0 0 0 1 1 1 1 Rm(3) Rd(3) +@encoding (t1) { - @syntax <Rd> <Rm> + @half 0 1 0 0 0 0 1 1 1 1 Rm(3) Rd(3) - @conv { + @syntax "mvns" <reg_D> <reg_M> - Rd = Register(Rd) - Rm = Register(Rm) + @conv { - } + reg_D = Register(Rd) + reg_M = Register(Rm) + + } } -@encoding(T2) { +@encoding (T2) { - @word 1 1 1 0 1 0 1 0 0 1 1 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) + @word 1 1 1 0 1 0 1 0 0 1 1 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - @syntax {S} <Rd> <Rm> <?shift> + @syntax <reg_D> <reg_M> <?shift> - @conv { + @conv { - S = SetFlags(S) - Rd = Register(Rd) - Rm = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) + reg_D = Register(Rd) + reg_M = Register(Rm) + setflags = (S == '1') + shift = DecodeImmShift(type, imm3:imm2) - } + } - @rules { + @rules { - //if d IN {13,15} || m IN {13,15} then UNPREDICTABLE + if (setflags); chk_call ExtendKeyword("s") + chk_call ExtendKeyword(".w") - } + } } -@encoding(A1) { +@encoding (A1) { - @word cond(4) 0 0 0 1 1 1 1 S(1) 0 0 0 0 Rd(4) imm5(5) type(2) 0 Rm(4) + @word cond(4) 0 0 0 1 1 1 1 S(1) 0 0 0 0 Rd(4) imm5(5) type(2) 0 Rm(4) - @syntax {S} {c} <Rd> <Rm> <?shift> + @syntax <reg_D> <reg_M> <?shift> - @conv { + @conv { - S = SetFlags(S) - c = Condition(cond) - Rd = Register(Rd) - Rm = Register(Rm) - shift = DecodeImmShift(type, imm5) + reg_D = Register(Rd) + reg_M = Register(Rm) + setflags = (S == '1') + shift = DecodeImmShift(type, imm5) - } + } - @rules { + @rules { - //if ((Rd == '1111') && (S == '1')) ; see SUBS PC, LR and related instructions + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) - } + } } + |