1 files changed, 21 insertions, 42 deletions
diff --git a/src/arch/arm/v7/opdefs/pop_A88131.d b/src/arch/arm/v7/opdefs/pop_A88131.d
index 47b9c2d..7de7ee4 100644
--- a/src/arch/arm/v7/opdefs/pop_A88131.d
+++ b/src/arch/arm/v7/opdefs/pop_A88131.d
@@ -2,7 +2,7 @@
 /* Chrysalide - Outil d'analyse de fichiers binaires
  * ##FILE## - traduction d'instructions ARMv7
  *
- * Copyright (C) 2014 Cyrille Bagard
+ * Copyright (C) 2015 Cyrille Bagard
  *
  *  This file is part of Chrysalide.
  *
@@ -23,68 +23,47 @@
 
 @title POP (Thumb)
 
-@encoding(t1) {
+@desc Pop Multiple Registers loads multiple registers from the stack, loading from consecutive memory locations starting at the address in SP, and updates SP to point just above the loaded data.
 
-    @half 1 0 1 1 1 1 0 P(1) register_list(8)
+@encoding (t1) {
 
-    @syntax <registers>
+	@half 1 0 1 1 1 1 0 P(1) register_list(8)
 
-    @conv {
+	@syntax <registers>
 
-        registers = RegistersList(P:'0000000':register_list)
+	@conv {
 
-    }
+		registers = RegistersList(P:'0000000':register_list)
 
-    @rules {
-
-        //if BitCount(registers) < 1 then UNPREDICTABLE;
-        //if registers<15> == '1' && InITBlock() && !LastInITBlock() then UNPREDICTABLE;
-        if (P == '1') ; chk_call SetInsFlag(AIF_RETURN_POINT)
-
-    }
+	}
 
 }
 
-@encoding(T2) {
-
-    @word 1 1 1 0 1 0 0 0 1 0 1 1 1 1 0 1 P(1) M(1) 0 register_list(13)
-
-    @syntax "pop.W" <registers>
-
-    @conv {
+@encoding (T2) {
 
-        registers = RegistersList(P:M:'0':register_list)
+	@word 1 1 1 0 1 0 0 0 1 0 1 1 1 1 0 1 P(1) M(1) 0 register_list(13)
 
-    }
+	@syntax ".W" <registers>
 
-    @rules {
+	@conv {
 
-        //if BitCount(registers) < 2 || (P == '1' && M == '1') then UNPREDICTABLE;
-        //if registers<15> == '1' && InITBlock() && !LastInITBlock() then UNPREDICTABLE;
-        if (P == '1') ; chk_call SetInsFlag(AIF_RETURN_POINT)
+		registers = RegistersList(P:M:'0':register_list)
 
-    }
+	}
 
 }
 
-@encoding(T3) {
+@encoding (T3) {
 
-    @word 1 1 1 1 1 0 0 0 0 1 0 1 1 1 0 1 Rt(4) 1 0 1 1 0 0 0 0 0 1 0 0
+	@word 1 1 1 1 1 0 0 0 0 1 0 1 1 1 0 1 Rt(4) 1 0 1 1 0 0 0 0 0 1 0 0
 
-    @syntax "pop.W" <registers>
+	@syntax ".W" <registers>
 
-    @conv {
+	@conv {
 
-        Rgt = Register(Rt)
-        registers = ListFromRegister(Rgt)
+		registers = Zeros(16)
 
-    }
-
-    @rules {
-
-        //if t == 13 || (t == 15 && InITBlock() && !LastInITBlock()) then UNPREDICTABLE;
-        if (Rt == '1111') ; chk_call SetInsFlag(AIF_RETURN_POINT)
-
-    }
+	}
 
 }
+