diff options
Diffstat (limited to 'src/arch/arm/v7/opdefs/rsb_A88152.d')
| -rw-r--r-- | src/arch/arm/v7/opdefs/rsb_A88152.d | 72 |
1 files changed, 38 insertions, 34 deletions
diff --git a/src/arch/arm/v7/opdefs/rsb_A88152.d b/src/arch/arm/v7/opdefs/rsb_A88152.d index f7bee59..ea53373 100644 --- a/src/arch/arm/v7/opdefs/rsb_A88152.d +++ b/src/arch/arm/v7/opdefs/rsb_A88152.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2014 Cyrille Bagard + * Copyright (C) 2015 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,65 +23,69 @@ @title RSB (immediate) -@encoding(t1) { +@desc Reverse Subtract (immediate) subtracts a register value from an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - @half 0 1 0 0 0 0 1 0 0 1 Rn(3) Rd(3) +@encoding (t1) { - @syntax <Rd> <Rn> <zero> + @half 0 1 0 0 0 0 1 0 0 1 Rn(3) Rd(3) - @conv { + @syntax "rsbs" <reg_D> <reg_N> <imm32> - Rd = Register(Rd) - Rn = Register(Rn) - zero = Zeros(32) + @conv { - } + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = Zeros(32) + + } } -@encoding(T2) { +@encoding (T2) { - @word 1 1 1 1 0 i(1) 0 1 1 1 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) + @word 1 1 1 1 0 i(1) 0 1 1 1 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - @syntax {S} <Rd> <Rn> <const> + @syntax <reg_D> <reg_N> <imm32> - @conv { + @conv { - S = SetFlags(S) - Rd = Register(Rd) - Rn = Register(Rn) - const = ThumbExpandImm(i:imm3:imm8) + reg_D = Register(Rd) + reg_N = Register(Rn) + setflags = (S == '1') + imm32 = ThumbExpandImm(i:imm3:imm8) - } + } - @rules { + @rules { - //if ((d IN {13,15}) || (n IN {13,15})) ; unpredictable + if (setflags); chk_call ExtendKeyword("s") + chk_call ExtendKeyword(".w") - } + } } -@encoding(A1) { +@encoding (A1) { - @word cond(4) 0 0 1 0 0 1 1 S(1) Rn(4) Rd(4) imm12(12) + @word cond(4) 0 0 1 0 0 1 1 S(1) Rn(4) Rd(4) imm12(12) - @syntax {S} {c} <Rd> <Rn> + @syntax <reg_D> <reg_N> <imm32> - @conv { + @conv { - S = SetFlags(S) - c = Condition(cond) - Rd = Register(Rd) - Rn = Register(Rn) - const = ARMExpandImm(imm12) + reg_D = Register(Rd) + reg_N = Register(Rn) + setflags = (S == '1') + imm32 = ARMExpandImm(imm12) - } + } - @rules { + @rules { - //if ((Rd == '1111') && (S == '1')) ; see SUBS PC, LR and related instructions + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) - } + } } + |