diff options
Diffstat (limited to 'src/arch/arm/v7/opdefs/sub_A88222.d')
| -rw-r--r-- | src/arch/arm/v7/opdefs/sub_A88222.d | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/src/arch/arm/v7/opdefs/sub_A88222.d b/src/arch/arm/v7/opdefs/sub_A88222.d index 5564a07..ef326b8 100644 --- a/src/arch/arm/v7/opdefs/sub_A88222.d +++ b/src/arch/arm/v7/opdefs/sub_A88222.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2014 Cyrille Bagard + * Copyright (C) 2015 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,29 +23,29 @@ @title SUB (immediate, ARM) -@encoding(A1) { +@desc This instruction subtracts an immediate value from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - @word cond(4) 0 0 1 0 0 1 0 S(1) Rn(4) Rd(4) imm12(12) +@encoding (A1) { - @syntax {S} {c} <Rd> <Rn> <const> + @word cond(4) 0 0 1 0 0 1 0 S(1) Rn(4) Rd(4) imm12(12) - @conv { + @syntax <reg_D> <reg_N> <imm32> - S = SetFlags(S) - c = Condition(cond) - Rd = Register(Rd) - Rn = Register(Rn) - const = ARMExpandImm(imm12) + @conv { - } + reg_D = Register(Rd) + reg_N = Register(Rn) + setflags = (S == '1') + imm32 = ARMExpandImm(imm12) - @rules { + } - //if ((Rn == '1111') && (S == '0')) ; see ADR - //if (Rn == '1101') ; see SUB (SP minus immediate) - //if ((Rd == '1111') && (S == '1')) ; see SUBS PC, LR and related instructions + @rules { + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) - } + } } + |