1 files changed, 41 insertions, 41 deletions
diff --git a/src/arch/arm/v7/opdefs/sub_A88223.d b/src/arch/arm/v7/opdefs/sub_A88223.d
index 3693bc4..a629250 100644
--- a/src/arch/arm/v7/opdefs/sub_A88223.d
+++ b/src/arch/arm/v7/opdefs/sub_A88223.d
@@ -2,7 +2,7 @@
 /* Chrysalide - Outil d'analyse de fichiers binaires
  * ##FILE## - traduction d'instructions ARMv7
  *
- * Copyright (C) 2014 Cyrille Bagard
+ * Copyright (C) 2015 Cyrille Bagard
  *
  *  This file is part of Chrysalide.
  *
@@ -23,71 +23,71 @@
 
 @title SUB (register)
 
-@encoding(t1) {
+@desc This instruction subtracts an optionally-shifted register value from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result.
 
-    @half 0 0 0 1 1 0 1 Rm(3) Rn(3) Rd(3)
+@encoding (t1) {
 
-    @syntax <Rd> <Rn> <Rm>
+	@half 0 0 0 1 1 0 1 Rm(3) Rn(3) Rd(3)
 
-    @conv {
+	@syntax "subs" <reg_D> <reg_N> <reg_M>
 
-        Rd = Register(Rd)
-        Rn = Register(Rn)
-        Rm = Register(Rm)
+	@conv {
 
-    }
+		reg_D = Register(Rd)
+		reg_N = Register(Rn)
+		reg_M = Register(Rm)
+
+	}
 
 }
 
-@encoding(T2) {
+@encoding (T2) {
 
-    @word 1 1 1 0 1 0 1 1 1 0 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4)
+	@word 1 1 1 0 1 0 1 1 1 0 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4)
 
-    @syntax {S} <Rd> <Rn> <Rm> <?shift>
+	@syntax <reg_D> <reg_N> <reg_M> <?shift>
 
-    @conv {
+	@conv {
 
-        S = SetFlags(S)
-        Rd = Register(Rd)
-        Rn = Register(Rn)
-        Rm = Register(Rm)
-        shift = DecodeImmShift(type, imm3:imm2)
+		reg_D = Register(Rd)
+		reg_N = Register(Rn)
+		reg_M = Register(Rm)
+		setflags = (S == '1')
+		shift = DecodeImmShift(type, imm3:imm2)
 
-    }
+	}
 
-    @rules {
-        
-        //if ((Rd == '1111') && (S == '1')) ; see CMP (register)
-        //if (Rn == '1101') ; see SUB (SP minus register)
-        //if ((d == 13) || ((d == 15) && (S == '0')) [[ n == 15 || (m IN {13,15})) ; unpredictable
+	@rules {
 
-    }
+		if (setflags); chk_call ExtendKeyword("s")
+		chk_call ExtendKeyword(".w")
 
-}
+	}
 
-@encoding(A1) {
+}
 
-    @word cond(4) 0 0 0 0 0 1 0 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4)
+@encoding (A1) {
 
-    @syntax {S} {c} <Rd> <Rn> <Rm> <?shift>
+	@word cond(4) 0 0 0 0 0 1 0 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4)
 
-    @conv {
+	@syntax <reg_D> <reg_N> <reg_M> <?shift>
 
-        S = SetFlags(S)
-        c = Condition(cond)
-        Rd = Register(Rd)
-        Rn = Register(Rn)
-        Rm = Register(Rm)
-        shift = DecodeImmShift(type, imm5)
+	@conv {
 
-    }
+		reg_D = Register(Rd)
+		reg_N = Register(Rn)
+		reg_M = Register(Rm)
+		setflags = (S == '1')
+		shift = DecodeImmShift(type, imm5)
 
-    @rules {
+	}
 
-        //if (Rn == '1101') ; see SUB (SP minus register)
-        //if ((Rd == '1111') && (S == '1')) ; see SUBS PC, LR and related instructions
+	@rules {
 
+		if (setflags); chk_call ExtendKeyword("s")
+		chk_call StoreCondition(cond)
 
-    }
+	}
 
 }
+