diff options
Diffstat (limited to 'src/arch/arm/v7/opdefs/teq_A88238.d')
| -rw-r--r-- | src/arch/arm/v7/opdefs/teq_A88238.d | 46 |
1 files changed, 24 insertions, 22 deletions
diff --git a/src/arch/arm/v7/opdefs/teq_A88238.d b/src/arch/arm/v7/opdefs/teq_A88238.d index a79eb3e..8187d81 100644 --- a/src/arch/arm/v7/opdefs/teq_A88238.d +++ b/src/arch/arm/v7/opdefs/teq_A88238.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2014 Cyrille Bagard + * Copyright (C) 2015 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,41 +23,43 @@ @title TEQ (register) -@encoding(T1) { +@desc Test Equivalence (register) performs a bitwise exclusive OR operation on a register value and an optionally-shifted register value. It updates the condition flags based on the result, and discards the result. - @word 1 1 1 0 1 0 1 0 1 0 0 1 Rn(4) 0 imm3(3) 1 1 1 1 imm2(2) type(2) Rm(4) +@encoding (T1) { - @syntax <Rn> <Rm> <?shift> + @word 1 1 1 0 1 0 1 0 1 0 0 1 Rn(4) 0 imm3(3) 1 1 1 1 imm2(2) type(2) Rm(4) - @conv { + @syntax <reg_N> <reg_M> <?shift> - Rn = Register(Rn) - Rm = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) + @conv { - } + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) - @rules { + } - //if n IN {13,15} || m IN {13,15} then UNPREDICTABLE +} - } +@encoding (A1) { -} + @word cond(4) 0 0 0 1 0 0 1 1 Rn(4) 0 0 0 0 imm5(5) type(2) 0 Rm(4) -@encoding(A1) { + @syntax <reg_N> <reg_M> <?shift> - @word cond(4) 0 0 0 1 0 0 1 1 Rn(4) 0 0 0 0 imm5(5) type(2) 0 Rm(4) + @conv { - @syntax {c} <Rn> <Rm> <?shift> + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) - @conv { + } - c = Condition(cond) - Rn = Register(Rn) - Rm = Register(Rm) - shift = DecodeImmShift(type, imm5) + @rules { - } + chk_call StoreCondition(cond) + + } } + |