diff options
Diffstat (limited to 'src/arch/arm/v7/opdefs/tst_A88241.d')
-rw-r--r-- | src/arch/arm/v7/opdefs/tst_A88241.d | 64 |
1 files changed, 30 insertions, 34 deletions
diff --git a/src/arch/arm/v7/opdefs/tst_A88241.d b/src/arch/arm/v7/opdefs/tst_A88241.d index 070fcb3..8777d06 100644 --- a/src/arch/arm/v7/opdefs/tst_A88241.d +++ b/src/arch/arm/v7/opdefs/tst_A88241.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2014 Cyrille Bagard + * Copyright (C) 2015 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,62 +23,58 @@ @title TST (register) -@encoding(t1) { +@desc Test (register) performs a bitwise AND operation on a register value and an optionally-shifted register value. It updates the condition flags based on the result, and discards the result. - @half 0 1 0 0 0 0 1 0 0 0 Rm(3) Rn(3) +@encoding (t1) { - @syntax <Rn> <Rm> + @half 0 1 0 0 0 0 1 0 0 0 Rm(3) Rn(3) - @conv { + @syntax <reg_N> <reg_M> - Rn = Register(Rn) - Rm = Register(Rm) + @conv { - } + reg_N = Register(Rn) + reg_M = Register(Rm) -} - -@encoding(T2) { - - @word 1 1 1 0 1 0 1 0 0 0 0 1 Rn(4) 0 imm3(3) 1 1 1 1 imm2(2) type(2) Rm(4) + } - @syntax <Rn> <Rm> <?shift> +} - @conv { +@encoding (T2) { - Rn = Register(Rn) - Rm = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) + @word 1 1 1 0 1 0 1 0 0 0 0 1 Rn(4) 0 imm3(3) 1 1 1 1 imm2(2) type(2) Rm(4) - } + @syntax ".W" <reg_N> <reg_M> <?shift> - @rules { + @conv { - //if n IN {13,15} || m IN {13,15} then UNPREDICTABLE + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) - } + } } -@encoding(A1) { +@encoding (A1) { - @word cond(4) 0 0 0 1 0 0 0 1 Rn(4) 0 0 0 0 imm5(5) type(2) 0 Rm(4) + @word cond(4) 0 0 0 1 0 0 0 1 Rn(4) 0 0 0 0 imm5(5) type(2) 0 Rm(4) - @syntax {c} <Rn> <Rm> <?shift> + @syntax <reg_N> <reg_M> <?shift> - @conv { + @conv { - c = Condition(cond) - Rn = Register(Rn) - Rm = Register(Rm) - shift = DecodeImmShift(type, imm5) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) - } + } - @rules { + @rules { - //if ((Rd == '1111') && (S == '1')) ; see SUBS PC, LR and related instructions + chk_call StoreCondition(cond) - } + } } + |