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/* Chrysalide - Outil d'analyse de fichiers binaires
* ##FILE## - traduction d'instructions ARMv7
*
* Copyright (C) 2017 Cyrille Bagard
*
* This file is part of Chrysalide.
*
* Chrysalide is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* Chrysalide is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Chrysalide. If not, see <http://www.gnu.org/licenses/>.
*/
@title VEOR
@id 307
@desc {
Vector Bitwise Exclusive OR performs a bitwise Exclusive OR operation between two registers, and places the result in the destination register. The operand and result registers can be quadword or doubleword. They must all be the same size. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of access controls for Advanced SIMD functionality on page B1-1232 summarizes these controls. ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available as a VFP instruction encoding, see Conditional execution on page A8-288.
}
@encoding (T1) {
@word 1 1 1 1 1 1 1 1 0 D(1) 0 0 Vn(4) Vd(4) 0 0 0 1 N(1) Q(1) M(1) 1 Vm(4)
@syntax {
@subid 1293
@assert {
Q == 1
}
@conv {
qwvec_D = QuadWordVector(D:Vd)
qwvec_N = QuadWordVector(N:Vn)
qwvec_M = QuadWordVector(M:Vm)
}
@asm veor ?qwvec_D qwvec_N qwvec_M
}
@syntax {
@subid 1294
@assert {
Q == 0
}
@conv {
dwvec_D = DoubleWordVector(D:Vd)
dwvec_N = DoubleWordVector(N:Vn)
dwvec_M = DoubleWordVector(M:Vm)
}
@asm veor ?dwvec_D dwvec_N dwvec_M
}
}
@encoding (A1) {
@word 1 1 1 1 1 1 1 1 0 D(1) 0 0 Vn(4) Vd(4) 0 0 0 1 N(1) Q(1) M(1) 1 Vm(4)
@syntax {
@subid 1295
@assert {
Q == 1
}
@conv {
qwvec_D = QuadWordVector(D:Vd)
qwvec_N = QuadWordVector(N:Vn)
qwvec_M = QuadWordVector(M:Vm)
}
@asm veor ?qwvec_D qwvec_N qwvec_M
}
@syntax {
@subid 1296
@assert {
Q == 0
}
@conv {
dwvec_D = DoubleWordVector(D:Vd)
dwvec_N = DoubleWordVector(N:Vn)
dwvec_M = DoubleWordVector(M:Vm)
}
@asm veor ?dwvec_D dwvec_N dwvec_M
}
}
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