blob: e0a6708358740f8f43cc42dbea75309edc6d7a00 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
|
/* Chrysalide - Outil d'analyse de fichiers binaires
* ##FILE## - traduction d'instructions ARMv7
*
* Copyright (C) 2017 Cyrille Bagard
*
* This file is part of Chrysalide.
*
* Chrysalide is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* Chrysalide is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Chrysalide. If not, see <http://www.gnu.org/licenses/>.
*/
@title VSQRT
@id 339
@desc {
This instruction calculates the square root of the value in a floating-point register and writes the result to another floating-point register. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of general controls of CP10 and CP11 functionality on page B1-1230 summarizes these controls.
}
@encoding (T1) {
@word 1 1 1 0 1 1 1 0 1 D(1) 1 1 0 0 0 1 Vd(4) 1 0 1 sz(1) 1 1 M(1) 0 Vm(4)
@syntax {
@subid 1877
@assert {
sz == 1
}
@conv {
dwvec_D = DoubleWordVector(D:Vd)
dwvec_M = DoubleWordVector(M:Vm)
}
@asm vsqrt.f64 dwvec_D dwvec_M
}
@syntax {
@subid 1878
@assert {
sz == 0
}
@conv {
swvec_D = SingleWordVector(Vd:D)
swvec_M = SingleWordVector(Vm:M)
}
@asm vsqrt.f32 swvec_D swvec_M
}
}
@encoding (A1) {
@word 1 1 1 0 1 1 1 0 1 D(1) 1 1 0 0 0 1 Vd(4) 1 0 1 sz(1) 1 1 M(1) 0 Vm(4)
@syntax {
@subid 1879
@assert {
sz == 1
}
@conv {
dwvec_D = DoubleWordVector(D:Vd)
dwvec_M = DoubleWordVector(M:Vm)
}
@asm vsqrt.f64 dwvec_D dwvec_M
}
@syntax {
@subid 1880
@assert {
sz == 0
}
@conv {
swvec_D = SingleWordVector(Vd:D)
swvec_M = SingleWordVector(Vm:M)
}
@asm vsqrt.f32 swvec_D swvec_M
}
}
|
