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/* Chrysalide - Outil d'analyse de fichiers binaires
* ##FILE## - traduction d'instructions ARMv7
*
* Copyright (C) 2015 Cyrille Bagard
*
* This file is part of Chrysalide.
*
* Chrysalide is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* Chrysalide is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Foobar. If not, see <http://www.gnu.org/licenses/>.
*/
@title ASR (register)
@desc Arithmetic Shift Right (register) shifts a register value right by a variable number of bits, shifting in copies of its sign bit, and writes the result to the destination register. The variable number of bits is read from the bottom byte of a register. It can optionally update the condition flags based on the result.
@encoding (t1) {
@half 0 1 0 0 0 0 0 1 0 0 Rm(3) Rdn(3)
@syntax "asrs" <reg_DN> <reg_M>
@conv {
reg_DN = Register(Rdn)
reg_M = Register(Rm)
}
}
@encoding (T2) {
@word 1 1 1 1 1 0 1 0 0 1 0 S(1) Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4)
@syntax <reg_D> <reg_N> <reg_M>
@conv {
reg_D = Register(Rd)
reg_N = Register(Rn)
reg_M = Register(Rm)
setflags = (S == '1')
}
@rules {
if (setflags); chk_call ExtendKeyword("s")
chk_call ExtendKeyword(".w")
}
}
@encoding (A1) {
@word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) Rm(4) 0 1 0 1 Rn(4)
@syntax <reg_D> <reg_N> <reg_M>
@conv {
reg_D = Register(Rd)
reg_N = Register(Rn)
reg_M = Register(Rm)
setflags = (S == '1')
}
@rules {
if (setflags); chk_call ExtendKeyword("s")
chk_call StoreCondition(cond)
}
}
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