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/* Chrysalide - Outil d'analyse de fichiers binaires
* ##FILE## - traduction d'instructions ARMv7
*
* Copyright (C) 2017 Cyrille Bagard
*
* This file is part of Chrysalide.
*
* Chrysalide is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* Chrysalide is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Chrysalide. If not, see <http://www.gnu.org/licenses/>.
*/
@title MSR (register)
@id 111
@desc {
Move to Special register from ARM core register moves selected bits of an ARM core register to the APSR. For details of system level use of this instruction, see MSR (register) on page B9-1996.
}
@encoding (T1) {
@word 1 1 1 1 0 0 1 1 1 0 0 0 Rn(4) 1 0 0 0 mask(2) 0 0 0 0 0 0 0 0 0 0
@syntax {
@subid 336
@conv {
spec_reg = SpecRegFromMask(mask)
reg_N = Register(Rn)
}
@asm msr spec_reg reg_N
}
}
@encoding (A1) {
@word cond(4) 0 0 0 1 0 0 1 0 mask(2) 0 0 1 1 1 1 0 0 0 0 0 0 0 0 Rn(4)
@syntax {
@subid 337
@conv {
spec_reg = SpecRegFromMask(mask)
reg_N = Register(Rn)
}
@asm msr spec_reg reg_N
@rules {
check g_arm_instruction_set_cond(cond)
}
}
}
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