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/* Chrysalide - Outil d'analyse de fichiers binaires
 * ##FILE## - traduction d'instructions ARMv7
 *
 * Copyright (C) 2014 Cyrille Bagard
 *
 *  This file is part of Chrysalide.
 *
 *  Chrysalide is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 3 of the License, or
 *  (at your option) any later version.
 *
 *  Chrysalide is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with Foobar.  If not, see <http://www.gnu.org/licenses/>.
 */


@title SUB (SP minus immediate)

@encoding(t1) {

    @half 1 0 1 1 0 0 0 0 1 imm7(7)

    @syntax <SP1> <SP2> <const>

    @conv {

        SP1 = Register(13)
        SP2 = Register(13)
        const = ZeroExtend(imm7:'00', 9, 32);

    }

    @rules {

        //setflags = FALSE

    }

}

@encoding(T2) {

    @word 1 1 1 1 0 i(1) 0 1 1 0 1 S(1) 1 1 0 1 0 imm3(3) Rd(4) imm8(8)

    @syntax {S} ".W" <Rd> <SP> <const>

    @conv {

        S = SetFlags(S)
        Rd = Register(Rd)
        SP = Register(13)
        const = ThumbExpandImm(i:imm3:imm8)

    }

    @rules {

        //if Rd == '1111' && S == '1' then SEE CMP (immediate);
        //if d == 15 && S == '0' then UNPREDICTABLE;

    }

}

@encoding(T3) {

    @word 1 1 1 1 0 i(1) 1 0 1 0 1 0 1 1 0 1 0 imm3(3) Rd(4) imm8(8)

    @syntax "subw" <Rd> <SP> <const>

    @conv {

        Rd = Register(Rd)
        SP = Register(13)
        const = ZeroExtend(i:imm3:imm8, 12, 32)

    }

    @rules {

        //if d == 15 then UNPREDICTABLE;

    }

}

@encoding(A1) {

    @word cond(4) 0 0 1 0 0 1 0 S(1) 1 1 0 1 Rd(4) imm12(12)

    @syntax {S} {c} <Rd> <SP> <const>

    @conv {

        S = SetFlags(S)
        c = Condition(cond)
        Rd = Register(Rd)
        SP = Register(13)
        const = ARMExpandImm(imm12)

    }

    @rules {

        //if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;

    }

}