summaryrefslogtreecommitdiff
path: root/src/arch/mips/instruction.h
blob: 3edea639873af524980a4d5a960ee41075f33069 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105

/* Chrysalide - Outil d'analyse de fichiers binaires
 * instruction.h - prototypes pour la gestion des instructions de l'architecture MIPS
 *
 * Copyright (C) 2009-2017 Cyrille Bagard
 *
 *  This file is part of Chrysalide.
 *
 *  Chrysalide is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 3 of the License, or
 *  (at your option) any later version.
 *
 *  Chrysalide is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with Foobar.  If not, see <http://www.gnu.org/licenses/>.
 */


#ifndef _ARCH_MIPS_INSTRUCTION_H
#define _ARCH_MIPS_INSTRUCTION_H


#include "../instruction.h"






/* Enumération de tous les opcodes */
typedef enum _MipsOpcodes
{
    MOP_NOP,                                /* nop (0x00 ... 0x00)         */

    MOP_SRA,                                /* sra (0x00 ... 0x03)         */

    MOP_JR,                                 /* jr (0x00 ... 0x08)          */
    MOP_JALR,                               /* jalr (0x00 ... 0x09)        */
    MOP_JALR_HB,                            /* jalr.hb (0x00 ... 0x09)     */


    MOP_ADDU,                               /* addu (0x00 ... 0x21)        */
    MOP_SUB,                                /* sub (0x00 ... 0x22)         */
    MOP_SUBU,                               /* subu (0x00 ... 0x23)        */

    MOP_AND,                                /* and (0x00 ... 0x24)         */

    MOP_BGEZAL,                             /* bgezal (0x04 ... 0x11 ...)  */

    MOP_BEQ,                                /* beq (0x10)                  */
    MOP_BNE,                                /* bne (0x14)                  */

    MOP_ADDIU,                              /* addiu (0x24)                */

    MOP_BEQL,                               /* beql (0x50)                 */

    MOP_LW,                                 /* lw (0x8c)                   */
    MOP_LUI,                                /* lui (0x3c)                  */

    MOP_LBU,                                /* lbu (0x90)                  */

    MOP_SB,                                 /* sb (0xa0)                   */
    MOP_SW,                                 /* sw (0xac)                   */

    MOP_COUNT


} MipsOpcodes;


#define G_TYPE_MIPS_INSTRUCTION                 g_mips_instruction_get_type()
#define G_MIPS_INSTRUCTION(obj)                 (G_TYPE_CHECK_INSTANCE_CAST((obj), g_mips_instruction_get_type(), GMipsInstruction))
#define G_IS_MIPS_INSTRUCTION(obj)              (G_TYPE_CHECK_INSTANCE_TYPE((obj), g_mips_instruction_get_type()))
#define G_MIPS_INSTRUCTION_GET_IFACE(inst)      (G_TYPE_INSTANCE_GET_INTERFACE((inst), g_mips_instruction_get_type(), GMipsInstructionIface))


/* Définition générique d'une instruction d'architecture MIPS (instance) */
typedef struct _GMipsInstruction GMipsInstruction;

/* Définition générique d'une instruction d'architecture MIPS (classe) */
typedef struct _GMipsInstructionClass GMipsInstructionClass;


/* Indique le type défini pour une instruction d'architecture MIPS. */
GType g_mips_instruction_get_type(void);

/* Crée une instruction pour l'architecture MIPS. */
GArchInstruction *g_mips_instruction_new(MipsOpcodes);



/* --------------------- AIDE A LA MISE EN PLACE D'INSTRUCTIONS --------------------- */


/* Recherche l'identifiant de la prochaine instruction. */
MipsOpcodes mips_guess_next_instruction(const bin_t *, off_t, off_t);



#endif  /* _ARCH_MIPS_INSTRUCTION_H */