Supported a few extra ARMv7 SIMD instructions.

1 files changed, 441 insertions, 0 deletions

diff --git a/plugins/arm/v7/opdefs/A88374_vqmov.d b/plugins/arm/v7/opdefs/A88374_vqmov.d
new file mode 100644
index 0000000..32a2dd0
--- /dev/null
+++ b/plugins/arm/v7/opdefs/A88374_vqmov.d
@@ -0,0 +1,441 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2017 Cyrille Bagard
+ *
+ *  This file is part of Chrysalide.
+ *
+ *  Chrysalide is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  Chrysalide is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Chrysalide.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title VQMOVN, VQMOVUN
+
+@id 341
+
+@desc {
+
+	Vector Saturating Move and Narrow copies each element of the operand vector to the corresponding element of the destination vector. The operand is a quadword vector. The elements can be any one of: • 16-bit, 32-bit, or 64-bit signed integers • 16-bit, 32-bit, or 64-bit unsigned integers. The result is a doubleword vector. The elements are half the length of the operand vector elements. If the operand is unsigned, the results are unsigned. If the operand is signed, the results can be signed or unsigned. If any of the results overflow, they are saturated. The cumulative saturation bit, FPSCR.QC, is set if saturation occurs. For details see Pseudocode details of saturation on page A2-44. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of access controls for Advanced SIMD functionality on page B1-1232 summarizes these controls. ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available as a VFP instruction encoding, see Conditional execution on page A8-288.
+
+}
+
+@encoding (T1) {
+
+	@word 1 1 1 1 1 1 1 1 1 D(1) 1 1 size(2) 1 0 Vd(4) 0 0 1 0 op(2) M(1) 0 Vm(4)
+
+	@syntax {
+
+		@subid 1851
+
+		@assert {
+
+			op == 1
+			size == 0
+
+		}
+
+		@conv {
+
+			dwvec_D = DoubleWordVector(D:Vd)
+			qwvec_M = QuadWordVector(M:Vm)
+
+		}
+
+		@asm vqmovun.s16 dwvec_D qwvec_M
+
+	}
+
+	@syntax {
+
+		@subid 1852
+
+		@assert {
+
+			op == 1
+			size == 1
+
+		}
+
+		@conv {
+
+			dwvec_D = DoubleWordVector(D:Vd)
+			qwvec_M = QuadWordVector(M:Vm)
+
+		}
+
+		@asm vqmovun.s32 dwvec_D qwvec_M
+
+	}
+
+	@syntax {
+
+		@subid 1853
+
+		@assert {
+
+			op == 1
+			size == 10
+
+		}
+
+		@conv {
+
+			dwvec_D = DoubleWordVector(D:Vd)
+			qwvec_M = QuadWordVector(M:Vm)
+
+		}
+
+		@asm vqmovun.s64 dwvec_D qwvec_M
+
+	}
+
+	@syntax {
+
+		@subid 1854
+
+		@assert {
+
+			op == 10
+			size == 0
+
+		}
+
+		@conv {
+
+			dwvec_D = DoubleWordVector(D:Vd)
+			qwvec_M = QuadWordVector(M:Vm)
+
+		}
+
+		@asm vqmovn.s16 dwvec_D qwvec_M
+
+	}
+
+	@syntax {
+
+		@subid 1855
+
+		@assert {
+
+			op == 10
+			size == 1
+
+		}
+
+		@conv {
+
+			dwvec_D = DoubleWordVector(D:Vd)
+			qwvec_M = QuadWordVector(M:Vm)
+
+		}
+
+		@asm vqmovn.s32 dwvec_D qwvec_M
+
+	}
+
+	@syntax {
+
+		@subid 1856
+
+		@assert {
+
+			op == 10
+			size == 10
+
+		}
+
+		@conv {
+
+			dwvec_D = DoubleWordVector(D:Vd)
+			qwvec_M = QuadWordVector(M:Vm)
+
+		}
+
+		@asm vqmovn.s64 dwvec_D qwvec_M
+
+	}
+
+	@syntax {
+
+		@subid 1857
+
+		@assert {
+
+			op == 11
+			size == 0
+
+		}
+
+		@conv {
+
+			dwvec_D = DoubleWordVector(D:Vd)
+			qwvec_M = QuadWordVector(M:Vm)
+
+		}
+
+		@asm vqmovn.u16 dwvec_D qwvec_M
+
+	}
+
+	@syntax {
+
+		@subid 1858
+
+		@assert {
+
+			op == 11
+			size == 1
+
+		}
+
+		@conv {
+
+			dwvec_D = DoubleWordVector(D:Vd)
+			qwvec_M = QuadWordVector(M:Vm)
+
+		}
+
+		@asm vqmovn.u32 dwvec_D qwvec_M
+
+	}
+
+	@syntax {
+
+		@subid 1859
+
+		@assert {
+
+			op == 11
+			size == 10
+
+		}
+
+		@conv {
+
+			dwvec_D = DoubleWordVector(D:Vd)
+			qwvec_M = QuadWordVector(M:Vm)
+
+		}
+
+		@asm vqmovn.u64 dwvec_D qwvec_M
+
+	}
+
+}
+
+@encoding (A1) {
+
+	@word 1 1 1 1 1 1 1 1 1 D(1) 1 1 size(2) 1 0 Vd(4) 0 0 1 0 op(2) M(1) 0 Vm(4)
+
+	@syntax {
+
+		@subid 1860
+
+		@assert {
+
+			op == 1
+			size == 0
+
+		}
+
+		@conv {
+
+			dwvec_D = DoubleWordVector(D:Vd)
+			qwvec_M = QuadWordVector(M:Vm)
+
+		}
+
+		@asm vqmovun.s16 dwvec_D qwvec_M
+
+	}
+
+	@syntax {
+
+		@subid 1861
+
+		@assert {
+
+			op == 1
+			size == 1
+
+		}
+
+		@conv {
+
+			dwvec_D = DoubleWordVector(D:Vd)
+			qwvec_M = QuadWordVector(M:Vm)
+
+		}
+
+		@asm vqmovun.s32 dwvec_D qwvec_M
+
+	}
+
+	@syntax {
+
+		@subid 1862
+
+		@assert {
+
+			op == 1
+			size == 10
+
+		}
+
+		@conv {
+
+			dwvec_D = DoubleWordVector(D:Vd)
+			qwvec_M = QuadWordVector(M:Vm)
+
+		}
+
+		@asm vqmovun.s64 dwvec_D qwvec_M
+
+	}
+
+	@syntax {
+
+		@subid 1863
+
+		@assert {
+
+			op == 10
+			size == 0
+
+		}
+
+		@conv {
+
+			dwvec_D = DoubleWordVector(D:Vd)
+			qwvec_M = QuadWordVector(M:Vm)
+
+		}
+
+		@asm vqmovn.s16 dwvec_D qwvec_M
+
+	}
+
+	@syntax {
+
+		@subid 1864
+
+		@assert {
+
+			op == 10
+			size == 1
+
+		}
+
+		@conv {
+
+			dwvec_D = DoubleWordVector(D:Vd)
+			qwvec_M = QuadWordVector(M:Vm)
+
+		}
+
+		@asm vqmovn.s32 dwvec_D qwvec_M
+
+	}
+
+	@syntax {
+
+		@subid 1865
+
+		@assert {
+
+			op == 10
+			size == 10
+
+		}
+
+		@conv {
+
+			dwvec_D = DoubleWordVector(D:Vd)
+			qwvec_M = QuadWordVector(M:Vm)
+
+		}
+
+		@asm vqmovn.s64 dwvec_D qwvec_M
+
+	}
+
+	@syntax {
+
+		@subid 1866
+
+		@assert {
+
+			op == 11
+			size == 0
+
+		}
+
+		@conv {
+
+			dwvec_D = DoubleWordVector(D:Vd)
+			qwvec_M = QuadWordVector(M:Vm)
+
+		}
+
+		@asm vqmovn.u16 dwvec_D qwvec_M
+
+	}
+
+	@syntax {
+
+		@subid 1867
+
+		@assert {
+
+			op == 11
+			size == 1
+
+		}
+
+		@conv {
+
+			dwvec_D = DoubleWordVector(D:Vd)
+			qwvec_M = QuadWordVector(M:Vm)
+
+		}
+
+		@asm vqmovn.u32 dwvec_D qwvec_M
+
+	}
+
+	@syntax {
+
+		@subid 1868
+
+		@assert {
+
+			op == 11
+			size == 10
+
+		}
+
+		@conv {
+
+			dwvec_D = DoubleWordVector(D:Vd)
+			qwvec_M = QuadWordVector(M:Vm)
+
+		}
+
+		@asm vqmovn.u64 dwvec_D qwvec_M
+
+	}
+
+}
+