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authorCyrille Bagard <nocbos@gmail.com>2018-05-30 17:15:13 (GMT)
committerCyrille Bagard <nocbos@gmail.com>2018-05-30 17:15:13 (GMT)
commitc492a5c94cc20210bce8069db7235cbb7dd691e9 (patch)
tree1521acfdfdd9bb6760c618fde460a6a63dff6d7b /plugins/arm
parentce3676d7c298c124253b32beeaebe2437a8ce8de (diff)
Supported a few extra ARMv7 SIMD instructions.
Diffstat (limited to 'plugins/arm')
-rw-r--r--plugins/arm/v7/helpers.h77
-rw-r--r--plugins/arm/v7/opcodes/opcodes_tmp_arm.h13
-rw-r--r--plugins/arm/v7/opcodes/opcodes_tmp_thumb_32.h13
-rw-r--r--plugins/arm/v7/opdefs/A88109_mrs.d4
-rw-r--r--plugins/arm/v7/opdefs/A88184_smmla.d16
-rw-r--r--plugins/arm/v7/opdefs/A88185_smmls.d16
-rw-r--r--plugins/arm/v7/opdefs/A88186_smmul.d16
-rw-r--r--plugins/arm/v7/opdefs/A88305_vcvt.d32
-rw-r--r--plugins/arm/v7/opdefs/A88306_vcvt.d597
-rw-r--r--plugins/arm/v7/opdefs/A88309_vcvt.d129
-rw-r--r--plugins/arm/v7/opdefs/A88310_vcvt.d129
-rw-r--r--plugins/arm/v7/opdefs/A88311_vcvt.d221
-rw-r--r--plugins/arm/v7/opdefs/A88312_vdiv.d10
-rw-r--r--plugins/arm/v7/opdefs/A88314_vdup.d26
-rw-r--r--plugins/arm/v7/opdefs/A88315_veor.d10
-rw-r--r--plugins/arm/v7/opdefs/A88316_vext.d137
-rw-r--r--plugins/arm/v7/opdefs/A88317_vfm.d34
-rw-r--r--plugins/arm/v7/opdefs/A88318_vfnm.d18
-rw-r--r--plugins/arm/v7/opdefs/A88319_vh.d98
-rw-r--r--plugins/arm/v7/opdefs/A88334_vmax.d98
-rw-r--r--plugins/arm/v7/opdefs/A88335_vmax.d18
-rw-r--r--plugins/arm/v7/opdefs/A88336_vmla.d1209
-rw-r--r--plugins/arm/v7/opdefs/A88337_vmla.d34
-rw-r--r--plugins/arm/v7/opdefs/A88343_vmov.d129
-rw-r--r--plugins/arm/v7/opdefs/A88344_vmov.d137
-rw-r--r--plugins/arm/v7/opdefs/A88345_vmov.d10
-rw-r--r--plugins/arm/v7/opdefs/A88346_vmovl.d26
-rw-r--r--plugins/arm/v7/opdefs/A88347_vmovn.d14
-rw-r--r--plugins/arm/v7/opdefs/A88348_vmrs.d75
-rw-r--r--plugins/arm/v7/opdefs/A88349_vmsr.d75
-rw-r--r--plugins/arm/v7/opdefs/A88350_vmul.d1065
-rw-r--r--plugins/arm/v7/opdefs/A88351_vmul.d18
-rw-r--r--plugins/arm/v7/opdefs/A88353_vmvn.d1277
-rw-r--r--plugins/arm/v7/opdefs/A88354_vmvn.d6
-rw-r--r--plugins/arm/v7/opdefs/A88355_vneg.d26
-rw-r--r--plugins/arm/v7/opdefs/A88356_vnm.d26
-rw-r--r--plugins/arm/v7/opdefs/A88358_vorn.d10
-rw-r--r--plugins/arm/v7/opdefs/A88359_vorr.d114
-rw-r--r--plugins/arm/v7/opdefs/A88360_vorr.d10
-rw-r--r--plugins/arm/v7/opdefs/A88361_vpadal.d50
-rw-r--r--plugins/arm/v7/opdefs/A88362_vpadd.d14
-rw-r--r--plugins/arm/v7/opdefs/A88363_vpadd.d6
-rw-r--r--plugins/arm/v7/opdefs/A88364_vpaddl.d50
-rw-r--r--plugins/arm/v7/opdefs/A88365_vpmax.d50
-rw-r--r--plugins/arm/v7/opdefs/A88366_vpmax.d10
-rw-r--r--plugins/arm/v7/opdefs/A88369_vqabs.d26
-rw-r--r--plugins/arm/v7/opdefs/A88370_vqadd.d813
-rw-r--r--plugins/arm/v7/opdefs/A88374_vqmov.d441
-rw-r--r--plugins/arm/v7/opdefs/A88375_vqneg.d26
-rw-r--r--plugins/arm/v7/opdefs/A88377_vqrshl.d66
-rw-r--r--plugins/arm/v7/opdefs/A88379_vqshl.d66
-rw-r--r--plugins/arm/v7/opdefs/A88382_vqsub.d66
-rw-r--r--plugins/arm/v7/opdefs/A88383_vraddhn.d14
-rw-r--r--plugins/arm/v7/opdefs/A88384_vrecpe.d18
-rw-r--r--plugins/arm/v7/opdefs/A88385_vrecps.d10
-rw-r--r--plugins/arm/v7/opdefs/A88386_vrev.d74
-rw-r--r--plugins/arm/v7/opdefs/A88387_vrhadd.d50
-rw-r--r--plugins/arm/v7/opdefs/A88388_vrshl.d66
-rw-r--r--plugins/arm/v7/opdefs/A88391_vrsqrte.d18
-rw-r--r--plugins/arm/v7/opdefs/A88392_vrsqrts.d10
-rw-r--r--plugins/arm/v7/opdefs/A88394_vrsubhn.d14
-rw-r--r--plugins/arm/v7/opdefs/A88396_vshl.d66
-rw-r--r--plugins/arm/v7/opdefs/A88401_vsqrt.d10
-rw-r--r--plugins/arm/v7/opdefs/A88413_vstr.d125
-rw-r--r--plugins/arm/v7/opdefs/A88414_vsub.d18
-rw-r--r--plugins/arm/v7/opdefs/A88415_vsub.d18
-rw-r--r--plugins/arm/v7/opdefs/A88416_vsubhn.d14
-rw-r--r--plugins/arm/v7/opdefs/A88417_vsub.d50
-rw-r--r--plugins/arm/v7/opdefs/A88418_vswp.d10
-rw-r--r--plugins/arm/v7/opdefs/A88420_vtrn.d26
-rw-r--r--plugins/arm/v7/opdefs/A88421_vtst.d26
-rw-r--r--plugins/arm/v7/opdefs/A88422_vuzp.d26
-rw-r--r--plugins/arm/v7/opdefs/A88423_vzip.d26
-rw-r--r--plugins/arm/v7/opdefs/A88424_wfe.d8
-rw-r--r--plugins/arm/v7/opdefs/A88425_wfi.d8
-rw-r--r--plugins/arm/v7/opdefs/A88426_yield.d8
-rw-r--r--plugins/arm/v7/opdefs/A931_enterx.d6
-rw-r--r--plugins/arm/v7/opdefs/B9310_msr.d6
-rw-r--r--plugins/arm/v7/opdefs/B9311_msr.d4
-rw-r--r--plugins/arm/v7/opdefs/B9312_msr.d6
-rw-r--r--plugins/arm/v7/opdefs/B9313_rfe.d14
-rw-r--r--plugins/arm/v7/opdefs/B9314_smc.d6
-rw-r--r--plugins/arm/v7/opdefs/B9315_srs.d6
-rw-r--r--plugins/arm/v7/opdefs/B9316_srs.d10
-rw-r--r--plugins/arm/v7/opdefs/B9317_stm.d10
-rw-r--r--plugins/arm/v7/opdefs/B9319_subs.d4
-rw-r--r--plugins/arm/v7/opdefs/B931_cps.d12
-rw-r--r--plugins/arm/v7/opdefs/B9320_subs.d6
-rw-r--r--plugins/arm/v7/opdefs/B9321_vmrs.d6
-rw-r--r--plugins/arm/v7/opdefs/B9322_vmsr.d6
-rw-r--r--plugins/arm/v7/opdefs/B932_cps.d8
-rw-r--r--plugins/arm/v7/opdefs/B933_eret.d6
-rw-r--r--plugins/arm/v7/opdefs/B934_hvc.d6
-rw-r--r--plugins/arm/v7/opdefs/B935_ldm.d10
-rw-r--r--plugins/arm/v7/opdefs/B936_ldm.d10
-rw-r--r--plugins/arm/v7/opdefs/B938_mrs.d6
-rw-r--r--plugins/arm/v7/opdefs/B939_mrs.d6
-rw-r--r--plugins/arm/v7/opdefs/Makefile.am15
98 files changed, 7556 insertions, 983 deletions
diff --git a/plugins/arm/v7/helpers.h b/plugins/arm/v7/helpers.h
index 5d4db94..bf4bc5a 100644
--- a/plugins/arm/v7/helpers.h
+++ b/plugins/arm/v7/helpers.h
@@ -43,6 +43,7 @@
#include "registers/coproc.h"
#include "registers/simd.h"
#include "registers/special.h"
+#include "../register.h"
@@ -286,6 +287,15 @@
})
+#define Multiplication(factor, val) \
+ ({ \
+ GArchOperand *__result; \
+ uint32_t __computed; \
+ __computed = factor * val; \
+ __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __computed); \
+ __result; \
+ })
+
#define NextRegister(idx) \
({ \
GArchOperand *__result; \
@@ -299,11 +309,13 @@
})
-#define QuadWordVector(idx) \
+#define NexSingleWordVector(prev) \
({ \
GArchOperand *__result; \
+ uint8_t __idx; \
GArchRegister *__reg; \
- __reg = g_armv7_simd_register_new(SRM_QUAD_WORD, idx); \
+ __idx = g_arm_register_get_index(G_ARM_REGISTER(prev)); \
+ __reg = g_armv7_simd_register_new(SRM_SINGLE_WORD, __idx + 1); \
if (__reg == NULL) \
__result = NULL; \
else \
@@ -312,31 +324,11 @@
})
-#define SignExtend(val, size, top) \
- ({ \
- GArchOperand *__result; \
- MemoryDataSize __mds; \
- uint ## size ## _t __val; \
- __mds = MDS_ ## size ## _BITS_SIGNED; \
- __val = armv7_sign_extend(val, top, size); \
- __result = g_imm_operand_new_from_value(__mds, __val); \
- __result; \
- })
-
-
-#define SingleRegList(t) \
- ({ \
- GArchOperand *__result; \
- __result = g_armv7_reglist_operand_new(1 << t); \
- __result; \
- })
-
-
-#define SingleWordVector(idx) \
+#define QuadWordVector(idx) \
({ \
GArchOperand *__result; \
GArchRegister *__reg; \
- __reg = g_armv7_simd_register_new(SRM_SINGLE_WORD, idx); \
+ __reg = g_armv7_simd_register_new(SRM_QUAD_WORD, idx); \
if (__reg == NULL) \
__result = NULL; \
else \
@@ -422,11 +414,44 @@
})
-#define SpecRegAPSR() \
+#define SignExtend(val, size, top) \
+ ({ \
+ GArchOperand *__result; \
+ MemoryDataSize __mds; \
+ uint ## size ## _t __val; \
+ __mds = MDS_ ## size ## _BITS_SIGNED; \
+ __val = armv7_sign_extend(val, top, size); \
+ __result = g_imm_operand_new_from_value(__mds, __val); \
+ __result; \
+ })
+
+
+#define SingleRegList(t) \
+ ({ \
+ GArchOperand *__result; \
+ __result = g_armv7_reglist_operand_new(1 << t); \
+ __result; \
+ })
+
+
+#define SingleWordVector(idx) \
+ ({ \
+ GArchOperand *__result; \
+ GArchRegister *__reg; \
+ __reg = g_armv7_simd_register_new(SRM_SINGLE_WORD, idx); \
+ if (__reg == NULL) \
+ __result = NULL; \
+ else \
+ __result = g_armv7_register_operand_new(G_ARMV7_REGISTER(__reg)); \
+ __result; \
+ })
+
+
+#define SpecReg(target) \
({ \
GArchOperand *__result; \
GArchRegister *__reg; \
- __reg = g_armv7_special_register_new(SRT_APSR); \
+ __reg = g_armv7_special_register_new(target); \
if (__reg == NULL) \
__result = NULL; \
else \
diff --git a/plugins/arm/v7/opcodes/opcodes_tmp_arm.h b/plugins/arm/v7/opcodes/opcodes_tmp_arm.h
index 48a0c1a..238b87a 100644
--- a/plugins/arm/v7/opcodes/opcodes_tmp_arm.h
+++ b/plugins/arm/v7/opcodes/opcodes_tmp_arm.h
@@ -1,12 +1,8 @@
#ifndef arm_def_tmp_h
#define arm_def_tmp_h
-#define armv7_read_arm_instr_a8_vcvt_between_double_precision_and_single_precision(r) NULL
#define armv7_read_arm_instr_a8_vcvt_between_floating_point_and_fixed_point_advanced_simd(r) NULL
#define armv7_read_arm_instr_a8_vcvt_between_floating_point_and_fixed_point_floating_point(r) NULL
-#define armv7_read_arm_instr_a8_vcvtb_vcvtt(r) NULL
-#define armv7_read_arm_instr_a8_vcvt_vcvtr_between_floating_point_and_integer_floating_point(r) NULL
#define armv7_read_arm_instr_a8_vdup_scalar(r) NULL
-#define armv7_read_arm_instr_a8_vext(r) NULL
#define armv7_read_arm_instr_a8_vld1_multiple_single_elements(r) NULL
#define armv7_read_arm_instr_a8_vld1_single_element_to_all_lanes(r) NULL
#define armv7_read_arm_instr_a8_vld1_single_element_to_one_lane(r) NULL
@@ -22,21 +18,13 @@
#define armv7_read_arm_instr_a8_vldm(r) NULL
#define armv7_read_arm_instr_a8_vldr(r) NULL
#define armv7_read_arm_instr_a8_vmla_vmlal_vmls_vmlsl_by_scalar(r) NULL
-#define armv7_read_arm_instr_a8_vmla_vmlal_vmls_vmlsl_integer(r) NULL
#define armv7_read_arm_instr_a8_vmov_arm_core_register_to_scalar(r) NULL
-#define armv7_read_arm_instr_a8_vmov_between_arm_core_register_and_single_precision_register(r) NULL
-#define armv7_read_arm_instr_a8_vmov_between_two_arm_core_registers_and_two_single_precision_registers(r) NULL
#define armv7_read_arm_instr_a8_vmov_immediate(r) NULL
#define armv7_read_arm_instr_a8_vmov_register(r) NULL
#define armv7_read_arm_instr_a8_vmov_scalar_to_arm_core_register(r) NULL
-#define armv7_read_arm_instr_a8_vmrs(r) NULL
-#define armv7_read_arm_instr_a8_vmsr(r) NULL
#define armv7_read_arm_instr_a8_vmul_vmull_by_scalar(r) NULL
-#define armv7_read_arm_instr_a8_vmul_vmull_integer_and_polynomial(r) NULL
-#define armv7_read_arm_instr_a8_vmvn_immediate(r) NULL
#define armv7_read_arm_instr_a8_vpop(r) NULL
#define armv7_read_arm_instr_a8_vpush(r) NULL
-#define armv7_read_arm_instr_a8_vqadd(r) NULL
#define armv7_read_arm_instr_a8_vqdmlal_vqdmlsl(r) NULL
#define armv7_read_arm_instr_a8_vqdmulh(r) NULL
#define armv7_read_arm_instr_a8_vqdmull(r) NULL
@@ -63,6 +51,5 @@
#define armv7_read_arm_instr_a8_vst4_multiple_4_element_structures(r) NULL
#define armv7_read_arm_instr_a8_vst4_single_4_element_structure_from_one_lane(r) NULL
#define armv7_read_arm_instr_a8_vstm(r) NULL
-#define armv7_read_arm_instr_a8_vstr(r) NULL
#define armv7_read_arm_instr_a8_vtbl_vtbx(r) NULL
#endif
diff --git a/plugins/arm/v7/opcodes/opcodes_tmp_thumb_32.h b/plugins/arm/v7/opcodes/opcodes_tmp_thumb_32.h
index 1605942..c0ec1f8 100644
--- a/plugins/arm/v7/opcodes/opcodes_tmp_thumb_32.h
+++ b/plugins/arm/v7/opcodes/opcodes_tmp_thumb_32.h
@@ -1,12 +1,8 @@
#ifndef thumb_32_def_tmp_h
#define thumb_32_def_tmp_h
-#define armv7_read_thumb_32_instr_a8_vcvt_between_double_precision_and_single_precision(r) NULL
#define armv7_read_thumb_32_instr_a8_vcvt_between_floating_point_and_fixed_point_advanced_simd(r) NULL
#define armv7_read_thumb_32_instr_a8_vcvt_between_floating_point_and_fixed_point_floating_point(r) NULL
-#define armv7_read_thumb_32_instr_a8_vcvtb_vcvtt(r) NULL
-#define armv7_read_thumb_32_instr_a8_vcvt_vcvtr_between_floating_point_and_integer_floating_point(r) NULL
#define armv7_read_thumb_32_instr_a8_vdup_scalar(r) NULL
-#define armv7_read_thumb_32_instr_a8_vext(r) NULL
#define armv7_read_thumb_32_instr_a8_vld1_multiple_single_elements(r) NULL
#define armv7_read_thumb_32_instr_a8_vld1_single_element_to_all_lanes(r) NULL
#define armv7_read_thumb_32_instr_a8_vld1_single_element_to_one_lane(r) NULL
@@ -22,21 +18,13 @@
#define armv7_read_thumb_32_instr_a8_vldm(r) NULL
#define armv7_read_thumb_32_instr_a8_vldr(r) NULL
#define armv7_read_thumb_32_instr_a8_vmla_vmlal_vmls_vmlsl_by_scalar(r) NULL
-#define armv7_read_thumb_32_instr_a8_vmla_vmlal_vmls_vmlsl_integer(r) NULL
#define armv7_read_thumb_32_instr_a8_vmov_arm_core_register_to_scalar(r) NULL
-#define armv7_read_thumb_32_instr_a8_vmov_between_arm_core_register_and_single_precision_register(r) NULL
-#define armv7_read_thumb_32_instr_a8_vmov_between_two_arm_core_registers_and_two_single_precision_registers(r) NULL
#define armv7_read_thumb_32_instr_a8_vmov_immediate(r) NULL
#define armv7_read_thumb_32_instr_a8_vmov_register(r) NULL
#define armv7_read_thumb_32_instr_a8_vmov_scalar_to_arm_core_register(r) NULL
-#define armv7_read_thumb_32_instr_a8_vmrs(r) NULL
-#define armv7_read_thumb_32_instr_a8_vmsr(r) NULL
#define armv7_read_thumb_32_instr_a8_vmul_vmull_by_scalar(r) NULL
-#define armv7_read_thumb_32_instr_a8_vmul_vmull_integer_and_polynomial(r) NULL
-#define armv7_read_thumb_32_instr_a8_vmvn_immediate(r) NULL
#define armv7_read_thumb_32_instr_a8_vpop(r) NULL
#define armv7_read_thumb_32_instr_a8_vpush(r) NULL
-#define armv7_read_thumb_32_instr_a8_vqadd(r) NULL
#define armv7_read_thumb_32_instr_a8_vqdmlal_vqdmlsl(r) NULL
#define armv7_read_thumb_32_instr_a8_vqdmulh(r) NULL
#define armv7_read_thumb_32_instr_a8_vqdmull(r) NULL
@@ -63,6 +51,5 @@
#define armv7_read_thumb_32_instr_a8_vst4_multiple_4_element_structures(r) NULL
#define armv7_read_thumb_32_instr_a8_vst4_single_4_element_structure_from_one_lane(r) NULL
#define armv7_read_thumb_32_instr_a8_vstm(r) NULL
-#define armv7_read_thumb_32_instr_a8_vstr(r) NULL
#define armv7_read_thumb_32_instr_a8_vtbl_vtbx(r) NULL
#endif
diff --git a/plugins/arm/v7/opdefs/A88109_mrs.d b/plugins/arm/v7/opdefs/A88109_mrs.d
index 664a8be..bf52adc 100644
--- a/plugins/arm/v7/opdefs/A88109_mrs.d
+++ b/plugins/arm/v7/opdefs/A88109_mrs.d
@@ -42,7 +42,7 @@
@conv {
reg_D = Register(Rd)
- spec_reg = SpecRegAPSR()
+ spec_reg = SpecReg(SRT_APSR)
}
@@ -63,7 +63,7 @@
@conv {
reg_D = Register(Rd)
- spec_reg = SpecRegAPSR()
+ spec_reg = SpecReg(SRT_APSR)
}
diff --git a/plugins/arm/v7/opdefs/A88184_smmla.d b/plugins/arm/v7/opdefs/A88184_smmla.d
index a3131ce..28293be 100644
--- a/plugins/arm/v7/opdefs/A88184_smmla.d
+++ b/plugins/arm/v7/opdefs/A88184_smmla.d
@@ -41,7 +41,7 @@
@assert {
- R == 0
+ R == 1
}
@@ -54,7 +54,7 @@
}
- @asm smmla reg_D reg_N reg_M reg_A
+ @asm smmlar reg_D reg_N reg_M reg_A
}
@@ -64,7 +64,7 @@
@assert {
- R == 1
+ R == 0
}
@@ -77,7 +77,7 @@
}
- @asm smmlar reg_D reg_N reg_M reg_A
+ @asm smmla reg_D reg_N reg_M reg_A
}
@@ -93,7 +93,7 @@
@assert {
- R == 0
+ R == 1
}
@@ -106,7 +106,7 @@
}
- @asm smmla reg_D reg_N reg_M reg_A
+ @asm smmlar reg_D reg_N reg_M reg_A
@rules {
@@ -122,7 +122,7 @@
@assert {
- R == 1
+ R == 0
}
@@ -135,7 +135,7 @@
}
- @asm smmlar reg_D reg_N reg_M reg_A
+ @asm smmla reg_D reg_N reg_M reg_A
@rules {
diff --git a/plugins/arm/v7/opdefs/A88185_smmls.d b/plugins/arm/v7/opdefs/A88185_smmls.d
index 2a7407a..02fd927 100644
--- a/plugins/arm/v7/opdefs/A88185_smmls.d
+++ b/plugins/arm/v7/opdefs/A88185_smmls.d
@@ -41,7 +41,7 @@
@assert {
- R == 0
+ R == 1
}
@@ -54,7 +54,7 @@
}
- @asm smmls reg_D reg_N reg_M reg_A
+ @asm smmlsr reg_D reg_N reg_M reg_A
}
@@ -64,7 +64,7 @@
@assert {
- R == 1
+ R == 0
}
@@ -77,7 +77,7 @@
}
- @asm smmlsr reg_D reg_N reg_M reg_A
+ @asm smmls reg_D reg_N reg_M reg_A
}
@@ -93,7 +93,7 @@
@assert {
- R == 0
+ R == 1
}
@@ -106,7 +106,7 @@
}
- @asm smmls reg_D reg_N reg_M reg_A
+ @asm smmlsr reg_D reg_N reg_M reg_A
@rules {
@@ -122,7 +122,7 @@
@assert {
- R == 1
+ R == 0
}
@@ -135,7 +135,7 @@
}
- @asm smmlsr reg_D reg_N reg_M reg_A
+ @asm smmls reg_D reg_N reg_M reg_A
@rules {
diff --git a/plugins/arm/v7/opdefs/A88186_smmul.d b/plugins/arm/v7/opdefs/A88186_smmul.d
index 8004547..8d0c2f4 100644
--- a/plugins/arm/v7/opdefs/A88186_smmul.d
+++ b/plugins/arm/v7/opdefs/A88186_smmul.d
@@ -41,7 +41,7 @@
@assert {
- R == 0
+ R == 1
}
@@ -53,7 +53,7 @@
}
- @asm smmul ?reg_D reg_N reg_M
+ @asm smmulr ?reg_D reg_N reg_M
}
@@ -63,7 +63,7 @@
@assert {
- R == 1
+ R == 0
}
@@ -75,7 +75,7 @@
}
- @asm smmulr ?reg_D reg_N reg_M
+ @asm smmul ?reg_D reg_N reg_M
}
@@ -91,7 +91,7 @@
@assert {
- R == 0
+ R == 1
}
@@ -103,7 +103,7 @@
}
- @asm smmul ?reg_D reg_N reg_M
+ @asm smmulr ?reg_D reg_N reg_M
@rules {
@@ -119,7 +119,7 @@
@assert {
- R == 1
+ R == 0
}
@@ -131,7 +131,7 @@
}
- @asm smmulr ?reg_D reg_N reg_M
+ @asm smmul ?reg_D reg_N reg_M
@rules {
diff --git a/plugins/arm/v7/opdefs/A88305_vcvt.d b/plugins/arm/v7/opdefs/A88305_vcvt.d
index 554722f..02fe652 100644
--- a/plugins/arm/v7/opdefs/A88305_vcvt.d
+++ b/plugins/arm/v7/opdefs/A88305_vcvt.d
@@ -54,7 +54,7 @@
}
- @asm vcvt.s32.f32. qwvec_D qwvec_M
+ @asm vcvt.s32.f32 qwvec_D qwvec_M
}
@@ -77,7 +77,7 @@
}
- @asm vcvt.u32.f32. qwvec_D qwvec_M
+ @asm vcvt.u32.f32 qwvec_D qwvec_M
}
@@ -100,7 +100,7 @@
}
- @asm vcvt.f32.s32. qwvec_D qwvec_M
+ @asm vcvt.f32.s32 qwvec_D qwvec_M
}
@@ -123,7 +123,7 @@
}
- @asm vcvt.f32.u32. qwvec_D qwvec_M
+ @asm vcvt.f32.u32 qwvec_D qwvec_M
}
@@ -146,7 +146,7 @@
}
- @asm vcvt.s32.f32. dwvec_D dwvec_M
+ @asm vcvt.s32.f32 dwvec_D dwvec_M
}
@@ -169,7 +169,7 @@
}
- @asm vcvt.u32.f32. dwvec_D dwvec_M
+ @asm vcvt.u32.f32 dwvec_D dwvec_M
}
@@ -192,7 +192,7 @@
}
- @asm vcvt.f32.s32. dwvec_D dwvec_M
+ @asm vcvt.f32.s32 dwvec_D dwvec_M
}
@@ -215,7 +215,7 @@
}
- @asm vcvt.f32.u32. dwvec_D dwvec_M
+ @asm vcvt.f32.u32 dwvec_D dwvec_M
}
@@ -244,7 +244,7 @@
}
- @asm vcvt.s32.f32. qwvec_D qwvec_M
+ @asm vcvt.s32.f32 qwvec_D qwvec_M
}
@@ -267,7 +267,7 @@
}
- @asm vcvt.u32.f32. qwvec_D qwvec_M
+ @asm vcvt.u32.f32 qwvec_D qwvec_M
}
@@ -290,7 +290,7 @@
}
- @asm vcvt.f32.s32. qwvec_D qwvec_M
+ @asm vcvt.f32.s32 qwvec_D qwvec_M
}
@@ -313,7 +313,7 @@
}
- @asm vcvt.f32.u32. qwvec_D qwvec_M
+ @asm vcvt.f32.u32 qwvec_D qwvec_M
}
@@ -336,7 +336,7 @@
}
- @asm vcvt.s32.f32. dwvec_D dwvec_M
+ @asm vcvt.s32.f32 dwvec_D dwvec_M
}
@@ -359,7 +359,7 @@
}
- @asm vcvt.u32.f32. dwvec_D dwvec_M
+ @asm vcvt.u32.f32 dwvec_D dwvec_M
}
@@ -382,7 +382,7 @@
}
- @asm vcvt.f32.s32. dwvec_D dwvec_M
+ @asm vcvt.f32.s32 dwvec_D dwvec_M
}
@@ -405,7 +405,7 @@
}
- @asm vcvt.f32.u32. dwvec_D dwvec_M
+ @asm vcvt.f32.u32 dwvec_D dwvec_M
}
diff --git a/plugins/arm/v7/opdefs/A88306_vcvt.d b/plugins/arm/v7/opdefs/A88306_vcvt.d
new file mode 100644
index 0000000..173232b
--- /dev/null
+++ b/plugins/arm/v7/opdefs/A88306_vcvt.d
@@ -0,0 +1,597 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2017 Cyrille Bagard
+ *
+ * This file is part of Chrysalide.
+ *
+ * Chrysalide is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * Chrysalide is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title VCVT, VCVTR (between floating-point and integer, Floating-point)
+
+@id 301
+
+@desc {
+
+ These instructions convert a value in a register from floating-point to a 32-bit integer, or from a 32-bit integer to floating-point, and place the result in a second register. The floating-point to integer operation normally uses the Round towards Zero rounding mode, but can optionally use the rounding mode specified by the FPSCR. The integer to floating-point operation uses the rounding mode specified by the FPSCR. VCVT (between floating-point and fixed-point, Floating-point) on page A8-874 describes conversions between floating-point and 16-bit integers. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of general controls of CP10 and CP11 functionality on page B1-1230 summarizes these controls.
+
+}
+
+@encoding (T1) {
+
+ @word 1 1 1 0 1 1 1 0 1 D(1) 1 1 1 opc2(3) Vd(4) 1 0 1 sz(1) op(1) 1 M(1) 0 Vm(4)
+
+ @syntax {
+
+ @subid 1237
+
+ @assert {
+
+ opc2 == 0
+ sz == 1
+ op == 0
+
+ }
+
+ @conv {
+
+ swvec_D = SingleWordVector(Vd:D)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vcvtr.s32.f64 swvec_D dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1238
+
+ @assert {
+
+ opc2 == 0
+ sz == 1
+ op == 1
+
+ }
+
+ @conv {
+
+ swvec_D = SingleWordVector(Vd:D)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vcvt.s32.f64 swvec_D dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1239
+
+ @assert {
+
+ opc2 == 0
+ sz == 0
+ op == 0
+
+ }
+
+ @conv {
+
+ swvec_D = SingleWordVector(Vd:D)
+ swvec_M = SingleWordVector(Vm:M)
+
+ }
+
+ @asm vcvtr.s32.f32 swvec_D swvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1240
+
+ @assert {
+
+ opc2 == 0
+ sz == 0
+ op == 1
+
+ }
+
+ @conv {
+
+ swvec_D = SingleWordVector(Vd:D)
+ swvec_M = SingleWordVector(Vm:M)
+
+ }
+
+ @asm vcvt.s32.f32 swvec_D swvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1241
+
+ @assert {
+
+ opc2 == 0
+ sz == 1
+ op == 0
+
+ }
+
+ @conv {
+
+ swvec_D = SingleWordVector(Vd:D)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vcvtr.u32.f64 swvec_D dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1242
+
+ @assert {
+
+ opc2 == 0
+ sz == 1
+ op == 1
+
+ }
+
+ @conv {
+
+ swvec_D = SingleWordVector(Vd:D)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vcvt.u32.f64 swvec_D dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1243
+
+ @assert {
+
+ opc2 == 0
+ sz == 0
+ op == 0
+
+ }
+
+ @conv {
+
+ swvec_D = SingleWordVector(Vd:D)
+ swvec_M = SingleWordVector(Vm:M)
+
+ }
+
+ @asm vcvtr.u32.f32 swvec_D swvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1244
+
+ @assert {
+
+ opc2 == 0
+ sz == 0
+ op == 1
+
+ }
+
+ @conv {
+
+ swvec_D = SingleWordVector(Vd:D)
+ swvec_M = SingleWordVector(Vm:M)
+
+ }
+
+ @asm vcvt.u32.f32 swvec_D swvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1245
+
+ @assert {
+
+ opc2 == 0
+ sz == 1
+ op == 1
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(Vd:D)
+ swvec_M = SingleWordVector(M:Vm)
+
+ }
+
+ @asm vcvt.f64.s32 dwvec_D swvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1246
+
+ @assert {
+
+ opc2 == 0
+ sz == 1
+ op == 0
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(Vd:D)
+ swvec_M = SingleWordVector(M:Vm)
+
+ }
+
+ @asm vcvt.f64.u32 dwvec_D swvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1247
+
+ @assert {
+
+ opc2 == 0
+ sz == 0
+ op == 1
+
+ }
+
+ @conv {
+
+ swvec_D = SingleWordVector(Vd:D)
+ swvec_M = SingleWordVector(Vm:M)
+
+ }
+
+ @asm vcvt.f32.s32 swvec_D swvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1248
+
+ @assert {
+
+ opc2 == 0
+ sz == 0
+ op == 0
+
+ }
+
+ @conv {
+
+ swvec_D = SingleWordVector(Vd:D)
+ swvec_M = SingleWordVector(Vm:M)
+
+ }
+
+ @asm vcvt.f32.u32 swvec_D swvec_M
+
+ }
+
+}
+
+@encoding (A1) {
+
+ @word 1 1 1 0 1 1 1 0 1 D(1) 1 1 1 opc2(3) Vd(4) 1 0 1 sz(1) op(1) 1 M(1) 0 Vm(4)
+
+ @syntax {
+
+ @subid 1249
+
+ @assert {
+
+ opc2 == 0
+ sz == 1
+ op == 0
+
+ }
+
+ @conv {
+
+ swvec_D = SingleWordVector(Vd:D)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vcvtr.s32.f64 swvec_D dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1250
+
+ @assert {
+
+ opc2 == 0
+ sz == 1
+ op == 1
+
+ }
+
+ @conv {
+
+ swvec_D = SingleWordVector(Vd:D)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vcvt.s32.f64 swvec_D dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1251
+
+ @assert {
+
+ opc2 == 0
+ sz == 0
+ op == 0
+
+ }
+
+ @conv {
+
+ swvec_D = SingleWordVector(Vd:D)
+ swvec_M = SingleWordVector(Vm:M)
+
+ }
+
+ @asm vcvtr.s32.f32 swvec_D swvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1252
+
+ @assert {
+
+ opc2 == 0
+ sz == 0
+ op == 1
+
+ }
+
+ @conv {
+
+ swvec_D = SingleWordVector(Vd:D)
+ swvec_M = SingleWordVector(Vm:M)
+
+ }
+
+ @asm vcvt.s32.f32 swvec_D swvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1253
+
+ @assert {
+
+ opc2 == 0
+ sz == 1
+ op == 0
+
+ }
+
+ @conv {
+
+ swvec_D = SingleWordVector(Vd:D)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vcvtr.u32.f64 swvec_D dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1254
+
+ @assert {
+
+ opc2 == 0
+ sz == 1
+ op == 1
+
+ }
+
+ @conv {
+
+ swvec_D = SingleWordVector(Vd:D)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vcvt.u32.f64 swvec_D dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1255
+
+ @assert {
+
+ opc2 == 0
+ sz == 0
+ op == 0
+
+ }
+
+ @conv {
+
+ swvec_D = SingleWordVector(Vd:D)
+ swvec_M = SingleWordVector(Vm:M)
+
+ }
+
+ @asm vcvtr.u32.f32 swvec_D swvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1256
+
+ @assert {
+
+ opc2 == 0
+ sz == 0
+ op == 1
+
+ }
+
+ @conv {
+
+ swvec_D = SingleWordVector(Vd:D)
+ swvec_M = SingleWordVector(Vm:M)
+
+ }
+
+ @asm vcvt.u32.f32 swvec_D swvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1257
+
+ @assert {
+
+ opc2 == 0
+ sz == 1
+ op == 1
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(Vd:D)
+ swvec_M = SingleWordVector(M:Vm)
+
+ }
+
+ @asm vcvt.f64.s32 dwvec_D swvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1258
+
+ @assert {
+
+ opc2 == 0
+ sz == 1
+ op == 0
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(Vd:D)
+ swvec_M = SingleWordVector(M:Vm)
+
+ }
+
+ @asm vcvt.f64.u32 dwvec_D swvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1259
+
+ @assert {
+
+ opc2 == 0
+ sz == 0
+ op == 1
+
+ }
+
+ @conv {
+
+ swvec_D = SingleWordVector(Vd:D)
+ swvec_M = SingleWordVector(Vm:M)
+
+ }
+
+ @asm vcvt.f32.s32 swvec_D swvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1260
+
+ @assert {
+
+ opc2 == 0
+ sz == 0
+ op == 0
+
+ }
+
+ @conv {
+
+ swvec_D = SingleWordVector(Vd:D)
+ swvec_M = SingleWordVector(Vm:M)
+
+ }
+
+ @asm vcvt.f32.u32 swvec_D swvec_M
+
+ }
+
+}
+
diff --git a/plugins/arm/v7/opdefs/A88309_vcvt.d b/plugins/arm/v7/opdefs/A88309_vcvt.d
new file mode 100644
index 0000000..2002aa0
--- /dev/null
+++ b/plugins/arm/v7/opdefs/A88309_vcvt.d
@@ -0,0 +1,129 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2017 Cyrille Bagard
+ *
+ * This file is part of Chrysalide.
+ *
+ * Chrysalide is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * Chrysalide is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title VCVT (between double-precision and single-precision)
+
+@id 302
+
+@desc {
+
+ This instruction does one of the following: • converts the value in a double-precision register to single-precision and writes the result to a single-precision register • converts the value in a single-precision register to double-precision and writes the result to a double-precision register. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of general controls of CP10 and CP11 functionality on page B1-1230 summarizes these controls.
+
+}
+
+@encoding (T1) {
+
+ @word 1 1 1 0 1 1 1 0 1 D(1) 1 1 0 1 1 1 Vd(4) 1 0 1 sz(1) 1 1 M(1) 0 Vm(4)
+
+ @syntax {
+
+ @subid 1261
+
+ @assert {
+
+ sz == 0
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ swvec_M = SingleWordVector(Vm:M)
+
+ }
+
+ @asm vcvt.f64.f32 dwvec_D swvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1262
+
+ @assert {
+
+ sz == 1
+
+ }
+
+ @conv {
+
+ swvec_D = SingleWordVector(Vd:D)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vcvt.f32.f64 swvec_D dwvec_M
+
+ }
+
+}
+
+@encoding (A1) {
+
+ @word 1 1 1 0 1 1 1 0 1 D(1) 1 1 0 1 1 1 Vd(4) 1 0 1 sz(1) 1 1 M(1) 0 Vm(4)
+
+ @syntax {
+
+ @subid 1263
+
+ @assert {
+
+ sz == 0
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ swvec_M = SingleWordVector(Vm:M)
+
+ }
+
+ @asm vcvt.f64.f32 dwvec_D swvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1264
+
+ @assert {
+
+ sz == 1
+
+ }
+
+ @conv {
+
+ swvec_D = SingleWordVector(Vd:D)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vcvt.f32.f64 swvec_D dwvec_M
+
+ }
+
+}
+
diff --git a/plugins/arm/v7/opdefs/A88310_vcvt.d b/plugins/arm/v7/opdefs/A88310_vcvt.d
new file mode 100644
index 0000000..6d5a176
--- /dev/null
+++ b/plugins/arm/v7/opdefs/A88310_vcvt.d
@@ -0,0 +1,129 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2017 Cyrille Bagard
+ *
+ * This file is part of Chrysalide.
+ *
+ * Chrysalide is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * Chrysalide is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title VCVT (between half-precision and single-precision, Advanced SIMD)
+
+@id 303
+
+@desc {
+
+ This instruction converts each element in a vector from single-precision to half-precision floating-point or from half-precision to single-precision, and places the results in a second vector. The vector elements must be 32-bit floating-point numbers, or 16-bit floating-point numbers. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of access controls for Advanced SIMD functionality on page B1-1232 summarizes these controls. ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available as a VFP instruction encoding, see Conditional execution on page A8-288.
+
+}
+
+@encoding (T1) {
+
+ @word 1 1 1 1 1 1 1 1 1 D(1) 1 1 size(2) 1 0 Vd(4) 0 1 1 op(1) 0 0 M(1) 0 Vm(4)
+
+ @syntax {
+
+ @subid 1265
+
+ @assert {
+
+ op == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vcvt.f32.f16 qwvec_D dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1266
+
+ @assert {
+
+ op == 0
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vcvt.f16.f32 dwvec_D qwvec_M
+
+ }
+
+}
+
+@encoding (A1) {
+
+ @word 1 1 1 1 1 1 1 1 1 D(1) 1 1 size(2) 1 0 Vd(4) 0 1 1 op(1) 0 0 M(1) 0 Vm(4)
+
+ @syntax {
+
+ @subid 1267
+
+ @assert {
+
+ op == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vcvt.f32.f16 qwvec_D dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1268
+
+ @assert {
+
+ op == 0
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vcvt.f16.f32 dwvec_D qwvec_M
+
+ }
+
+}
+
diff --git a/plugins/arm/v7/opdefs/A88311_vcvt.d b/plugins/arm/v7/opdefs/A88311_vcvt.d
new file mode 100644
index 0000000..8b6e279
--- /dev/null
+++ b/plugins/arm/v7/opdefs/A88311_vcvt.d
@@ -0,0 +1,221 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2017 Cyrille Bagard
+ *
+ * This file is part of Chrysalide.
+ *
+ * Chrysalide is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * Chrysalide is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title VCVTB, VCVTT
+
+@id 304
+
+@desc {
+
+ Vector Convert Bottom and Vector Convert Top do one of the following: • convert the half-precision value in the top or bottom half of a single-precision register to single-precision and write the result to a single-precision register • convert the value in a single-precision register to half-precision and write the result into the top or bottom half of a single-precision register, preserving the other half of the target register. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of general controls of CP10 and CP11 functionality on page B1-1230 summarizes these controls.
+
+}
+
+@encoding (T1) {
+
+ @word 1 1 1 0 1 1 1 0 1 D(1) 1 1 0 0 1 op(1) Vd(4) 1 0 1 0 T(1) 1 M(1) 0 Vm(4)
+
+ @syntax {
+
+ @subid 1269
+
+ @assert {
+
+ op == 0
+ T == 0
+
+ }
+
+ @conv {
+
+ swvec_D = SingleWordVector(Vd:D)
+ swvec_M = SingleWordVector(Vm:M)
+
+ }
+
+ @asm vcvtb.f32.f16 swvec_D swvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1270
+
+ @assert {
+
+ op == 0
+ T == 1
+
+ }
+
+ @conv {
+
+ swvec_D = SingleWordVector(Vd:D)
+ swvec_M = SingleWordVector(Vm:M)
+
+ }
+
+ @asm vcvtt.f32.f16 swvec_D swvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1271
+
+ @assert {
+
+ op == 1
+ T == 0
+
+ }
+
+ @conv {
+
+ swvec_D = SingleWordVector(Vd:D)
+ swvec_M = SingleWordVector(Vm:M)
+
+ }
+
+ @asm vcvtb.f16.f32 swvec_D swvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1272
+
+ @assert {
+
+ op == 1
+ T == 1
+
+ }
+
+ @conv {
+
+ swvec_D = SingleWordVector(Vd:D)
+ swvec_M = SingleWordVector(Vm:M)
+
+ }
+
+ @asm vcvtt.f16.f32 swvec_D swvec_M
+
+ }
+
+}
+
+@encoding (A1) {
+
+ @word 1 1 1 0 1 1 1 0 1 D(1) 1 1 0 0 1 op(1) Vd(4) 1 0 1 0 T(1) 1 M(1) 0 Vm(4)
+
+ @syntax {
+
+ @subid 1273
+
+ @assert {
+
+ op == 0
+ T == 0
+
+ }
+
+ @conv {
+
+ swvec_D = SingleWordVector(Vd:D)
+ swvec_M = SingleWordVector(Vm:M)
+
+ }
+
+ @asm vcvtb.f32.f16 swvec_D swvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1274
+
+ @assert {
+
+ op == 0
+ T == 1
+
+ }
+
+ @conv {
+
+ swvec_D = SingleWordVector(Vd:D)
+ swvec_M = SingleWordVector(Vm:M)
+
+ }
+
+ @asm vcvtt.f32.f16 swvec_D swvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1275
+
+ @assert {
+
+ op == 1
+ T == 0
+
+ }
+
+ @conv {
+
+ swvec_D = SingleWordVector(Vd:D)
+ swvec_M = SingleWordVector(Vm:M)
+
+ }
+
+ @asm vcvtb.f16.f32 swvec_D swvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1276
+
+ @assert {
+
+ op == 1
+ T == 1
+
+ }
+
+ @conv {
+
+ swvec_D = SingleWordVector(Vd:D)
+ swvec_M = SingleWordVector(Vm:M)
+
+ }
+
+ @asm vcvtt.f16.f32 swvec_D swvec_M
+
+ }
+
+}
+
diff --git a/plugins/arm/v7/opdefs/A88312_vdiv.d b/plugins/arm/v7/opdefs/A88312_vdiv.d
index a7e6a24..6500a3c 100644
--- a/plugins/arm/v7/opdefs/A88312_vdiv.d
+++ b/plugins/arm/v7/opdefs/A88312_vdiv.d
@@ -23,7 +23,7 @@
@title VDIV
-@id 301
+@id 305
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1237
+ @subid 1277
@assert {
@@ -59,7 +59,7 @@
@syntax {
- @subid 1238
+ @subid 1278
@assert {
@@ -87,7 +87,7 @@
@syntax {
- @subid 1239
+ @subid 1279
@assert {
@@ -109,7 +109,7 @@
@syntax {
- @subid 1240
+ @subid 1280
@assert {
diff --git a/plugins/arm/v7/opdefs/A88314_vdup.d b/plugins/arm/v7/opdefs/A88314_vdup.d
index a9f59ad..edba821 100644
--- a/plugins/arm/v7/opdefs/A88314_vdup.d
+++ b/plugins/arm/v7/opdefs/A88314_vdup.d
@@ -23,7 +23,7 @@
@title VDUP (ARM core register)
-@id 302
+@id 306
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1241
+ @subid 1281
@assert {
@@ -60,7 +60,7 @@
@syntax {
- @subid 1242
+ @subid 1282
@assert {
@@ -83,7 +83,7 @@
@syntax {
- @subid 1243
+ @subid 1283
@assert {
@@ -106,7 +106,7 @@
@syntax {
- @subid 1244
+ @subid 1284
@assert {
@@ -129,7 +129,7 @@
@syntax {
- @subid 1245
+ @subid 1285
@assert {
@@ -152,7 +152,7 @@
@syntax {
- @subid 1246
+ @subid 1286
@assert {
@@ -181,7 +181,7 @@
@syntax {
- @subid 1247
+ @subid 1287
@assert {
@@ -204,7 +204,7 @@
@syntax {
- @subid 1248
+ @subid 1288
@assert {
@@ -227,7 +227,7 @@
@syntax {
- @subid 1249
+ @subid 1289
@assert {
@@ -250,7 +250,7 @@
@syntax {
- @subid 1250
+ @subid 1290
@assert {
@@ -273,7 +273,7 @@
@syntax {
- @subid 1251
+ @subid 1291
@assert {
@@ -296,7 +296,7 @@
@syntax {
- @subid 1252
+ @subid 1292
@assert {
diff --git a/plugins/arm/v7/opdefs/A88315_veor.d b/plugins/arm/v7/opdefs/A88315_veor.d
index 43a2983..e722727 100644
--- a/plugins/arm/v7/opdefs/A88315_veor.d
+++ b/plugins/arm/v7/opdefs/A88315_veor.d
@@ -23,7 +23,7 @@
@title VEOR
-@id 303
+@id 307
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1253
+ @subid 1293
@assert {
@@ -59,7 +59,7 @@
@syntax {
- @subid 1254
+ @subid 1294
@assert {
@@ -87,7 +87,7 @@
@syntax {
- @subid 1255
+ @subid 1295
@assert {
@@ -109,7 +109,7 @@
@syntax {
- @subid 1256
+ @subid 1296
@assert {
diff --git a/plugins/arm/v7/opdefs/A88316_vext.d b/plugins/arm/v7/opdefs/A88316_vext.d
new file mode 100644
index 0000000..285e2ec
--- /dev/null
+++ b/plugins/arm/v7/opdefs/A88316_vext.d
@@ -0,0 +1,137 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2017 Cyrille Bagard
+ *
+ * This file is part of Chrysalide.
+ *
+ * Chrysalide is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * Chrysalide is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title VEXT
+
+@id 308
+
+@desc {
+
+ Vector Extract extracts elements from the bottom end of the second operand vector and the top end of the first, concatenates them and places the result in the destination vector. See Figure A8-1 for an example. The elements of the vectors are treated as being 8-bit fields. There is no distinction between data types. 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Vm Vn Vd Figure A8-1 VEXT doubleword operation for imm = 3 Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of access controls for Advanced SIMD functionality on page B1-1232 summarizes these controls. ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available as a VFP instruction encoding, see Conditional execution on page A8-288.
+
+}
+
+@encoding (T1) {
+
+ @word 1 1 1 0 1 1 1 1 1 D(1) 1 1 Vn(4) Vd(4) imm4(4) N(1) Q(1) M(1) 0 Vm(4)
+
+ @syntax {
+
+ @subid 1297
+
+ @assert {
+
+ Q == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+ imm = Multiplication(8, imm4)
+
+ }
+
+ @asm vext.8 ?qwvec_D qwvec_N qwvec_M imm
+
+ }
+
+ @syntax {
+
+ @subid 1298
+
+ @assert {
+
+ Q == 0
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+ imm = Multiplication(8, imm4)
+
+ }
+
+ @asm vext.8 ?dwvec_D dwvec_N dwvec_M imm
+
+ }
+
+}
+
+@encoding (A1) {
+
+ @word 1 1 1 0 1 1 1 1 1 D(1) 1 1 Vn(4) Vd(4) imm4(4) N(1) Q(1) M(1) 0 Vm(4)
+
+ @syntax {
+
+ @subid 1299
+
+ @assert {
+
+ Q == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+ imm = Multiplication(8, imm4)
+
+ }
+
+ @asm vext.8 ?qwvec_D qwvec_N qwvec_M imm
+
+ }
+
+ @syntax {
+
+ @subid 1300
+
+ @assert {
+
+ Q == 0
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+ imm = Multiplication(8, imm4)
+
+ }
+
+ @asm vext.8 ?dwvec_D dwvec_N dwvec_M imm
+
+ }
+
+}
+
diff --git a/plugins/arm/v7/opdefs/A88317_vfm.d b/plugins/arm/v7/opdefs/A88317_vfm.d
index 7e29823..f0c1f9e 100644
--- a/plugins/arm/v7/opdefs/A88317_vfm.d
+++ b/plugins/arm/v7/opdefs/A88317_vfm.d
@@ -23,7 +23,7 @@
@title VFMA, VFMS
-@id 304
+@id 309
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1257
+ @subid 1301
@assert {
@@ -61,7 +61,7 @@
@syntax {
- @subid 1258
+ @subid 1302
@assert {
@@ -85,7 +85,7 @@
@syntax {
- @subid 1259
+ @subid 1303
@assert {
@@ -109,7 +109,7 @@
@syntax {
- @subid 1260
+ @subid 1304
@assert {
@@ -139,7 +139,7 @@
@syntax {
- @subid 1261
+ @subid 1305
@assert {
@@ -162,7 +162,7 @@
@syntax {
- @subid 1262
+ @subid 1306
@assert {
@@ -185,7 +185,7 @@
@syntax {
- @subid 1263
+ @subid 1307
@assert {
@@ -208,7 +208,7 @@
@syntax {
- @subid 1264
+ @subid 1308
@assert {
@@ -237,7 +237,7 @@
@syntax {
- @subid 1265
+ @subid 1309
@assert {
@@ -261,7 +261,7 @@
@syntax {
- @subid 1266
+ @subid 1310
@assert {
@@ -285,7 +285,7 @@
@syntax {
- @subid 1267
+ @subid 1311
@assert {
@@ -309,7 +309,7 @@
@syntax {
- @subid 1268
+ @subid 1312
@assert {
@@ -339,7 +339,7 @@
@syntax {
- @subid 1269
+ @subid 1313
@assert {
@@ -362,7 +362,7 @@
@syntax {
- @subid 1270
+ @subid 1314
@assert {
@@ -385,7 +385,7 @@
@syntax {
- @subid 1271
+ @subid 1315
@assert {
@@ -408,7 +408,7 @@
@syntax {
- @subid 1272
+ @subid 1316
@assert {
diff --git a/plugins/arm/v7/opdefs/A88318_vfnm.d b/plugins/arm/v7/opdefs/A88318_vfnm.d
index 55fb5c6..78adeb2 100644
--- a/plugins/arm/v7/opdefs/A88318_vfnm.d
+++ b/plugins/arm/v7/opdefs/A88318_vfnm.d
@@ -23,7 +23,7 @@
@title VFNMA, VFNMS
-@id 305
+@id 310
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1273
+ @subid 1317
@assert {
@@ -60,7 +60,7 @@
@syntax {
- @subid 1274
+ @subid 1318
@assert {
@@ -83,7 +83,7 @@
@syntax {
- @subid 1275
+ @subid 1319
@assert {
@@ -106,7 +106,7 @@
@syntax {
- @subid 1276
+ @subid 1320
@assert {
@@ -135,7 +135,7 @@
@syntax {
- @subid 1277
+ @subid 1321
@assert {
@@ -158,7 +158,7 @@
@syntax {
- @subid 1278
+ @subid 1322
@assert {
@@ -181,7 +181,7 @@
@syntax {
- @subid 1279
+ @subid 1323
@assert {
@@ -204,7 +204,7 @@
@syntax {
- @subid 1280
+ @subid 1324
@assert {
diff --git a/plugins/arm/v7/opdefs/A88319_vh.d b/plugins/arm/v7/opdefs/A88319_vh.d
index 1ee7888..5311f11 100644
--- a/plugins/arm/v7/opdefs/A88319_vh.d
+++ b/plugins/arm/v7/opdefs/A88319_vh.d
@@ -23,7 +23,7 @@
@title VHADD, VHSUB
-@id 306
+@id 311
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1281
+ @subid 1325
@assert {
@@ -62,7 +62,7 @@
@syntax {
- @subid 1282
+ @subid 1326
@assert {
@@ -87,7 +87,7 @@
@syntax {
- @subid 1283
+ @subid 1327
@assert {
@@ -112,7 +112,7 @@
@syntax {
- @subid 1284
+ @subid 1328
@assert {
@@ -137,7 +137,7 @@
@syntax {
- @subid 1285
+ @subid 1329
@assert {
@@ -162,7 +162,7 @@
@syntax {
- @subid 1286
+ @subid 1330
@assert {
@@ -187,7 +187,7 @@
@syntax {
- @subid 1287
+ @subid 1331
@assert {
@@ -212,7 +212,7 @@
@syntax {
- @subid 1288
+ @subid 1332
@assert {
@@ -237,7 +237,7 @@
@syntax {
- @subid 1289
+ @subid 1333
@assert {
@@ -262,7 +262,7 @@
@syntax {
- @subid 1290
+ @subid 1334
@assert {
@@ -287,7 +287,7 @@
@syntax {
- @subid 1291
+ @subid 1335
@assert {
@@ -312,7 +312,7 @@
@syntax {
- @subid 1292
+ @subid 1336
@assert {
@@ -337,7 +337,7 @@
@syntax {
- @subid 1293
+ @subid 1337
@assert {
@@ -362,7 +362,7 @@
@syntax {
- @subid 1294
+ @subid 1338
@assert {
@@ -387,7 +387,7 @@
@syntax {
- @subid 1295
+ @subid 1339
@assert {
@@ -412,7 +412,7 @@
@syntax {
- @subid 1296
+ @subid 1340
@assert {
@@ -437,7 +437,7 @@
@syntax {
- @subid 1297
+ @subid 1341
@assert {
@@ -462,7 +462,7 @@
@syntax {
- @subid 1298
+ @subid 1342
@assert {
@@ -487,7 +487,7 @@
@syntax {
- @subid 1299
+ @subid 1343
@assert {
@@ -512,7 +512,7 @@
@syntax {
- @subid 1300
+ @subid 1344
@assert {
@@ -537,7 +537,7 @@
@syntax {
- @subid 1301
+ @subid 1345
@assert {
@@ -562,7 +562,7 @@
@syntax {
- @subid 1302
+ @subid 1346
@assert {
@@ -587,7 +587,7 @@
@syntax {
- @subid 1303
+ @subid 1347
@assert {
@@ -612,7 +612,7 @@
@syntax {
- @subid 1304
+ @subid 1348
@assert {
@@ -643,7 +643,7 @@
@syntax {
- @subid 1305
+ @subid 1349
@assert {
@@ -668,7 +668,7 @@
@syntax {
- @subid 1306
+ @subid 1350
@assert {
@@ -693,7 +693,7 @@
@syntax {
- @subid 1307
+ @subid 1351
@assert {
@@ -718,7 +718,7 @@
@syntax {
- @subid 1308
+ @subid 1352
@assert {
@@ -743,7 +743,7 @@
@syntax {
- @subid 1309
+ @subid 1353
@assert {
@@ -768,7 +768,7 @@
@syntax {
- @subid 1310
+ @subid 1354
@assert {
@@ -793,7 +793,7 @@
@syntax {
- @subid 1311
+ @subid 1355
@assert {
@@ -818,7 +818,7 @@
@syntax {
- @subid 1312
+ @subid 1356
@assert {
@@ -843,7 +843,7 @@
@syntax {
- @subid 1313
+ @subid 1357
@assert {
@@ -868,7 +868,7 @@
@syntax {
- @subid 1314
+ @subid 1358
@assert {
@@ -893,7 +893,7 @@
@syntax {
- @subid 1315
+ @subid 1359
@assert {
@@ -918,7 +918,7 @@
@syntax {
- @subid 1316
+ @subid 1360
@assert {
@@ -943,7 +943,7 @@
@syntax {
- @subid 1317
+ @subid 1361
@assert {
@@ -968,7 +968,7 @@
@syntax {
- @subid 1318
+ @subid 1362
@assert {
@@ -993,7 +993,7 @@
@syntax {
- @subid 1319
+ @subid 1363
@assert {
@@ -1018,7 +1018,7 @@
@syntax {
- @subid 1320
+ @subid 1364
@assert {
@@ -1043,7 +1043,7 @@
@syntax {
- @subid 1321
+ @subid 1365
@assert {
@@ -1068,7 +1068,7 @@
@syntax {
- @subid 1322
+ @subid 1366
@assert {
@@ -1093,7 +1093,7 @@
@syntax {
- @subid 1323
+ @subid 1367
@assert {
@@ -1118,7 +1118,7 @@
@syntax {
- @subid 1324
+ @subid 1368
@assert {
@@ -1143,7 +1143,7 @@
@syntax {
- @subid 1325
+ @subid 1369
@assert {
@@ -1168,7 +1168,7 @@
@syntax {
- @subid 1326
+ @subid 1370
@assert {
@@ -1193,7 +1193,7 @@
@syntax {
- @subid 1327
+ @subid 1371
@assert {
@@ -1218,7 +1218,7 @@
@syntax {
- @subid 1328
+ @subid 1372
@assert {
diff --git a/plugins/arm/v7/opdefs/A88334_vmax.d b/plugins/arm/v7/opdefs/A88334_vmax.d
index 98b1ffe..b695d70 100644
--- a/plugins/arm/v7/opdefs/A88334_vmax.d
+++ b/plugins/arm/v7/opdefs/A88334_vmax.d
@@ -23,7 +23,7 @@
@title VMAX, VMIN (integer)
-@id 307
+@id 312
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1329
+ @subid 1373
@assert {
@@ -62,7 +62,7 @@
@syntax {
- @subid 1330
+ @subid 1374
@assert {
@@ -87,7 +87,7 @@
@syntax {
- @subid 1331
+ @subid 1375
@assert {
@@ -112,7 +112,7 @@
@syntax {
- @subid 1332
+ @subid 1376
@assert {
@@ -137,7 +137,7 @@
@syntax {
- @subid 1333
+ @subid 1377
@assert {
@@ -162,7 +162,7 @@
@syntax {
- @subid 1334
+ @subid 1378
@assert {
@@ -187,7 +187,7 @@
@syntax {
- @subid 1335
+ @subid 1379
@assert {
@@ -212,7 +212,7 @@
@syntax {
- @subid 1336
+ @subid 1380
@assert {
@@ -237,7 +237,7 @@
@syntax {
- @subid 1337
+ @subid 1381
@assert {
@@ -262,7 +262,7 @@
@syntax {
- @subid 1338
+ @subid 1382
@assert {
@@ -287,7 +287,7 @@
@syntax {
- @subid 1339
+ @subid 1383
@assert {
@@ -312,7 +312,7 @@
@syntax {
- @subid 1340
+ @subid 1384
@assert {
@@ -337,7 +337,7 @@
@syntax {
- @subid 1341
+ @subid 1385
@assert {
@@ -362,7 +362,7 @@
@syntax {
- @subid 1342
+ @subid 1386
@assert {
@@ -387,7 +387,7 @@
@syntax {
- @subid 1343
+ @subid 1387
@assert {
@@ -412,7 +412,7 @@
@syntax {
- @subid 1344
+ @subid 1388
@assert {
@@ -437,7 +437,7 @@
@syntax {
- @subid 1345
+ @subid 1389
@assert {
@@ -462,7 +462,7 @@
@syntax {
- @subid 1346
+ @subid 1390
@assert {
@@ -487,7 +487,7 @@
@syntax {
- @subid 1347
+ @subid 1391
@assert {
@@ -512,7 +512,7 @@
@syntax {
- @subid 1348
+ @subid 1392
@assert {
@@ -537,7 +537,7 @@
@syntax {
- @subid 1349
+ @subid 1393
@assert {
@@ -562,7 +562,7 @@
@syntax {
- @subid 1350
+ @subid 1394
@assert {
@@ -587,7 +587,7 @@
@syntax {
- @subid 1351
+ @subid 1395
@assert {
@@ -612,7 +612,7 @@
@syntax {
- @subid 1352
+ @subid 1396
@assert {
@@ -643,7 +643,7 @@
@syntax {
- @subid 1353
+ @subid 1397
@assert {
@@ -668,7 +668,7 @@
@syntax {
- @subid 1354
+ @subid 1398
@assert {
@@ -693,7 +693,7 @@
@syntax {
- @subid 1355
+ @subid 1399
@assert {
@@ -718,7 +718,7 @@
@syntax {
- @subid 1356
+ @subid 1400
@assert {
@@ -743,7 +743,7 @@
@syntax {
- @subid 1357
+ @subid 1401
@assert {
@@ -768,7 +768,7 @@
@syntax {
- @subid 1358
+ @subid 1402
@assert {
@@ -793,7 +793,7 @@
@syntax {
- @subid 1359
+ @subid 1403
@assert {
@@ -818,7 +818,7 @@
@syntax {
- @subid 1360
+ @subid 1404
@assert {
@@ -843,7 +843,7 @@
@syntax {
- @subid 1361
+ @subid 1405
@assert {
@@ -868,7 +868,7 @@
@syntax {
- @subid 1362
+ @subid 1406
@assert {
@@ -893,7 +893,7 @@
@syntax {
- @subid 1363
+ @subid 1407
@assert {
@@ -918,7 +918,7 @@
@syntax {
- @subid 1364
+ @subid 1408
@assert {
@@ -943,7 +943,7 @@
@syntax {
- @subid 1365
+ @subid 1409
@assert {
@@ -968,7 +968,7 @@
@syntax {
- @subid 1366
+ @subid 1410
@assert {
@@ -993,7 +993,7 @@
@syntax {
- @subid 1367
+ @subid 1411
@assert {
@@ -1018,7 +1018,7 @@
@syntax {
- @subid 1368
+ @subid 1412
@assert {
@@ -1043,7 +1043,7 @@
@syntax {
- @subid 1369
+ @subid 1413
@assert {
@@ -1068,7 +1068,7 @@
@syntax {
- @subid 1370
+ @subid 1414
@assert {
@@ -1093,7 +1093,7 @@
@syntax {
- @subid 1371
+ @subid 1415
@assert {
@@ -1118,7 +1118,7 @@
@syntax {
- @subid 1372
+ @subid 1416
@assert {
@@ -1143,7 +1143,7 @@
@syntax {
- @subid 1373
+ @subid 1417
@assert {
@@ -1168,7 +1168,7 @@
@syntax {
- @subid 1374
+ @subid 1418
@assert {
@@ -1193,7 +1193,7 @@
@syntax {
- @subid 1375
+ @subid 1419
@assert {
@@ -1218,7 +1218,7 @@
@syntax {
- @subid 1376
+ @subid 1420
@assert {
diff --git a/plugins/arm/v7/opdefs/A88335_vmax.d b/plugins/arm/v7/opdefs/A88335_vmax.d
index 1cb6d40..d14313e 100644
--- a/plugins/arm/v7/opdefs/A88335_vmax.d
+++ b/plugins/arm/v7/opdefs/A88335_vmax.d
@@ -23,7 +23,7 @@
@title VMAX, VMIN (floating-point)
-@id 308
+@id 313
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1377
+ @subid 1421
@assert {
@@ -60,7 +60,7 @@
@syntax {
- @subid 1378
+ @subid 1422
@assert {
@@ -83,7 +83,7 @@
@syntax {
- @subid 1379
+ @subid 1423
@assert {
@@ -106,7 +106,7 @@
@syntax {
- @subid 1380
+ @subid 1424
@assert {
@@ -135,7 +135,7 @@
@syntax {
- @subid 1381
+ @subid 1425
@assert {
@@ -158,7 +158,7 @@
@syntax {
- @subid 1382
+ @subid 1426
@assert {
@@ -181,7 +181,7 @@
@syntax {
- @subid 1383
+ @subid 1427
@assert {
@@ -204,7 +204,7 @@
@syntax {
- @subid 1384
+ @subid 1428
@assert {
diff --git a/plugins/arm/v7/opdefs/A88336_vmla.d b/plugins/arm/v7/opdefs/A88336_vmla.d
new file mode 100644
index 0000000..93f0161
--- /dev/null
+++ b/plugins/arm/v7/opdefs/A88336_vmla.d
@@ -0,0 +1,1209 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2017 Cyrille Bagard
+ *
+ * This file is part of Chrysalide.
+ *
+ * Chrysalide is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * Chrysalide is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title VMLA, VMLAL, VMLS, VMLSL (integer)
+
+@id 314
+
+@desc {
+
+ Vector Multiply Accumulate and Vector Multiply Subtract multiply corresponding elements in two vectors, and either add the products to, or subtract them from, the corresponding elements of the destination vector. Vector Multiply Accumulate Long and Vector Multiply Subtract Long do the same thing, but with destination vector elements that are twice as long as the elements that are multiplied. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of access controls for Advanced SIMD functionality on page B1-1232 summarizes these controls. ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available as a VFP instruction encoding, see Conditional execution on page A8-288.
+
+}
+
+@encoding (T1) {
+
+ @word 1 1 1 op(1) 1 1 1 1 0 D(1) size(2) Vn(4) Vd(4) 1 0 0 1 N(1) Q(1) M(1) 0 Vm(4)
+
+ @syntax {
+
+ @subid 1429
+
+ @assert {
+
+ Q == 1
+ op == 0
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vmla.i8 qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1430
+
+ @assert {
+
+ Q == 1
+ op == 0
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vmla.i16 qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1431
+
+ @assert {
+
+ Q == 1
+ op == 0
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vmla.i32 qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1432
+
+ @assert {
+
+ Q == 1
+ op == 1
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vmls.i8 qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1433
+
+ @assert {
+
+ Q == 1
+ op == 1
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vmls.i16 qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1434
+
+ @assert {
+
+ Q == 1
+ op == 1
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vmls.i32 qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1435
+
+ @assert {
+
+ Q == 0
+ op == 0
+ size == 0
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmla.i8 dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1436
+
+ @assert {
+
+ Q == 0
+ op == 0
+ size == 1
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmla.i16 dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1437
+
+ @assert {
+
+ Q == 0
+ op == 0
+ size == 10
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmla.i32 dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1438
+
+ @assert {
+
+ Q == 0
+ op == 1
+ size == 0
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmls.i8 dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1439
+
+ @assert {
+
+ Q == 0
+ op == 1
+ size == 1
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmls.i16 dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1440
+
+ @assert {
+
+ Q == 0
+ op == 1
+ size == 10
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmls.i32 dwvec_D dwvec_N dwvec_M
+
+ }
+
+}
+
+@encoding (T2) {
+
+ @word 1 1 1 U(1) 1 1 1 1 1 D(1) size(2) Vn(4) Vd(4) 1 0 op(1) 0 N(1) 0 M(1) 0 Vm(4)
+
+ @syntax {
+
+ @subid 1441
+
+ @assert {
+
+ op == 0
+ U == 0
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmlal.s8 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1442
+
+ @assert {
+
+ op == 0
+ U == 0
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmlal.s16 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1443
+
+ @assert {
+
+ op == 0
+ U == 0
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmlal.s32 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1444
+
+ @assert {
+
+ op == 0
+ U == 1
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmlal.u8 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1445
+
+ @assert {
+
+ op == 0
+ U == 1
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmlal.u16 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1446
+
+ @assert {
+
+ op == 0
+ U == 1
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmlal.u32 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1447
+
+ @assert {
+
+ op == 1
+ U == 0
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmlsl.s8 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1448
+
+ @assert {
+
+ op == 1
+ U == 0
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmlsl.s16 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1449
+
+ @assert {
+
+ op == 1
+ U == 0
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmlsl.s32 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1450
+
+ @assert {
+
+ op == 1
+ U == 1
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmlsl.u8 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1451
+
+ @assert {
+
+ op == 1
+ U == 1
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmlsl.u16 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1452
+
+ @assert {
+
+ op == 1
+ U == 1
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmlsl.u32 qwvec_D dwvec_N dwvec_M
+
+ }
+
+}
+
+@encoding (A1) {
+
+ @word 1 1 1 op(1) 1 1 1 1 0 D(1) size(2) Vn(4) Vd(4) 1 0 0 1 N(1) Q(1) M(1) 0 Vm(4)
+
+ @syntax {
+
+ @subid 1453
+
+ @assert {
+
+ Q == 1
+ op == 0
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vmla.i8 qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1454
+
+ @assert {
+
+ Q == 1
+ op == 0
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vmla.i16 qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1455
+
+ @assert {
+
+ Q == 1
+ op == 0
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vmla.i32 qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1456
+
+ @assert {
+
+ Q == 1
+ op == 1
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vmls.i8 qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1457
+
+ @assert {
+
+ Q == 1
+ op == 1
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vmls.i16 qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1458
+
+ @assert {
+
+ Q == 1
+ op == 1
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vmls.i32 qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1459
+
+ @assert {
+
+ Q == 0
+ op == 0
+ size == 0
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmla.i8 dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1460
+
+ @assert {
+
+ Q == 0
+ op == 0
+ size == 1
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmla.i16 dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1461
+
+ @assert {
+
+ Q == 0
+ op == 0
+ size == 10
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmla.i32 dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1462
+
+ @assert {
+
+ Q == 0
+ op == 1
+ size == 0
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmls.i8 dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1463
+
+ @assert {
+
+ Q == 0
+ op == 1
+ size == 1
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmls.i16 dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1464
+
+ @assert {
+
+ Q == 0
+ op == 1
+ size == 10
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmls.i32 dwvec_D dwvec_N dwvec_M
+
+ }
+
+}
+
+@encoding (A2) {
+
+ @word 1 1 1 U(1) 1 1 1 1 1 D(1) size(2) Vn(4) Vd(4) 1 0 op(1) 0 N(1) 0 M(1) 0 Vm(4)
+
+ @syntax {
+
+ @subid 1465
+
+ @assert {
+
+ op == 0
+ U == 0
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmlal.s8 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1466
+
+ @assert {
+
+ op == 0
+ U == 0
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmlal.s16 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1467
+
+ @assert {
+
+ op == 0
+ U == 0
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmlal.s32 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1468
+
+ @assert {
+
+ op == 0
+ U == 1
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmlal.u8 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1469
+
+ @assert {
+
+ op == 0
+ U == 1
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmlal.u16 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1470
+
+ @assert {
+
+ op == 0
+ U == 1
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmlal.u32 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1471
+
+ @assert {
+
+ op == 1
+ U == 0
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmlsl.s8 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1472
+
+ @assert {
+
+ op == 1
+ U == 0
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmlsl.s16 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1473
+
+ @assert {
+
+ op == 1
+ U == 0
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmlsl.s32 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1474
+
+ @assert {
+
+ op == 1
+ U == 1
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmlsl.u8 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1475
+
+ @assert {
+
+ op == 1
+ U == 1
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmlsl.u16 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1476
+
+ @assert {
+
+ op == 1
+ U == 1
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmlsl.u32 qwvec_D dwvec_N dwvec_M
+
+ }
+
+}
+
diff --git a/plugins/arm/v7/opdefs/A88337_vmla.d b/plugins/arm/v7/opdefs/A88337_vmla.d
index e124a30..94d2817 100644
--- a/plugins/arm/v7/opdefs/A88337_vmla.d
+++ b/plugins/arm/v7/opdefs/A88337_vmla.d
@@ -23,7 +23,7 @@
@title VMLA, VMLS (floating-point)
-@id 309
+@id 315
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1385
+ @subid 1477
@assert {
@@ -61,7 +61,7 @@
@syntax {
- @subid 1386
+ @subid 1478
@assert {
@@ -85,7 +85,7 @@
@syntax {
- @subid 1387
+ @subid 1479
@assert {
@@ -109,7 +109,7 @@
@syntax {
- @subid 1388
+ @subid 1480
@assert {
@@ -139,7 +139,7 @@
@syntax {
- @subid 1389
+ @subid 1481
@assert {
@@ -162,7 +162,7 @@
@syntax {
- @subid 1390
+ @subid 1482
@assert {
@@ -185,7 +185,7 @@
@syntax {
- @subid 1391
+ @subid 1483
@assert {
@@ -208,7 +208,7 @@
@syntax {
- @subid 1392
+ @subid 1484
@assert {
@@ -237,7 +237,7 @@
@syntax {
- @subid 1393
+ @subid 1485
@assert {
@@ -261,7 +261,7 @@
@syntax {
- @subid 1394
+ @subid 1486
@assert {
@@ -285,7 +285,7 @@
@syntax {
- @subid 1395
+ @subid 1487
@assert {
@@ -309,7 +309,7 @@
@syntax {
- @subid 1396
+ @subid 1488
@assert {
@@ -339,7 +339,7 @@
@syntax {
- @subid 1397
+ @subid 1489
@assert {
@@ -362,7 +362,7 @@
@syntax {
- @subid 1398
+ @subid 1490
@assert {
@@ -385,7 +385,7 @@
@syntax {
- @subid 1399
+ @subid 1491
@assert {
@@ -408,7 +408,7 @@
@syntax {
- @subid 1400
+ @subid 1492
@assert {
diff --git a/plugins/arm/v7/opdefs/A88343_vmov.d b/plugins/arm/v7/opdefs/A88343_vmov.d
new file mode 100644
index 0000000..1607415
--- /dev/null
+++ b/plugins/arm/v7/opdefs/A88343_vmov.d
@@ -0,0 +1,129 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2017 Cyrille Bagard
+ *
+ * This file is part of Chrysalide.
+ *
+ * Chrysalide is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * Chrysalide is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title VMOV (between ARM core register and single-precision register)
+
+@id 316
+
+@desc {
+
+ This instruction transfers the contents of a single-precision Floating-point register to an ARM core register, or the contents of an ARM core register to a single-precision Floating-point register. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of general controls of CP10 and CP11 functionality on page B1-1230 summarizes these controls.
+
+}
+
+@encoding (T1) {
+
+ @word 1 1 1 0 1 1 1 0 0 0 0 op(1) Vn(4) Rt(4) 1 0 1 0 N(1) 0 0 1 0 0 0 0
+
+ @syntax {
+
+ @subid 1493
+
+ @assert {
+
+ op == 0
+
+ }
+
+ @conv {
+
+ swvec_N = SingleWordVector(Vn:N)
+ reg_T = Register(Rt)
+
+ }
+
+ @asm vmov swvec_N reg_T
+
+ }
+
+ @syntax {
+
+ @subid 1494
+
+ @assert {
+
+ op == 1
+
+ }
+
+ @conv {
+
+ reg_T = Register(Rt)
+ swvec_N = SingleWordVector(Vn:N)
+
+ }
+
+ @asm vmov reg_T swvec_N
+
+ }
+
+}
+
+@encoding (A1) {
+
+ @word 1 1 1 0 1 1 1 0 0 0 0 op(1) Vn(4) Rt(4) 1 0 1 0 N(1) 0 0 1 0 0 0 0
+
+ @syntax {
+
+ @subid 1495
+
+ @assert {
+
+ op == 0
+
+ }
+
+ @conv {
+
+ swvec_N = SingleWordVector(Vn:N)
+ reg_T = Register(Rt)
+
+ }
+
+ @asm vmov swvec_N reg_T
+
+ }
+
+ @syntax {
+
+ @subid 1496
+
+ @assert {
+
+ op == 1
+
+ }
+
+ @conv {
+
+ reg_T = Register(Rt)
+ swvec_N = SingleWordVector(Vn:N)
+
+ }
+
+ @asm vmov reg_T swvec_N
+
+ }
+
+}
+
diff --git a/plugins/arm/v7/opdefs/A88344_vmov.d b/plugins/arm/v7/opdefs/A88344_vmov.d
new file mode 100644
index 0000000..a3de0b8
--- /dev/null
+++ b/plugins/arm/v7/opdefs/A88344_vmov.d
@@ -0,0 +1,137 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2017 Cyrille Bagard
+ *
+ * This file is part of Chrysalide.
+ *
+ * Chrysalide is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * Chrysalide is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title VMOV (between two ARM core registers and two single-precision registers)
+
+@id 317
+
+@desc {
+
+ This instruction transfers the contents of two consecutively numbered single-precision Floating-point registers to two ARM core registers, or the contents of two ARM core registers to a pair of single-precision Floating-point registers. The ARM core registers do not have to be contiguous. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of general controls of CP10 and CP11 functionality on page B1-1230 summarizes these controls.
+
+}
+
+@encoding (T1) {
+
+ @word 1 1 1 0 1 1 0 0 0 1 0 op(1) Rt2(4) Rt(4) 1 0 1 0 0 0 M(1) 1 Vm(4)
+
+ @syntax {
+
+ @subid 1497
+
+ @assert {
+
+ op == 0
+
+ }
+
+ @conv {
+
+ swvec_M = SingleWordVector(Vm:M)
+ reg_Sm1 = NexSingleWordVector(swvec_M)
+ reg_T = Register(Rt)
+ reg_T2 = Register(Rt2)
+
+ }
+
+ @asm vmov swvec_M reg_Sm1 reg_T reg_T2
+
+ }
+
+ @syntax {
+
+ @subid 1498
+
+ @assert {
+
+ op == 1
+
+ }
+
+ @conv {
+
+ reg_T = Register(Rt)
+ reg_T2 = Register(Rt2)
+ swvec_M = SingleWordVector(Vm:M)
+ reg_Sm1 = NexSingleWordVector(swvec_M)
+
+ }
+
+ @asm vmov reg_T reg_T2 swvec_M reg_Sm1
+
+ }
+
+}
+
+@encoding (A1) {
+
+ @word 1 1 1 0 1 1 0 0 0 1 0 op(1) Rt2(4) Rt(4) 1 0 1 0 0 0 M(1) 1 Vm(4)
+
+ @syntax {
+
+ @subid 1499
+
+ @assert {
+
+ op == 0
+
+ }
+
+ @conv {
+
+ swvec_M = SingleWordVector(Vm:M)
+ reg_Sm1 = NexSingleWordVector(swvec_M)
+ reg_T = Register(Rt)
+ reg_T2 = Register(Rt2)
+
+ }
+
+ @asm vmov swvec_M reg_Sm1 reg_T reg_T2
+
+ }
+
+ @syntax {
+
+ @subid 1500
+
+ @assert {
+
+ op == 1
+
+ }
+
+ @conv {
+
+ reg_T = Register(Rt)
+ reg_T2 = Register(Rt2)
+ swvec_M = SingleWordVector(Vm:M)
+ reg_Sm1 = NexSingleWordVector(swvec_M)
+
+ }
+
+ @asm vmov reg_T reg_T2 swvec_M reg_Sm1
+
+ }
+
+}
+
diff --git a/plugins/arm/v7/opdefs/A88345_vmov.d b/plugins/arm/v7/opdefs/A88345_vmov.d
index f6b9d31..18c6dfa 100644
--- a/plugins/arm/v7/opdefs/A88345_vmov.d
+++ b/plugins/arm/v7/opdefs/A88345_vmov.d
@@ -23,7 +23,7 @@
@title VMOV (between two ARM core registers and a doubleword extension register)
-@id 310
+@id 318
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1401
+ @subid 1501
@assert {
@@ -59,7 +59,7 @@
@syntax {
- @subid 1402
+ @subid 1502
@assert {
@@ -87,7 +87,7 @@
@syntax {
- @subid 1403
+ @subid 1503
@assert {
@@ -109,7 +109,7 @@
@syntax {
- @subid 1404
+ @subid 1504
@assert {
diff --git a/plugins/arm/v7/opdefs/A88346_vmovl.d b/plugins/arm/v7/opdefs/A88346_vmovl.d
index 6e0c15a..4c73e88 100644
--- a/plugins/arm/v7/opdefs/A88346_vmovl.d
+++ b/plugins/arm/v7/opdefs/A88346_vmovl.d
@@ -23,7 +23,7 @@
@title VMOVL
-@id 311
+@id 319
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1405
+ @subid 1505
@assert {
@@ -59,7 +59,7 @@
@syntax {
- @subid 1406
+ @subid 1506
@assert {
@@ -81,7 +81,7 @@
@syntax {
- @subid 1407
+ @subid 1507
@assert {
@@ -103,7 +103,7 @@
@syntax {
- @subid 1408
+ @subid 1508
@assert {
@@ -125,7 +125,7 @@
@syntax {
- @subid 1409
+ @subid 1509
@assert {
@@ -147,7 +147,7 @@
@syntax {
- @subid 1410
+ @subid 1510
@assert {
@@ -175,7 +175,7 @@
@syntax {
- @subid 1411
+ @subid 1511
@assert {
@@ -197,7 +197,7 @@
@syntax {
- @subid 1412
+ @subid 1512
@assert {
@@ -219,7 +219,7 @@
@syntax {
- @subid 1413
+ @subid 1513
@assert {
@@ -241,7 +241,7 @@
@syntax {
- @subid 1414
+ @subid 1514
@assert {
@@ -263,7 +263,7 @@
@syntax {
- @subid 1415
+ @subid 1515
@assert {
@@ -285,7 +285,7 @@
@syntax {
- @subid 1416
+ @subid 1516
@assert {
diff --git a/plugins/arm/v7/opdefs/A88347_vmovn.d b/plugins/arm/v7/opdefs/A88347_vmovn.d
index bcb00a2..1f9f1a1 100644
--- a/plugins/arm/v7/opdefs/A88347_vmovn.d
+++ b/plugins/arm/v7/opdefs/A88347_vmovn.d
@@ -23,7 +23,7 @@
@title VMOVN
-@id 312
+@id 320
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1417
+ @subid 1517
@assert {
@@ -58,7 +58,7 @@
@syntax {
- @subid 1418
+ @subid 1518
@assert {
@@ -79,7 +79,7 @@
@syntax {
- @subid 1419
+ @subid 1519
@assert {
@@ -106,7 +106,7 @@
@syntax {
- @subid 1420
+ @subid 1520
@assert {
@@ -127,7 +127,7 @@
@syntax {
- @subid 1421
+ @subid 1521
@assert {
@@ -148,7 +148,7 @@
@syntax {
- @subid 1422
+ @subid 1522
@assert {
diff --git a/plugins/arm/v7/opdefs/A88348_vmrs.d b/plugins/arm/v7/opdefs/A88348_vmrs.d
new file mode 100644
index 0000000..182b77f
--- /dev/null
+++ b/plugins/arm/v7/opdefs/A88348_vmrs.d
@@ -0,0 +1,75 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2017 Cyrille Bagard
+ *
+ * This file is part of Chrysalide.
+ *
+ * Chrysalide is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * Chrysalide is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title VMRS
+
+@id 321
+
+@desc {
+
+ Move to ARM core register from Advanced SIMD and Floating-point Extension System Register moves the value of the FPSCR to an ARM core register. For details of system level use of this instruction, see VMRS on page B9-2012. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of general controls of CP10 and CP11 functionality on page B1-1230 and Summary of access controls for Advanced SIMD functionality on page B1-1232 summarize these controls.
+
+}
+
+@encoding (T1) {
+
+ @word 1 1 1 0 1 1 1 0 1 1 1 1 0 0 0 1 Rt(4) 1 0 1 0 0 0 0 1 0 0 0 0
+
+ @syntax {
+
+ @subid 1523
+
+ @conv {
+
+ reg_T = Register(Rt)
+ reg_FPSCR = SpecReg(SRT_FPSCR)
+
+ }
+
+ @asm vmrs reg_T reg_FPSCR
+
+ }
+
+}
+
+@encoding (A1) {
+
+ @word 1 1 1 0 1 1 1 0 1 1 1 1 0 0 0 1 Rt(4) 1 0 1 0 0 0 0 1 0 0 0 0
+
+ @syntax {
+
+ @subid 1524
+
+ @conv {
+
+ reg_T = Register(Rt)
+ reg_FPSCR = SpecReg(SRT_FPSCR)
+
+ }
+
+ @asm vmrs reg_T reg_FPSCR
+
+ }
+
+}
+
diff --git a/plugins/arm/v7/opdefs/A88349_vmsr.d b/plugins/arm/v7/opdefs/A88349_vmsr.d
new file mode 100644
index 0000000..cda0610
--- /dev/null
+++ b/plugins/arm/v7/opdefs/A88349_vmsr.d
@@ -0,0 +1,75 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2017 Cyrille Bagard
+ *
+ * This file is part of Chrysalide.
+ *
+ * Chrysalide is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * Chrysalide is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title VMSR
+
+@id 322
+
+@desc {
+
+ Move to Advanced SIMD and Floating-point Extension System Register from ARM core register moves the value of an ARM core register to the FPSCR. For details of system level use of this instruction, see VMSR on page B9-2014. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of general controls of CP10 and CP11 functionality on page B1-1230 and Summary of access controls for Advanced SIMD functionality on page B1-1232 summarize these controls.
+
+}
+
+@encoding (T1) {
+
+ @word 1 1 1 0 1 1 1 0 1 1 1 0 0 0 0 1 Rt(4) 1 0 1 0 0 0 0 1 0 0 0 0
+
+ @syntax {
+
+ @subid 1525
+
+ @conv {
+
+ reg_FPSCR = SpecReg(SRT_FPSCR)
+ reg_T = Register(Rt)
+
+ }
+
+ @asm vmsr reg_FPSCR reg_T
+
+ }
+
+}
+
+@encoding (A1) {
+
+ @word 1 1 1 0 1 1 1 0 1 1 1 0 0 0 0 1 Rt(4) 1 0 1 0 0 0 0 1 0 0 0 0
+
+ @syntax {
+
+ @subid 1526
+
+ @conv {
+
+ reg_FPSCR = SpecReg(SRT_FPSCR)
+ reg_T = Register(Rt)
+
+ }
+
+ @asm vmsr reg_FPSCR reg_T
+
+ }
+
+}
+
diff --git a/plugins/arm/v7/opdefs/A88350_vmul.d b/plugins/arm/v7/opdefs/A88350_vmul.d
new file mode 100644
index 0000000..4b1271a
--- /dev/null
+++ b/plugins/arm/v7/opdefs/A88350_vmul.d
@@ -0,0 +1,1065 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2017 Cyrille Bagard
+ *
+ * This file is part of Chrysalide.
+ *
+ * Chrysalide is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * Chrysalide is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title VMUL, VMULL (integer and polynomial)
+
+@id 323
+
+@desc {
+
+ Vector Multiply multiplies corresponding elements in two vectors. Vector Multiply Long does the same thing, but with destination vector elements that are twice as long as the elements that are multiplied. For information about multiplying polynomials see Polynomial arithmetic over {0, 1} on page A2-93. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of access controls for Advanced SIMD functionality on page B1-1232 summarizes these controls. ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available as a VFP instruction encoding, see Conditional execution on page A8-288.
+
+}
+
+@encoding (T1) {
+
+ @word 1 1 1 op(1) 1 1 1 1 0 D(1) size(2) Vn(4) Vd(4) 1 0 0 1 N(1) Q(1) M(1) 1 Vm(4)
+
+ @syntax {
+
+ @subid 1527
+
+ @assert {
+
+ Q == 1
+ op == 0
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vmul.i8 ?qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1528
+
+ @assert {
+
+ Q == 1
+ op == 0
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vmul.i16 ?qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1529
+
+ @assert {
+
+ Q == 1
+ op == 0
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vmul.i32 ?qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1530
+
+ @assert {
+
+ Q == 1
+ op == 1
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vmul.p8 ?qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1531
+
+ @assert {
+
+ Q == 1
+ op == 1
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vmul.p16 ?qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1532
+
+ @assert {
+
+ Q == 1
+ op == 1
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vmul.p32 ?qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1533
+
+ @assert {
+
+ Q == 0
+ op == 0
+ size == 0
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmul.i8 ?dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1534
+
+ @assert {
+
+ Q == 0
+ op == 0
+ size == 1
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmul.i16 ?dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1535
+
+ @assert {
+
+ Q == 0
+ op == 0
+ size == 10
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmul.i32 ?dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1536
+
+ @assert {
+
+ Q == 0
+ op == 1
+ size == 0
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmul.p8 ?dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1537
+
+ @assert {
+
+ Q == 0
+ op == 1
+ size == 1
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmul.p16 ?dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1538
+
+ @assert {
+
+ Q == 0
+ op == 1
+ size == 10
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmul.p32 ?dwvec_D dwvec_N dwvec_M
+
+ }
+
+}
+
+@encoding (T2) {
+
+ @word 1 1 1 U(1) 1 1 1 1 1 D(1) size(2) Vn(4) Vd(4) 1 1 op(1) 0 N(1) 0 M(1) 0 Vm(4)
+
+ @syntax {
+
+ @subid 1539
+
+ @assert {
+
+ op == 0
+ U == 0
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmull.s8 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1540
+
+ @assert {
+
+ op == 0
+ U == 0
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmull.s16 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1541
+
+ @assert {
+
+ op == 0
+ U == 0
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmull.s32 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1542
+
+ @assert {
+
+ op == 0
+ U == 1
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmull.u8 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1543
+
+ @assert {
+
+ op == 0
+ U == 1
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmull.u16 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1544
+
+ @assert {
+
+ op == 0
+ U == 1
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmull.u32 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1545
+
+ @assert {
+
+ op == 1
+ U == 0
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmull.p8 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1546
+
+ @assert {
+
+ op == 1
+ U == 0
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmull.p16 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1547
+
+ @assert {
+
+ op == 1
+ U == 0
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmull.p32 qwvec_D dwvec_N dwvec_M
+
+ }
+
+}
+
+@encoding (A1) {
+
+ @word 1 1 1 op(1) 1 1 1 1 0 D(1) size(2) Vn(4) Vd(4) 1 0 0 1 N(1) Q(1) M(1) 1 Vm(4)
+
+ @syntax {
+
+ @subid 1548
+
+ @assert {
+
+ Q == 1
+ op == 0
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vmul.i8 ?qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1549
+
+ @assert {
+
+ Q == 1
+ op == 0
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vmul.i16 ?qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1550
+
+ @assert {
+
+ Q == 1
+ op == 0
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vmul.i32 ?qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1551
+
+ @assert {
+
+ Q == 1
+ op == 1
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vmul.p8 ?qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1552
+
+ @assert {
+
+ Q == 1
+ op == 1
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vmul.p16 ?qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1553
+
+ @assert {
+
+ Q == 1
+ op == 1
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vmul.p32 ?qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1554
+
+ @assert {
+
+ Q == 0
+ op == 0
+ size == 0
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmul.i8 ?dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1555
+
+ @assert {
+
+ Q == 0
+ op == 0
+ size == 1
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmul.i16 ?dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1556
+
+ @assert {
+
+ Q == 0
+ op == 0
+ size == 10
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmul.i32 ?dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1557
+
+ @assert {
+
+ Q == 0
+ op == 1
+ size == 0
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmul.p8 ?dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1558
+
+ @assert {
+
+ Q == 0
+ op == 1
+ size == 1
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmul.p16 ?dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1559
+
+ @assert {
+
+ Q == 0
+ op == 1
+ size == 10
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmul.p32 ?dwvec_D dwvec_N dwvec_M
+
+ }
+
+}
+
+@encoding (A2) {
+
+ @word 1 1 1 U(1) 1 1 1 1 1 D(1) size(2) Vn(4) Vd(4) 1 1 op(1) 0 N(1) 0 M(1) 0 Vm(4)
+
+ @syntax {
+
+ @subid 1560
+
+ @assert {
+
+ op == 0
+ U == 0
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmull.s8 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1561
+
+ @assert {
+
+ op == 0
+ U == 0
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmull.s16 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1562
+
+ @assert {
+
+ op == 0
+ U == 0
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmull.s32 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1563
+
+ @assert {
+
+ op == 0
+ U == 1
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmull.u8 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1564
+
+ @assert {
+
+ op == 0
+ U == 1
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmull.u16 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1565
+
+ @assert {
+
+ op == 0
+ U == 1
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmull.u32 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1566
+
+ @assert {
+
+ op == 1
+ U == 0
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmull.p8 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1567
+
+ @assert {
+
+ op == 1
+ U == 0
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmull.p16 qwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1568
+
+ @assert {
+
+ op == 1
+ U == 0
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vmull.p32 qwvec_D dwvec_N dwvec_M
+
+ }
+
+}
+
diff --git a/plugins/arm/v7/opdefs/A88351_vmul.d b/plugins/arm/v7/opdefs/A88351_vmul.d
index 032f7bf..4112d08 100644
--- a/plugins/arm/v7/opdefs/A88351_vmul.d
+++ b/plugins/arm/v7/opdefs/A88351_vmul.d
@@ -23,7 +23,7 @@
@title VMUL (floating-point)
-@id 313
+@id 324
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1423
+ @subid 1569
@assert {
@@ -60,7 +60,7 @@
@syntax {
- @subid 1424
+ @subid 1570
@assert {
@@ -89,7 +89,7 @@
@syntax {
- @subid 1425
+ @subid 1571
@assert {
@@ -111,7 +111,7 @@
@syntax {
- @subid 1426
+ @subid 1572
@assert {
@@ -139,7 +139,7 @@
@syntax {
- @subid 1427
+ @subid 1573
@assert {
@@ -162,7 +162,7 @@
@syntax {
- @subid 1428
+ @subid 1574
@assert {
@@ -191,7 +191,7 @@
@syntax {
- @subid 1429
+ @subid 1575
@assert {
@@ -213,7 +213,7 @@
@syntax {
- @subid 1430
+ @subid 1576
@assert {
diff --git a/plugins/arm/v7/opdefs/A88353_vmvn.d b/plugins/arm/v7/opdefs/A88353_vmvn.d
new file mode 100644
index 0000000..2801289
--- /dev/null
+++ b/plugins/arm/v7/opdefs/A88353_vmvn.d
@@ -0,0 +1,1277 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2017 Cyrille Bagard
+ *
+ * This file is part of Chrysalide.
+ *
+ * Chrysalide is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * Chrysalide is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title VMVN (immediate)
+
+@id 325
+
+@desc {
+
+ Vector Bitwise NOT (immediate) places the bitwise inverse of an immediate integer constant into every element of the destination register. For the range of constants available, see One register and a modified immediate value on page A7-269. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of access controls for Advanced SIMD functionality on page B1-1232 summarizes these controls. ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available as a VFP instruction encoding, see Conditional execution on page A8-288.
+
+}
+
+@encoding (T1) {
+
+ @word 1 1 1 i(1) 1 1 1 1 1 D(1) 0 0 0 imm3(3) Vd(4) cmode(4) 0 Q(1) 1 1 imm4(4)
+
+ @syntax {
+
+ @subid 1577
+
+ @assert {
+
+ Q == 1
+ cmode == 1000
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i16 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1578
+
+ @assert {
+
+ Q == 1
+ cmode == 1001
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i16 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1579
+
+ @assert {
+
+ Q == 1
+ cmode == 1010
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i16 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1580
+
+ @assert {
+
+ Q == 1
+ cmode == 1011
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i16 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1581
+
+ @assert {
+
+ Q == 1
+ cmode == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1582
+
+ @assert {
+
+ Q == 1
+ cmode == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1583
+
+ @assert {
+
+ Q == 1
+ cmode == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1584
+
+ @assert {
+
+ Q == 1
+ cmode == 11
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1585
+
+ @assert {
+
+ Q == 1
+ cmode == 100
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1586
+
+ @assert {
+
+ Q == 1
+ cmode == 101
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1587
+
+ @assert {
+
+ Q == 1
+ cmode == 110
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1588
+
+ @assert {
+
+ Q == 1
+ cmode == 111
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1589
+
+ @assert {
+
+ Q == 1
+ cmode == 1100
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1590
+
+ @assert {
+
+ Q == 1
+ cmode == 1101
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1591
+
+ @assert {
+
+ Q == 0
+ cmode == 1000
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i16 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1592
+
+ @assert {
+
+ Q == 0
+ cmode == 1001
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i16 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1593
+
+ @assert {
+
+ Q == 0
+ cmode == 1010
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i16 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1594
+
+ @assert {
+
+ Q == 0
+ cmode == 1011
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i16 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1595
+
+ @assert {
+
+ Q == 0
+ cmode == 0
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1596
+
+ @assert {
+
+ Q == 0
+ cmode == 1
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1597
+
+ @assert {
+
+ Q == 0
+ cmode == 10
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1598
+
+ @assert {
+
+ Q == 0
+ cmode == 11
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1599
+
+ @assert {
+
+ Q == 0
+ cmode == 100
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1600
+
+ @assert {
+
+ Q == 0
+ cmode == 101
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1601
+
+ @assert {
+
+ Q == 0
+ cmode == 110
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1602
+
+ @assert {
+
+ Q == 0
+ cmode == 111
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1603
+
+ @assert {
+
+ Q == 0
+ cmode == 1100
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1604
+
+ @assert {
+
+ Q == 0
+ cmode == 1101
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 dwvec_D imm64
+
+ }
+
+}
+
+@encoding (A1) {
+
+ @word 1 1 1 i(1) 1 1 1 1 1 D(1) 0 0 0 imm3(3) Vd(4) cmode(4) 0 Q(1) 1 1 imm4(4)
+
+ @syntax {
+
+ @subid 1605
+
+ @assert {
+
+ Q == 1
+ cmode == 1000
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i16 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1606
+
+ @assert {
+
+ Q == 1
+ cmode == 1001
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i16 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1607
+
+ @assert {
+
+ Q == 1
+ cmode == 1010
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i16 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1608
+
+ @assert {
+
+ Q == 1
+ cmode == 1011
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i16 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1609
+
+ @assert {
+
+ Q == 1
+ cmode == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1610
+
+ @assert {
+
+ Q == 1
+ cmode == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1611
+
+ @assert {
+
+ Q == 1
+ cmode == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1612
+
+ @assert {
+
+ Q == 1
+ cmode == 11
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1613
+
+ @assert {
+
+ Q == 1
+ cmode == 100
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1614
+
+ @assert {
+
+ Q == 1
+ cmode == 101
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1615
+
+ @assert {
+
+ Q == 1
+ cmode == 110
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1616
+
+ @assert {
+
+ Q == 1
+ cmode == 111
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1617
+
+ @assert {
+
+ Q == 1
+ cmode == 1100
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1618
+
+ @assert {
+
+ Q == 1
+ cmode == 1101
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 qwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1619
+
+ @assert {
+
+ Q == 0
+ cmode == 1000
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i16 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1620
+
+ @assert {
+
+ Q == 0
+ cmode == 1001
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i16 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1621
+
+ @assert {
+
+ Q == 0
+ cmode == 1010
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i16 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1622
+
+ @assert {
+
+ Q == 0
+ cmode == 1011
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i16 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1623
+
+ @assert {
+
+ Q == 0
+ cmode == 0
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1624
+
+ @assert {
+
+ Q == 0
+ cmode == 1
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1625
+
+ @assert {
+
+ Q == 0
+ cmode == 10
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1626
+
+ @assert {
+
+ Q == 0
+ cmode == 11
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1627
+
+ @assert {
+
+ Q == 0
+ cmode == 100
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1628
+
+ @assert {
+
+ Q == 0
+ cmode == 101
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1629
+
+ @assert {
+
+ Q == 0
+ cmode == 110
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1630
+
+ @assert {
+
+ Q == 0
+ cmode == 111
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1631
+
+ @assert {
+
+ Q == 0
+ cmode == 1100
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 dwvec_D imm64
+
+ }
+
+ @syntax {
+
+ @subid 1632
+
+ @assert {
+
+ Q == 0
+ cmode == 1101
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4)
+
+ }
+
+ @asm vmvn.i32 dwvec_D imm64
+
+ }
+
+}
+
diff --git a/plugins/arm/v7/opdefs/A88354_vmvn.d b/plugins/arm/v7/opdefs/A88354_vmvn.d
index 6e91a3d..30c4391 100644
--- a/plugins/arm/v7/opdefs/A88354_vmvn.d
+++ b/plugins/arm/v7/opdefs/A88354_vmvn.d
@@ -23,7 +23,7 @@
@title VMVN (register)
-@id 314
+@id 326
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1431
+ @subid 1633
@conv {
@@ -58,7 +58,7 @@
@syntax {
- @subid 1432
+ @subid 1634
@conv {
diff --git a/plugins/arm/v7/opdefs/A88355_vneg.d b/plugins/arm/v7/opdefs/A88355_vneg.d
index e7ad0fb..fca1b13 100644
--- a/plugins/arm/v7/opdefs/A88355_vneg.d
+++ b/plugins/arm/v7/opdefs/A88355_vneg.d
@@ -23,7 +23,7 @@
@title VNEG
-@id 315
+@id 327
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1433
+ @subid 1635
@assert {
@@ -59,7 +59,7 @@
@syntax {
- @subid 1434
+ @subid 1636
@assert {
@@ -81,7 +81,7 @@
@syntax {
- @subid 1435
+ @subid 1637
@assert {
@@ -103,7 +103,7 @@
@syntax {
- @subid 1436
+ @subid 1638
@assert {
@@ -131,7 +131,7 @@
@syntax {
- @subid 1437
+ @subid 1639
@assert {
@@ -152,7 +152,7 @@
@syntax {
- @subid 1438
+ @subid 1640
@assert {
@@ -179,7 +179,7 @@
@syntax {
- @subid 1439
+ @subid 1641
@assert {
@@ -201,7 +201,7 @@
@syntax {
- @subid 1440
+ @subid 1642
@assert {
@@ -223,7 +223,7 @@
@syntax {
- @subid 1441
+ @subid 1643
@assert {
@@ -245,7 +245,7 @@
@syntax {
- @subid 1442
+ @subid 1644
@assert {
@@ -273,7 +273,7 @@
@syntax {
- @subid 1443
+ @subid 1645
@assert {
@@ -294,7 +294,7 @@
@syntax {
- @subid 1444
+ @subid 1646
@assert {
diff --git a/plugins/arm/v7/opdefs/A88356_vnm.d b/plugins/arm/v7/opdefs/A88356_vnm.d
index 488d721..5538125 100644
--- a/plugins/arm/v7/opdefs/A88356_vnm.d
+++ b/plugins/arm/v7/opdefs/A88356_vnm.d
@@ -23,7 +23,7 @@
@title VNMLA, VNMLS, VNMUL
-@id 316
+@id 328
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1445
+ @subid 1647
@assert {
@@ -60,7 +60,7 @@
@syntax {
- @subid 1446
+ @subid 1648
@assert {
@@ -83,7 +83,7 @@
@syntax {
- @subid 1447
+ @subid 1649
@assert {
@@ -106,7 +106,7 @@
@syntax {
- @subid 1448
+ @subid 1650
@assert {
@@ -135,7 +135,7 @@
@syntax {
- @subid 1449
+ @subid 1651
@assert {
@@ -157,7 +157,7 @@
@syntax {
- @subid 1450
+ @subid 1652
@assert {
@@ -185,7 +185,7 @@
@syntax {
- @subid 1451
+ @subid 1653
@assert {
@@ -208,7 +208,7 @@
@syntax {
- @subid 1452
+ @subid 1654
@assert {
@@ -231,7 +231,7 @@
@syntax {
- @subid 1453
+ @subid 1655
@assert {
@@ -254,7 +254,7 @@
@syntax {
- @subid 1454
+ @subid 1656
@assert {
@@ -283,7 +283,7 @@
@syntax {
- @subid 1455
+ @subid 1657
@assert {
@@ -305,7 +305,7 @@
@syntax {
- @subid 1456
+ @subid 1658
@assert {
diff --git a/plugins/arm/v7/opdefs/A88358_vorn.d b/plugins/arm/v7/opdefs/A88358_vorn.d
index d271d9e..66f68d4 100644
--- a/plugins/arm/v7/opdefs/A88358_vorn.d
+++ b/plugins/arm/v7/opdefs/A88358_vorn.d
@@ -23,7 +23,7 @@
@title VORN (register)
-@id 318
+@id 330
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1457
+ @subid 1659
@assert {
@@ -59,7 +59,7 @@
@syntax {
- @subid 1458
+ @subid 1660
@assert {
@@ -87,7 +87,7 @@
@syntax {
- @subid 1459
+ @subid 1661
@assert {
@@ -109,7 +109,7 @@
@syntax {
- @subid 1460
+ @subid 1662
@assert {
diff --git a/plugins/arm/v7/opdefs/A88359_vorr.d b/plugins/arm/v7/opdefs/A88359_vorr.d
index 5d29c8e..989e4e4 100644
--- a/plugins/arm/v7/opdefs/A88359_vorr.d
+++ b/plugins/arm/v7/opdefs/A88359_vorr.d
@@ -23,7 +23,7 @@
@title VORR (immediate)
-@id 319
+@id 331
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1461
+ @subid 1663
@assert {
@@ -59,7 +59,7 @@
@syntax {
- @subid 1462
+ @subid 1664
@assert {
@@ -81,7 +81,7 @@
@syntax {
- @subid 1463
+ @subid 1665
@assert {
@@ -103,7 +103,7 @@
@syntax {
- @subid 1464
+ @subid 1666
@assert {
@@ -125,7 +125,7 @@
@syntax {
- @subid 1465
+ @subid 1667
@assert {
@@ -147,7 +147,7 @@
@syntax {
- @subid 1466
+ @subid 1668
@assert {
@@ -169,7 +169,7 @@
@syntax {
- @subid 1467
+ @subid 1669
@assert {
@@ -191,7 +191,7 @@
@syntax {
- @subid 1468
+ @subid 1670
@assert {
@@ -213,7 +213,7 @@
@syntax {
- @subid 1469
+ @subid 1671
@assert {
@@ -235,7 +235,7 @@
@syntax {
- @subid 1470
+ @subid 1672
@assert {
@@ -257,7 +257,7 @@
@syntax {
- @subid 1471
+ @subid 1673
@assert {
@@ -279,7 +279,7 @@
@syntax {
- @subid 1472
+ @subid 1674
@assert {
@@ -301,7 +301,7 @@
@syntax {
- @subid 1473
+ @subid 1675
@assert {
@@ -323,7 +323,7 @@
@syntax {
- @subid 1474
+ @subid 1676
@assert {
@@ -345,7 +345,7 @@
@syntax {
- @subid 1475
+ @subid 1677
@assert {
@@ -367,7 +367,7 @@
@syntax {
- @subid 1476
+ @subid 1678
@assert {
@@ -389,7 +389,7 @@
@syntax {
- @subid 1477
+ @subid 1679
@assert {
@@ -411,7 +411,7 @@
@syntax {
- @subid 1478
+ @subid 1680
@assert {
@@ -433,7 +433,7 @@
@syntax {
- @subid 1479
+ @subid 1681
@assert {
@@ -455,7 +455,7 @@
@syntax {
- @subid 1480
+ @subid 1682
@assert {
@@ -477,7 +477,7 @@
@syntax {
- @subid 1481
+ @subid 1683
@assert {
@@ -499,7 +499,7 @@
@syntax {
- @subid 1482
+ @subid 1684
@assert {
@@ -521,7 +521,7 @@
@syntax {
- @subid 1483
+ @subid 1685
@assert {
@@ -543,7 +543,7 @@
@syntax {
- @subid 1484
+ @subid 1686
@assert {
@@ -565,7 +565,7 @@
@syntax {
- @subid 1485
+ @subid 1687
@assert {
@@ -587,7 +587,7 @@
@syntax {
- @subid 1486
+ @subid 1688
@assert {
@@ -609,7 +609,7 @@
@syntax {
- @subid 1487
+ @subid 1689
@assert {
@@ -631,7 +631,7 @@
@syntax {
- @subid 1488
+ @subid 1690
@assert {
@@ -659,7 +659,7 @@
@syntax {
- @subid 1489
+ @subid 1691
@assert {
@@ -681,7 +681,7 @@
@syntax {
- @subid 1490
+ @subid 1692
@assert {
@@ -703,7 +703,7 @@
@syntax {
- @subid 1491
+ @subid 1693
@assert {
@@ -725,7 +725,7 @@
@syntax {
- @subid 1492
+ @subid 1694
@assert {
@@ -747,7 +747,7 @@
@syntax {
- @subid 1493
+ @subid 1695
@assert {
@@ -769,7 +769,7 @@
@syntax {
- @subid 1494
+ @subid 1696
@assert {
@@ -791,7 +791,7 @@
@syntax {
- @subid 1495
+ @subid 1697
@assert {
@@ -813,7 +813,7 @@
@syntax {
- @subid 1496
+ @subid 1698
@assert {
@@ -835,7 +835,7 @@
@syntax {
- @subid 1497
+ @subid 1699
@assert {
@@ -857,7 +857,7 @@
@syntax {
- @subid 1498
+ @subid 1700
@assert {
@@ -879,7 +879,7 @@
@syntax {
- @subid 1499
+ @subid 1701
@assert {
@@ -901,7 +901,7 @@
@syntax {
- @subid 1500
+ @subid 1702
@assert {
@@ -923,7 +923,7 @@
@syntax {
- @subid 1501
+ @subid 1703
@assert {
@@ -945,7 +945,7 @@
@syntax {
- @subid 1502
+ @subid 1704
@assert {
@@ -967,7 +967,7 @@
@syntax {
- @subid 1503
+ @subid 1705
@assert {
@@ -989,7 +989,7 @@
@syntax {
- @subid 1504
+ @subid 1706
@assert {
@@ -1011,7 +1011,7 @@
@syntax {
- @subid 1505
+ @subid 1707
@assert {
@@ -1033,7 +1033,7 @@
@syntax {
- @subid 1506
+ @subid 1708
@assert {
@@ -1055,7 +1055,7 @@
@syntax {
- @subid 1507
+ @subid 1709
@assert {
@@ -1077,7 +1077,7 @@
@syntax {
- @subid 1508
+ @subid 1710
@assert {
@@ -1099,7 +1099,7 @@
@syntax {
- @subid 1509
+ @subid 1711
@assert {
@@ -1121,7 +1121,7 @@
@syntax {
- @subid 1510
+ @subid 1712
@assert {
@@ -1143,7 +1143,7 @@
@syntax {
- @subid 1511
+ @subid 1713
@assert {
@@ -1165,7 +1165,7 @@
@syntax {
- @subid 1512
+ @subid 1714
@assert {
@@ -1187,7 +1187,7 @@
@syntax {
- @subid 1513
+ @subid 1715
@assert {
@@ -1209,7 +1209,7 @@
@syntax {
- @subid 1514
+ @subid 1716
@assert {
@@ -1231,7 +1231,7 @@
@syntax {
- @subid 1515
+ @subid 1717
@assert {
@@ -1253,7 +1253,7 @@
@syntax {
- @subid 1516
+ @subid 1718
@assert {
diff --git a/plugins/arm/v7/opdefs/A88360_vorr.d b/plugins/arm/v7/opdefs/A88360_vorr.d
index 30bb5ce..6878274 100644
--- a/plugins/arm/v7/opdefs/A88360_vorr.d
+++ b/plugins/arm/v7/opdefs/A88360_vorr.d
@@ -23,7 +23,7 @@
@title VORR (register)
-@id 320
+@id 332
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1517
+ @subid 1719
@assert {
@@ -59,7 +59,7 @@
@syntax {
- @subid 1518
+ @subid 1720
@assert {
@@ -87,7 +87,7 @@
@syntax {
- @subid 1519
+ @subid 1721
@assert {
@@ -109,7 +109,7 @@
@syntax {
- @subid 1520
+ @subid 1722
@assert {
diff --git a/plugins/arm/v7/opdefs/A88361_vpadal.d b/plugins/arm/v7/opdefs/A88361_vpadal.d
index 71c699b..6c5aeac 100644
--- a/plugins/arm/v7/opdefs/A88361_vpadal.d
+++ b/plugins/arm/v7/opdefs/A88361_vpadal.d
@@ -23,7 +23,7 @@
@title VPADAL
-@id 321
+@id 333
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1521
+ @subid 1723
@assert {
@@ -60,7 +60,7 @@
@syntax {
- @subid 1522
+ @subid 1724
@assert {
@@ -83,7 +83,7 @@
@syntax {
- @subid 1523
+ @subid 1725
@assert {
@@ -106,7 +106,7 @@
@syntax {
- @subid 1524
+ @subid 1726
@assert {
@@ -129,7 +129,7 @@
@syntax {
- @subid 1525
+ @subid 1727
@assert {
@@ -152,7 +152,7 @@
@syntax {
- @subid 1526
+ @subid 1728
@assert {
@@ -175,7 +175,7 @@
@syntax {
- @subid 1527
+ @subid 1729
@assert {
@@ -198,7 +198,7 @@
@syntax {
- @subid 1528
+ @subid 1730
@assert {
@@ -221,7 +221,7 @@
@syntax {
- @subid 1529
+ @subid 1731
@assert {
@@ -244,7 +244,7 @@
@syntax {
- @subid 1530
+ @subid 1732
@assert {
@@ -267,7 +267,7 @@
@syntax {
- @subid 1531
+ @subid 1733
@assert {
@@ -290,7 +290,7 @@
@syntax {
- @subid 1532
+ @subid 1734
@assert {
@@ -319,7 +319,7 @@
@syntax {
- @subid 1533
+ @subid 1735
@assert {
@@ -342,7 +342,7 @@
@syntax {
- @subid 1534
+ @subid 1736
@assert {
@@ -365,7 +365,7 @@
@syntax {
- @subid 1535
+ @subid 1737
@assert {
@@ -388,7 +388,7 @@
@syntax {
- @subid 1536
+ @subid 1738
@assert {
@@ -411,7 +411,7 @@
@syntax {
- @subid 1537
+ @subid 1739
@assert {
@@ -434,7 +434,7 @@
@syntax {
- @subid 1538
+ @subid 1740
@assert {
@@ -457,7 +457,7 @@
@syntax {
- @subid 1539
+ @subid 1741
@assert {
@@ -480,7 +480,7 @@
@syntax {
- @subid 1540
+ @subid 1742
@assert {
@@ -503,7 +503,7 @@
@syntax {
- @subid 1541
+ @subid 1743
@assert {
@@ -526,7 +526,7 @@
@syntax {
- @subid 1542
+ @subid 1744
@assert {
@@ -549,7 +549,7 @@
@syntax {
- @subid 1543
+ @subid 1745
@assert {
@@ -572,7 +572,7 @@
@syntax {
- @subid 1544
+ @subid 1746
@assert {
diff --git a/plugins/arm/v7/opdefs/A88362_vpadd.d b/plugins/arm/v7/opdefs/A88362_vpadd.d
index 3f44021..53b56f9 100644
--- a/plugins/arm/v7/opdefs/A88362_vpadd.d
+++ b/plugins/arm/v7/opdefs/A88362_vpadd.d
@@ -23,7 +23,7 @@
@title VPADD (integer)
-@id 322
+@id 334
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1545
+ @subid 1747
@assert {
@@ -60,7 +60,7 @@
@syntax {
- @subid 1546
+ @subid 1748
@assert {
@@ -83,7 +83,7 @@
@syntax {
- @subid 1547
+ @subid 1749
@assert {
@@ -112,7 +112,7 @@
@syntax {
- @subid 1548
+ @subid 1750
@assert {
@@ -135,7 +135,7 @@
@syntax {
- @subid 1549
+ @subid 1751
@assert {
@@ -158,7 +158,7 @@
@syntax {
- @subid 1550
+ @subid 1752
@assert {
diff --git a/plugins/arm/v7/opdefs/A88363_vpadd.d b/plugins/arm/v7/opdefs/A88363_vpadd.d
index 08c9715..8149449 100644
--- a/plugins/arm/v7/opdefs/A88363_vpadd.d
+++ b/plugins/arm/v7/opdefs/A88363_vpadd.d
@@ -23,7 +23,7 @@
@title VPADD (floating-point)
-@id 323
+@id 335
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1551
+ @subid 1753
@assert {
@@ -66,7 +66,7 @@
@syntax {
- @subid 1552
+ @subid 1754
@assert {
diff --git a/plugins/arm/v7/opdefs/A88364_vpaddl.d b/plugins/arm/v7/opdefs/A88364_vpaddl.d
index 3d6b873..68e83c9 100644
--- a/plugins/arm/v7/opdefs/A88364_vpaddl.d
+++ b/plugins/arm/v7/opdefs/A88364_vpaddl.d
@@ -23,7 +23,7 @@
@title VPADDL
-@id 324
+@id 336
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1553
+ @subid 1755
@assert {
@@ -60,7 +60,7 @@
@syntax {
- @subid 1554
+ @subid 1756
@assert {
@@ -83,7 +83,7 @@
@syntax {
- @subid 1555
+ @subid 1757
@assert {
@@ -106,7 +106,7 @@
@syntax {
- @subid 1556
+ @subid 1758
@assert {
@@ -129,7 +129,7 @@
@syntax {
- @subid 1557
+ @subid 1759
@assert {
@@ -152,7 +152,7 @@
@syntax {
- @subid 1558
+ @subid 1760
@assert {
@@ -175,7 +175,7 @@
@syntax {
- @subid 1559
+ @subid 1761
@assert {
@@ -198,7 +198,7 @@
@syntax {
- @subid 1560
+ @subid 1762
@assert {
@@ -221,7 +221,7 @@
@syntax {
- @subid 1561
+ @subid 1763
@assert {
@@ -244,7 +244,7 @@
@syntax {
- @subid 1562
+ @subid 1764
@assert {
@@ -267,7 +267,7 @@
@syntax {
- @subid 1563
+ @subid 1765
@assert {
@@ -290,7 +290,7 @@
@syntax {
- @subid 1564
+ @subid 1766
@assert {
@@ -319,7 +319,7 @@
@syntax {
- @subid 1565
+ @subid 1767
@assert {
@@ -342,7 +342,7 @@
@syntax {
- @subid 1566
+ @subid 1768
@assert {
@@ -365,7 +365,7 @@
@syntax {
- @subid 1567
+ @subid 1769
@assert {
@@ -388,7 +388,7 @@
@syntax {
- @subid 1568
+ @subid 1770
@assert {
@@ -411,7 +411,7 @@
@syntax {
- @subid 1569
+ @subid 1771
@assert {
@@ -434,7 +434,7 @@
@syntax {
- @subid 1570
+ @subid 1772
@assert {
@@ -457,7 +457,7 @@
@syntax {
- @subid 1571
+ @subid 1773
@assert {
@@ -480,7 +480,7 @@
@syntax {
- @subid 1572
+ @subid 1774
@assert {
@@ -503,7 +503,7 @@
@syntax {
- @subid 1573
+ @subid 1775
@assert {
@@ -526,7 +526,7 @@
@syntax {
- @subid 1574
+ @subid 1776
@assert {
@@ -549,7 +549,7 @@
@syntax {
- @subid 1575
+ @subid 1777
@assert {
@@ -572,7 +572,7 @@
@syntax {
- @subid 1576
+ @subid 1778
@assert {
diff --git a/plugins/arm/v7/opdefs/A88365_vpmax.d b/plugins/arm/v7/opdefs/A88365_vpmax.d
index 66731cb..e36d35b 100644
--- a/plugins/arm/v7/opdefs/A88365_vpmax.d
+++ b/plugins/arm/v7/opdefs/A88365_vpmax.d
@@ -23,7 +23,7 @@
@title VPMAX, VPMIN (integer)
-@id 325
+@id 337
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1577
+ @subid 1779
@assert {
@@ -62,7 +62,7 @@
@syntax {
- @subid 1578
+ @subid 1780
@assert {
@@ -87,7 +87,7 @@
@syntax {
- @subid 1579
+ @subid 1781
@assert {
@@ -112,7 +112,7 @@
@syntax {
- @subid 1580
+ @subid 1782
@assert {
@@ -137,7 +137,7 @@
@syntax {
- @subid 1581
+ @subid 1783
@assert {
@@ -162,7 +162,7 @@
@syntax {
- @subid 1582
+ @subid 1784
@assert {
@@ -187,7 +187,7 @@
@syntax {
- @subid 1583
+ @subid 1785
@assert {
@@ -212,7 +212,7 @@
@syntax {
- @subid 1584
+ @subid 1786
@assert {
@@ -237,7 +237,7 @@
@syntax {
- @subid 1585
+ @subid 1787
@assert {
@@ -262,7 +262,7 @@
@syntax {
- @subid 1586
+ @subid 1788
@assert {
@@ -287,7 +287,7 @@
@syntax {
- @subid 1587
+ @subid 1789
@assert {
@@ -312,7 +312,7 @@
@syntax {
- @subid 1588
+ @subid 1790
@assert {
@@ -343,7 +343,7 @@
@syntax {
- @subid 1589
+ @subid 1791
@assert {
@@ -368,7 +368,7 @@
@syntax {
- @subid 1590
+ @subid 1792
@assert {
@@ -393,7 +393,7 @@
@syntax {
- @subid 1591
+ @subid 1793
@assert {
@@ -418,7 +418,7 @@
@syntax {
- @subid 1592
+ @subid 1794
@assert {
@@ -443,7 +443,7 @@
@syntax {
- @subid 1593
+ @subid 1795
@assert {
@@ -468,7 +468,7 @@
@syntax {
- @subid 1594
+ @subid 1796
@assert {
@@ -493,7 +493,7 @@
@syntax {
- @subid 1595
+ @subid 1797
@assert {
@@ -518,7 +518,7 @@
@syntax {
- @subid 1596
+ @subid 1798
@assert {
@@ -543,7 +543,7 @@
@syntax {
- @subid 1597
+ @subid 1799
@assert {
@@ -568,7 +568,7 @@
@syntax {
- @subid 1598
+ @subid 1800
@assert {
@@ -593,7 +593,7 @@
@syntax {
- @subid 1599
+ @subid 1801
@assert {
@@ -618,7 +618,7 @@
@syntax {
- @subid 1600
+ @subid 1802
@assert {
diff --git a/plugins/arm/v7/opdefs/A88366_vpmax.d b/plugins/arm/v7/opdefs/A88366_vpmax.d
index badd9d8..d927f44 100644
--- a/plugins/arm/v7/opdefs/A88366_vpmax.d
+++ b/plugins/arm/v7/opdefs/A88366_vpmax.d
@@ -23,7 +23,7 @@
@title VPMAX, VPMIN (floating-point)
-@id 326
+@id 338
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1601
+ @subid 1803
@assert {
@@ -61,7 +61,7 @@
@syntax {
- @subid 1602
+ @subid 1804
@assert {
@@ -91,7 +91,7 @@
@syntax {
- @subid 1603
+ @subid 1805
@assert {
@@ -115,7 +115,7 @@
@syntax {
- @subid 1604
+ @subid 1806
@assert {
diff --git a/plugins/arm/v7/opdefs/A88369_vqabs.d b/plugins/arm/v7/opdefs/A88369_vqabs.d
index 98020e1..de4af39 100644
--- a/plugins/arm/v7/opdefs/A88369_vqabs.d
+++ b/plugins/arm/v7/opdefs/A88369_vqabs.d
@@ -23,7 +23,7 @@
@title VQABS
-@id 327
+@id 339
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1605
+ @subid 1807
@assert {
@@ -59,7 +59,7 @@
@syntax {
- @subid 1606
+ @subid 1808
@assert {
@@ -81,7 +81,7 @@
@syntax {
- @subid 1607
+ @subid 1809
@assert {
@@ -103,7 +103,7 @@
@syntax {
- @subid 1608
+ @subid 1810
@assert {
@@ -125,7 +125,7 @@
@syntax {
- @subid 1609
+ @subid 1811
@assert {
@@ -147,7 +147,7 @@
@syntax {
- @subid 1610
+ @subid 1812
@assert {
@@ -175,7 +175,7 @@
@syntax {
- @subid 1611
+ @subid 1813
@assert {
@@ -197,7 +197,7 @@
@syntax {
- @subid 1612
+ @subid 1814
@assert {
@@ -219,7 +219,7 @@
@syntax {
- @subid 1613
+ @subid 1815
@assert {
@@ -241,7 +241,7 @@
@syntax {
- @subid 1614
+ @subid 1816
@assert {
@@ -263,7 +263,7 @@
@syntax {
- @subid 1615
+ @subid 1817
@assert {
@@ -285,7 +285,7 @@
@syntax {
- @subid 1616
+ @subid 1818
@assert {
diff --git a/plugins/arm/v7/opdefs/A88370_vqadd.d b/plugins/arm/v7/opdefs/A88370_vqadd.d
new file mode 100644
index 0000000..d5cf213
--- /dev/null
+++ b/plugins/arm/v7/opdefs/A88370_vqadd.d
@@ -0,0 +1,813 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2017 Cyrille Bagard
+ *
+ * This file is part of Chrysalide.
+ *
+ * Chrysalide is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * Chrysalide is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title VQADD
+
+@id 340
+
+@desc {
+
+ Vector Saturating Add adds the values of corresponding elements of two vectors, and places the results in the destination vector. If any of the results overflow, they are saturated. The cumulative saturation bit, FPSCR.QC, is set if saturation occurs. For details see Pseudocode details of saturation on page A2-44. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of access controls for Advanced SIMD functionality on page B1-1232 summarizes these controls. ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available as a VFP instruction encoding, see Conditional execution on page A8-288.
+
+}
+
+@encoding (T1) {
+
+ @word 1 1 1 U(1) 1 1 1 1 0 D(1) size(2) Vn(4) Vd(4) 0 0 0 0 N(1) Q(1) M(1) 1 Vm(4)
+
+ @syntax {
+
+ @subid 1819
+
+ @assert {
+
+ Q == 1
+ U == 0
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vqadd.s8 ?qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1820
+
+ @assert {
+
+ Q == 1
+ U == 0
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vqadd.s16 ?qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1821
+
+ @assert {
+
+ Q == 1
+ U == 0
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vqadd.s32 ?qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1822
+
+ @assert {
+
+ Q == 1
+ U == 0
+ size == 11
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vqadd.s64 ?qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1823
+
+ @assert {
+
+ Q == 1
+ U == 1
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vqadd.u8 ?qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1824
+
+ @assert {
+
+ Q == 1
+ U == 1
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vqadd.u16 ?qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1825
+
+ @assert {
+
+ Q == 1
+ U == 1
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vqadd.u32 ?qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1826
+
+ @assert {
+
+ Q == 1
+ U == 1
+ size == 11
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vqadd.u64 ?qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1827
+
+ @assert {
+
+ Q == 0
+ U == 0
+ size == 0
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vqadd.s8 ?dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1828
+
+ @assert {
+
+ Q == 0
+ U == 0
+ size == 1
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vqadd.s16 ?dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1829
+
+ @assert {
+
+ Q == 0
+ U == 0
+ size == 10
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vqadd.s32 ?dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1830
+
+ @assert {
+
+ Q == 0
+ U == 0
+ size == 11
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vqadd.s64 ?dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1831
+
+ @assert {
+
+ Q == 0
+ U == 1
+ size == 0
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vqadd.u8 ?dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1832
+
+ @assert {
+
+ Q == 0
+ U == 1
+ size == 1
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vqadd.u16 ?dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1833
+
+ @assert {
+
+ Q == 0
+ U == 1
+ size == 10
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vqadd.u32 ?dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1834
+
+ @assert {
+
+ Q == 0
+ U == 1
+ size == 11
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vqadd.u64 ?dwvec_D dwvec_N dwvec_M
+
+ }
+
+}
+
+@encoding (A1) {
+
+ @word 1 1 1 U(1) 1 1 1 1 0 D(1) size(2) Vn(4) Vd(4) 0 0 0 0 N(1) Q(1) M(1) 1 Vm(4)
+
+ @syntax {
+
+ @subid 1835
+
+ @assert {
+
+ Q == 1
+ U == 0
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vqadd.s8 ?qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1836
+
+ @assert {
+
+ Q == 1
+ U == 0
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vqadd.s16 ?qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1837
+
+ @assert {
+
+ Q == 1
+ U == 0
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vqadd.s32 ?qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1838
+
+ @assert {
+
+ Q == 1
+ U == 0
+ size == 11
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vqadd.s64 ?qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1839
+
+ @assert {
+
+ Q == 1
+ U == 1
+ size == 0
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vqadd.u8 ?qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1840
+
+ @assert {
+
+ Q == 1
+ U == 1
+ size == 1
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vqadd.u16 ?qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1841
+
+ @assert {
+
+ Q == 1
+ U == 1
+ size == 10
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vqadd.u32 ?qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1842
+
+ @assert {
+
+ Q == 1
+ U == 1
+ size == 11
+
+ }
+
+ @conv {
+
+ qwvec_D = QuadWordVector(D:Vd)
+ qwvec_N = QuadWordVector(N:Vn)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vqadd.u64 ?qwvec_D qwvec_N qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1843
+
+ @assert {
+
+ Q == 0
+ U == 0
+ size == 0
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vqadd.s8 ?dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1844
+
+ @assert {
+
+ Q == 0
+ U == 0
+ size == 1
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vqadd.s16 ?dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1845
+
+ @assert {
+
+ Q == 0
+ U == 0
+ size == 10
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vqadd.s32 ?dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1846
+
+ @assert {
+
+ Q == 0
+ U == 0
+ size == 11
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vqadd.s64 ?dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1847
+
+ @assert {
+
+ Q == 0
+ U == 1
+ size == 0
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vqadd.u8 ?dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1848
+
+ @assert {
+
+ Q == 0
+ U == 1
+ size == 1
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vqadd.u16 ?dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1849
+
+ @assert {
+
+ Q == 0
+ U == 1
+ size == 10
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vqadd.u32 ?dwvec_D dwvec_N dwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1850
+
+ @assert {
+
+ Q == 0
+ U == 1
+ size == 11
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ dwvec_N = DoubleWordVector(N:Vn)
+ dwvec_M = DoubleWordVector(M:Vm)
+
+ }
+
+ @asm vqadd.u64 ?dwvec_D dwvec_N dwvec_M
+
+ }
+
+}
+
diff --git a/plugins/arm/v7/opdefs/A88374_vqmov.d b/plugins/arm/v7/opdefs/A88374_vqmov.d
new file mode 100644
index 0000000..32a2dd0
--- /dev/null
+++ b/plugins/arm/v7/opdefs/A88374_vqmov.d
@@ -0,0 +1,441 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2017 Cyrille Bagard
+ *
+ * This file is part of Chrysalide.
+ *
+ * Chrysalide is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * Chrysalide is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title VQMOVN, VQMOVUN
+
+@id 341
+
+@desc {
+
+ Vector Saturating Move and Narrow copies each element of the operand vector to the corresponding element of the destination vector. The operand is a quadword vector. The elements can be any one of: • 16-bit, 32-bit, or 64-bit signed integers • 16-bit, 32-bit, or 64-bit unsigned integers. The result is a doubleword vector. The elements are half the length of the operand vector elements. If the operand is unsigned, the results are unsigned. If the operand is signed, the results can be signed or unsigned. If any of the results overflow, they are saturated. The cumulative saturation bit, FPSCR.QC, is set if saturation occurs. For details see Pseudocode details of saturation on page A2-44. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of access controls for Advanced SIMD functionality on page B1-1232 summarizes these controls. ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available as a VFP instruction encoding, see Conditional execution on page A8-288.
+
+}
+
+@encoding (T1) {
+
+ @word 1 1 1 1 1 1 1 1 1 D(1) 1 1 size(2) 1 0 Vd(4) 0 0 1 0 op(2) M(1) 0 Vm(4)
+
+ @syntax {
+
+ @subid 1851
+
+ @assert {
+
+ op == 1
+ size == 0
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vqmovun.s16 dwvec_D qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1852
+
+ @assert {
+
+ op == 1
+ size == 1
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vqmovun.s32 dwvec_D qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1853
+
+ @assert {
+
+ op == 1
+ size == 10
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vqmovun.s64 dwvec_D qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1854
+
+ @assert {
+
+ op == 10
+ size == 0
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vqmovn.s16 dwvec_D qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1855
+
+ @assert {
+
+ op == 10
+ size == 1
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vqmovn.s32 dwvec_D qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1856
+
+ @assert {
+
+ op == 10
+ size == 10
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vqmovn.s64 dwvec_D qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1857
+
+ @assert {
+
+ op == 11
+ size == 0
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vqmovn.u16 dwvec_D qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1858
+
+ @assert {
+
+ op == 11
+ size == 1
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vqmovn.u32 dwvec_D qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1859
+
+ @assert {
+
+ op == 11
+ size == 10
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vqmovn.u64 dwvec_D qwvec_M
+
+ }
+
+}
+
+@encoding (A1) {
+
+ @word 1 1 1 1 1 1 1 1 1 D(1) 1 1 size(2) 1 0 Vd(4) 0 0 1 0 op(2) M(1) 0 Vm(4)
+
+ @syntax {
+
+ @subid 1860
+
+ @assert {
+
+ op == 1
+ size == 0
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vqmovun.s16 dwvec_D qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1861
+
+ @assert {
+
+ op == 1
+ size == 1
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vqmovun.s32 dwvec_D qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1862
+
+ @assert {
+
+ op == 1
+ size == 10
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vqmovun.s64 dwvec_D qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1863
+
+ @assert {
+
+ op == 10
+ size == 0
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vqmovn.s16 dwvec_D qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1864
+
+ @assert {
+
+ op == 10
+ size == 1
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vqmovn.s32 dwvec_D qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1865
+
+ @assert {
+
+ op == 10
+ size == 10
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vqmovn.s64 dwvec_D qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1866
+
+ @assert {
+
+ op == 11
+ size == 0
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vqmovn.u16 dwvec_D qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1867
+
+ @assert {
+
+ op == 11
+ size == 1
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vqmovn.u32 dwvec_D qwvec_M
+
+ }
+
+ @syntax {
+
+ @subid 1868
+
+ @assert {
+
+ op == 11
+ size == 10
+
+ }
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ qwvec_M = QuadWordVector(M:Vm)
+
+ }
+
+ @asm vqmovn.u64 dwvec_D qwvec_M
+
+ }
+
+}
+
diff --git a/plugins/arm/v7/opdefs/A88375_vqneg.d b/plugins/arm/v7/opdefs/A88375_vqneg.d
index 8d5a1a0..408c817 100644
--- a/plugins/arm/v7/opdefs/A88375_vqneg.d
+++ b/plugins/arm/v7/opdefs/A88375_vqneg.d
@@ -23,7 +23,7 @@
@title VQNEG
-@id 328
+@id 342
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1617
+ @subid 1869
@assert {
@@ -59,7 +59,7 @@
@syntax {
- @subid 1618
+ @subid 1870
@assert {
@@ -81,7 +81,7 @@
@syntax {
- @subid 1619
+ @subid 1871
@assert {
@@ -103,7 +103,7 @@
@syntax {
- @subid 1620
+ @subid 1872
@assert {
@@ -125,7 +125,7 @@
@syntax {
- @subid 1621
+ @subid 1873
@assert {
@@ -147,7 +147,7 @@
@syntax {
- @subid 1622
+ @subid 1874
@assert {
@@ -175,7 +175,7 @@
@syntax {
- @subid 1623
+ @subid 1875
@assert {
@@ -197,7 +197,7 @@
@syntax {
- @subid 1624
+ @subid 1876
@assert {
@@ -219,7 +219,7 @@
@syntax {
- @subid 1625
+ @subid 1877
@assert {
@@ -241,7 +241,7 @@
@syntax {
- @subid 1626
+ @subid 1878
@assert {
@@ -263,7 +263,7 @@
@syntax {
- @subid 1627
+ @subid 1879
@assert {
@@ -285,7 +285,7 @@
@syntax {
- @subid 1628
+ @subid 1880
@assert {
diff --git a/plugins/arm/v7/opdefs/A88377_vqrshl.d b/plugins/arm/v7/opdefs/A88377_vqrshl.d
index f233245..3b2b83b 100644
--- a/plugins/arm/v7/opdefs/A88377_vqrshl.d
+++ b/plugins/arm/v7/opdefs/A88377_vqrshl.d
@@ -23,7 +23,7 @@
@title VQRSHL
-@id 329
+@id 343
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1629
+ @subid 1881
@assert {
@@ -61,7 +61,7 @@
@syntax {
- @subid 1630
+ @subid 1882
@assert {
@@ -85,7 +85,7 @@
@syntax {
- @subid 1631
+ @subid 1883
@assert {
@@ -109,7 +109,7 @@
@syntax {
- @subid 1632
+ @subid 1884
@assert {
@@ -133,7 +133,7 @@
@syntax {
- @subid 1633
+ @subid 1885
@assert {
@@ -157,7 +157,7 @@
@syntax {
- @subid 1634
+ @subid 1886
@assert {
@@ -181,7 +181,7 @@
@syntax {
- @subid 1635
+ @subid 1887
@assert {
@@ -205,7 +205,7 @@
@syntax {
- @subid 1636
+ @subid 1888
@assert {
@@ -229,7 +229,7 @@
@syntax {
- @subid 1637
+ @subid 1889
@assert {
@@ -253,7 +253,7 @@
@syntax {
- @subid 1638
+ @subid 1890
@assert {
@@ -277,7 +277,7 @@
@syntax {
- @subid 1639
+ @subid 1891
@assert {
@@ -301,7 +301,7 @@
@syntax {
- @subid 1640
+ @subid 1892
@assert {
@@ -325,7 +325,7 @@
@syntax {
- @subid 1641
+ @subid 1893
@assert {
@@ -349,7 +349,7 @@
@syntax {
- @subid 1642
+ @subid 1894
@assert {
@@ -373,7 +373,7 @@
@syntax {
- @subid 1643
+ @subid 1895
@assert {
@@ -397,7 +397,7 @@
@syntax {
- @subid 1644
+ @subid 1896
@assert {
@@ -427,7 +427,7 @@
@syntax {
- @subid 1645
+ @subid 1897
@assert {
@@ -451,7 +451,7 @@
@syntax {
- @subid 1646
+ @subid 1898
@assert {
@@ -475,7 +475,7 @@
@syntax {
- @subid 1647
+ @subid 1899
@assert {
@@ -499,7 +499,7 @@
@syntax {
- @subid 1648
+ @subid 1900
@assert {
@@ -523,7 +523,7 @@
@syntax {
- @subid 1649
+ @subid 1901
@assert {
@@ -547,7 +547,7 @@
@syntax {
- @subid 1650
+ @subid 1902
@assert {
@@ -571,7 +571,7 @@
@syntax {
- @subid 1651
+ @subid 1903
@assert {
@@ -595,7 +595,7 @@
@syntax {
- @subid 1652
+ @subid 1904
@assert {
@@ -619,7 +619,7 @@
@syntax {
- @subid 1653
+ @subid 1905
@assert {
@@ -643,7 +643,7 @@
@syntax {
- @subid 1654
+ @subid 1906
@assert {
@@ -667,7 +667,7 @@
@syntax {
- @subid 1655
+ @subid 1907
@assert {
@@ -691,7 +691,7 @@
@syntax {
- @subid 1656
+ @subid 1908
@assert {
@@ -715,7 +715,7 @@
@syntax {
- @subid 1657
+ @subid 1909
@assert {
@@ -739,7 +739,7 @@
@syntax {
- @subid 1658
+ @subid 1910
@assert {
@@ -763,7 +763,7 @@
@syntax {
- @subid 1659
+ @subid 1911
@assert {
@@ -787,7 +787,7 @@
@syntax {
- @subid 1660
+ @subid 1912
@assert {
diff --git a/plugins/arm/v7/opdefs/A88379_vqshl.d b/plugins/arm/v7/opdefs/A88379_vqshl.d
index acf4203..fee9008 100644
--- a/plugins/arm/v7/opdefs/A88379_vqshl.d
+++ b/plugins/arm/v7/opdefs/A88379_vqshl.d
@@ -23,7 +23,7 @@
@title VQSHL (register)
-@id 330
+@id 344
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1661
+ @subid 1913
@assert {
@@ -61,7 +61,7 @@
@syntax {
- @subid 1662
+ @subid 1914
@assert {
@@ -85,7 +85,7 @@
@syntax {
- @subid 1663
+ @subid 1915
@assert {
@@ -109,7 +109,7 @@
@syntax {
- @subid 1664
+ @subid 1916
@assert {
@@ -133,7 +133,7 @@
@syntax {
- @subid 1665
+ @subid 1917
@assert {
@@ -157,7 +157,7 @@
@syntax {
- @subid 1666
+ @subid 1918
@assert {
@@ -181,7 +181,7 @@
@syntax {
- @subid 1667
+ @subid 1919
@assert {
@@ -205,7 +205,7 @@
@syntax {
- @subid 1668
+ @subid 1920
@assert {
@@ -229,7 +229,7 @@
@syntax {
- @subid 1669
+ @subid 1921
@assert {
@@ -253,7 +253,7 @@
@syntax {
- @subid 1670
+ @subid 1922
@assert {
@@ -277,7 +277,7 @@
@syntax {
- @subid 1671
+ @subid 1923
@assert {
@@ -301,7 +301,7 @@
@syntax {
- @subid 1672
+ @subid 1924
@assert {
@@ -325,7 +325,7 @@
@syntax {
- @subid 1673
+ @subid 1925
@assert {
@@ -349,7 +349,7 @@
@syntax {
- @subid 1674
+ @subid 1926
@assert {
@@ -373,7 +373,7 @@
@syntax {
- @subid 1675
+ @subid 1927
@assert {
@@ -397,7 +397,7 @@
@syntax {
- @subid 1676
+ @subid 1928
@assert {
@@ -427,7 +427,7 @@
@syntax {
- @subid 1677
+ @subid 1929
@assert {
@@ -451,7 +451,7 @@
@syntax {
- @subid 1678
+ @subid 1930
@assert {
@@ -475,7 +475,7 @@
@syntax {
- @subid 1679
+ @subid 1931
@assert {
@@ -499,7 +499,7 @@
@syntax {
- @subid 1680
+ @subid 1932
@assert {
@@ -523,7 +523,7 @@
@syntax {
- @subid 1681
+ @subid 1933
@assert {
@@ -547,7 +547,7 @@
@syntax {
- @subid 1682
+ @subid 1934
@assert {
@@ -571,7 +571,7 @@
@syntax {
- @subid 1683
+ @subid 1935
@assert {
@@ -595,7 +595,7 @@
@syntax {
- @subid 1684
+ @subid 1936
@assert {
@@ -619,7 +619,7 @@
@syntax {
- @subid 1685
+ @subid 1937
@assert {
@@ -643,7 +643,7 @@
@syntax {
- @subid 1686
+ @subid 1938
@assert {
@@ -667,7 +667,7 @@
@syntax {
- @subid 1687
+ @subid 1939
@assert {
@@ -691,7 +691,7 @@
@syntax {
- @subid 1688
+ @subid 1940
@assert {
@@ -715,7 +715,7 @@
@syntax {
- @subid 1689
+ @subid 1941
@assert {
@@ -739,7 +739,7 @@
@syntax {
- @subid 1690
+ @subid 1942
@assert {
@@ -763,7 +763,7 @@
@syntax {
- @subid 1691
+ @subid 1943
@assert {
@@ -787,7 +787,7 @@
@syntax {
- @subid 1692
+ @subid 1944
@assert {
diff --git a/plugins/arm/v7/opdefs/A88382_vqsub.d b/plugins/arm/v7/opdefs/A88382_vqsub.d
index 62e7217..248f826 100644
--- a/plugins/arm/v7/opdefs/A88382_vqsub.d
+++ b/plugins/arm/v7/opdefs/A88382_vqsub.d
@@ -23,7 +23,7 @@
@title VQSUB
-@id 331
+@id 345
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1693
+ @subid 1945
@assert {
@@ -61,7 +61,7 @@
@syntax {
- @subid 1694
+ @subid 1946
@assert {
@@ -85,7 +85,7 @@
@syntax {
- @subid 1695
+ @subid 1947
@assert {
@@ -109,7 +109,7 @@
@syntax {
- @subid 1696
+ @subid 1948
@assert {
@@ -133,7 +133,7 @@
@syntax {
- @subid 1697
+ @subid 1949
@assert {
@@ -157,7 +157,7 @@
@syntax {
- @subid 1698
+ @subid 1950
@assert {
@@ -181,7 +181,7 @@
@syntax {
- @subid 1699
+ @subid 1951
@assert {
@@ -205,7 +205,7 @@
@syntax {
- @subid 1700
+ @subid 1952
@assert {
@@ -229,7 +229,7 @@
@syntax {
- @subid 1701
+ @subid 1953
@assert {
@@ -253,7 +253,7 @@
@syntax {
- @subid 1702
+ @subid 1954
@assert {
@@ -277,7 +277,7 @@
@syntax {
- @subid 1703
+ @subid 1955
@assert {
@@ -301,7 +301,7 @@
@syntax {
- @subid 1704
+ @subid 1956
@assert {
@@ -325,7 +325,7 @@
@syntax {
- @subid 1705
+ @subid 1957
@assert {
@@ -349,7 +349,7 @@
@syntax {
- @subid 1706
+ @subid 1958
@assert {
@@ -373,7 +373,7 @@
@syntax {
- @subid 1707
+ @subid 1959
@assert {
@@ -397,7 +397,7 @@
@syntax {
- @subid 1708
+ @subid 1960
@assert {
@@ -427,7 +427,7 @@
@syntax {
- @subid 1709
+ @subid 1961
@assert {
@@ -451,7 +451,7 @@
@syntax {
- @subid 1710
+ @subid 1962
@assert {
@@ -475,7 +475,7 @@
@syntax {
- @subid 1711
+ @subid 1963
@assert {
@@ -499,7 +499,7 @@
@syntax {
- @subid 1712
+ @subid 1964
@assert {
@@ -523,7 +523,7 @@
@syntax {
- @subid 1713
+ @subid 1965
@assert {
@@ -547,7 +547,7 @@
@syntax {
- @subid 1714
+ @subid 1966
@assert {
@@ -571,7 +571,7 @@
@syntax {
- @subid 1715
+ @subid 1967
@assert {
@@ -595,7 +595,7 @@
@syntax {
- @subid 1716
+ @subid 1968
@assert {
@@ -619,7 +619,7 @@
@syntax {
- @subid 1717
+ @subid 1969
@assert {
@@ -643,7 +643,7 @@
@syntax {
- @subid 1718
+ @subid 1970
@assert {
@@ -667,7 +667,7 @@
@syntax {
- @subid 1719
+ @subid 1971
@assert {
@@ -691,7 +691,7 @@
@syntax {
- @subid 1720
+ @subid 1972
@assert {
@@ -715,7 +715,7 @@
@syntax {
- @subid 1721
+ @subid 1973
@assert {
@@ -739,7 +739,7 @@
@syntax {
- @subid 1722
+ @subid 1974
@assert {
@@ -763,7 +763,7 @@
@syntax {
- @subid 1723
+ @subid 1975
@assert {
@@ -787,7 +787,7 @@
@syntax {
- @subid 1724
+ @subid 1976
@assert {
diff --git a/plugins/arm/v7/opdefs/A88383_vraddhn.d b/plugins/arm/v7/opdefs/A88383_vraddhn.d
index 466981e..731ebbb 100644
--- a/plugins/arm/v7/opdefs/A88383_vraddhn.d
+++ b/plugins/arm/v7/opdefs/A88383_vraddhn.d
@@ -23,7 +23,7 @@
@title VRADDHN
-@id 332
+@id 346
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1725
+ @subid 1977
@assert {
@@ -59,7 +59,7 @@
@syntax {
- @subid 1726
+ @subid 1978
@assert {
@@ -81,7 +81,7 @@
@syntax {
- @subid 1727
+ @subid 1979
@assert {
@@ -109,7 +109,7 @@
@syntax {
- @subid 1728
+ @subid 1980
@assert {
@@ -131,7 +131,7 @@
@syntax {
- @subid 1729
+ @subid 1981
@assert {
@@ -153,7 +153,7 @@
@syntax {
- @subid 1730
+ @subid 1982
@assert {
diff --git a/plugins/arm/v7/opdefs/A88384_vrecpe.d b/plugins/arm/v7/opdefs/A88384_vrecpe.d
index ea20988..4e3bc18 100644
--- a/plugins/arm/v7/opdefs/A88384_vrecpe.d
+++ b/plugins/arm/v7/opdefs/A88384_vrecpe.d
@@ -23,7 +23,7 @@
@title VRECPE
-@id 333
+@id 347
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1731
+ @subid 1983
@assert {
@@ -60,7 +60,7 @@
@syntax {
- @subid 1732
+ @subid 1984
@assert {
@@ -83,7 +83,7 @@
@syntax {
- @subid 1733
+ @subid 1985
@assert {
@@ -106,7 +106,7 @@
@syntax {
- @subid 1734
+ @subid 1986
@assert {
@@ -135,7 +135,7 @@
@syntax {
- @subid 1735
+ @subid 1987
@assert {
@@ -158,7 +158,7 @@
@syntax {
- @subid 1736
+ @subid 1988
@assert {
@@ -181,7 +181,7 @@
@syntax {
- @subid 1737
+ @subid 1989
@assert {
@@ -204,7 +204,7 @@
@syntax {
- @subid 1738
+ @subid 1990
@assert {
diff --git a/plugins/arm/v7/opdefs/A88385_vrecps.d b/plugins/arm/v7/opdefs/A88385_vrecps.d
index cf37d1e..6d8387a 100644
--- a/plugins/arm/v7/opdefs/A88385_vrecps.d
+++ b/plugins/arm/v7/opdefs/A88385_vrecps.d
@@ -23,7 +23,7 @@
@title VRECPS
-@id 334
+@id 348
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1739
+ @subid 1991
@assert {
@@ -59,7 +59,7 @@
@syntax {
- @subid 1740
+ @subid 1992
@assert {
@@ -87,7 +87,7 @@
@syntax {
- @subid 1741
+ @subid 1993
@assert {
@@ -109,7 +109,7 @@
@syntax {
- @subid 1742
+ @subid 1994
@assert {
diff --git a/plugins/arm/v7/opdefs/A88386_vrev.d b/plugins/arm/v7/opdefs/A88386_vrev.d
index f175c9f..c442e06 100644
--- a/plugins/arm/v7/opdefs/A88386_vrev.d
+++ b/plugins/arm/v7/opdefs/A88386_vrev.d
@@ -23,7 +23,7 @@
@title VREV16, VREV32, VREV64
-@id 335
+@id 349
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1743
+ @subid 1995
@assert {
@@ -60,7 +60,7 @@
@syntax {
- @subid 1744
+ @subid 1996
@assert {
@@ -83,7 +83,7 @@
@syntax {
- @subid 1745
+ @subid 1997
@assert {
@@ -106,7 +106,7 @@
@syntax {
- @subid 1746
+ @subid 1998
@assert {
@@ -129,7 +129,7 @@
@syntax {
- @subid 1747
+ @subid 1999
@assert {
@@ -152,7 +152,7 @@
@syntax {
- @subid 1748
+ @subid 2000
@assert {
@@ -175,7 +175,7 @@
@syntax {
- @subid 1749
+ @subid 2001
@assert {
@@ -198,7 +198,7 @@
@syntax {
- @subid 1750
+ @subid 2002
@assert {
@@ -221,7 +221,7 @@
@syntax {
- @subid 1751
+ @subid 2003
@assert {
@@ -244,7 +244,7 @@
@syntax {
- @subid 1752
+ @subid 2004
@assert {
@@ -267,7 +267,7 @@
@syntax {
- @subid 1753
+ @subid 2005
@assert {
@@ -290,7 +290,7 @@
@syntax {
- @subid 1754
+ @subid 2006
@assert {
@@ -313,7 +313,7 @@
@syntax {
- @subid 1755
+ @subid 2007
@assert {
@@ -336,7 +336,7 @@
@syntax {
- @subid 1756
+ @subid 2008
@assert {
@@ -359,7 +359,7 @@
@syntax {
- @subid 1757
+ @subid 2009
@assert {
@@ -382,7 +382,7 @@
@syntax {
- @subid 1758
+ @subid 2010
@assert {
@@ -405,7 +405,7 @@
@syntax {
- @subid 1759
+ @subid 2011
@assert {
@@ -428,7 +428,7 @@
@syntax {
- @subid 1760
+ @subid 2012
@assert {
@@ -457,7 +457,7 @@
@syntax {
- @subid 1761
+ @subid 2013
@assert {
@@ -480,7 +480,7 @@
@syntax {
- @subid 1762
+ @subid 2014
@assert {
@@ -503,7 +503,7 @@
@syntax {
- @subid 1763
+ @subid 2015
@assert {
@@ -526,7 +526,7 @@
@syntax {
- @subid 1764
+ @subid 2016
@assert {
@@ -549,7 +549,7 @@
@syntax {
- @subid 1765
+ @subid 2017
@assert {
@@ -572,7 +572,7 @@
@syntax {
- @subid 1766
+ @subid 2018
@assert {
@@ -595,7 +595,7 @@
@syntax {
- @subid 1767
+ @subid 2019
@assert {
@@ -618,7 +618,7 @@
@syntax {
- @subid 1768
+ @subid 2020
@assert {
@@ -641,7 +641,7 @@
@syntax {
- @subid 1769
+ @subid 2021
@assert {
@@ -664,7 +664,7 @@
@syntax {
- @subid 1770
+ @subid 2022
@assert {
@@ -687,7 +687,7 @@
@syntax {
- @subid 1771
+ @subid 2023
@assert {
@@ -710,7 +710,7 @@
@syntax {
- @subid 1772
+ @subid 2024
@assert {
@@ -733,7 +733,7 @@
@syntax {
- @subid 1773
+ @subid 2025
@assert {
@@ -756,7 +756,7 @@
@syntax {
- @subid 1774
+ @subid 2026
@assert {
@@ -779,7 +779,7 @@
@syntax {
- @subid 1775
+ @subid 2027
@assert {
@@ -802,7 +802,7 @@
@syntax {
- @subid 1776
+ @subid 2028
@assert {
@@ -825,7 +825,7 @@
@syntax {
- @subid 1777
+ @subid 2029
@assert {
@@ -848,7 +848,7 @@
@syntax {
- @subid 1778
+ @subid 2030
@assert {
diff --git a/plugins/arm/v7/opdefs/A88387_vrhadd.d b/plugins/arm/v7/opdefs/A88387_vrhadd.d
index d513037..e97aeaa 100644
--- a/plugins/arm/v7/opdefs/A88387_vrhadd.d
+++ b/plugins/arm/v7/opdefs/A88387_vrhadd.d
@@ -23,7 +23,7 @@
@title VRHADD
-@id 336
+@id 350
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1779
+ @subid 2031
@assert {
@@ -61,7 +61,7 @@
@syntax {
- @subid 1780
+ @subid 2032
@assert {
@@ -85,7 +85,7 @@
@syntax {
- @subid 1781
+ @subid 2033
@assert {
@@ -109,7 +109,7 @@
@syntax {
- @subid 1782
+ @subid 2034
@assert {
@@ -133,7 +133,7 @@
@syntax {
- @subid 1783
+ @subid 2035
@assert {
@@ -157,7 +157,7 @@
@syntax {
- @subid 1784
+ @subid 2036
@assert {
@@ -181,7 +181,7 @@
@syntax {
- @subid 1785
+ @subid 2037
@assert {
@@ -205,7 +205,7 @@
@syntax {
- @subid 1786
+ @subid 2038
@assert {
@@ -229,7 +229,7 @@
@syntax {
- @subid 1787
+ @subid 2039
@assert {
@@ -253,7 +253,7 @@
@syntax {
- @subid 1788
+ @subid 2040
@assert {
@@ -277,7 +277,7 @@
@syntax {
- @subid 1789
+ @subid 2041
@assert {
@@ -301,7 +301,7 @@
@syntax {
- @subid 1790
+ @subid 2042
@assert {
@@ -331,7 +331,7 @@
@syntax {
- @subid 1791
+ @subid 2043
@assert {
@@ -355,7 +355,7 @@
@syntax {
- @subid 1792
+ @subid 2044
@assert {
@@ -379,7 +379,7 @@
@syntax {
- @subid 1793
+ @subid 2045
@assert {
@@ -403,7 +403,7 @@
@syntax {
- @subid 1794
+ @subid 2046
@assert {
@@ -427,7 +427,7 @@
@syntax {
- @subid 1795
+ @subid 2047
@assert {
@@ -451,7 +451,7 @@
@syntax {
- @subid 1796
+ @subid 2048
@assert {
@@ -475,7 +475,7 @@
@syntax {
- @subid 1797
+ @subid 2049
@assert {
@@ -499,7 +499,7 @@
@syntax {
- @subid 1798
+ @subid 2050
@assert {
@@ -523,7 +523,7 @@
@syntax {
- @subid 1799
+ @subid 2051
@assert {
@@ -547,7 +547,7 @@
@syntax {
- @subid 1800
+ @subid 2052
@assert {
@@ -571,7 +571,7 @@
@syntax {
- @subid 1801
+ @subid 2053
@assert {
@@ -595,7 +595,7 @@
@syntax {
- @subid 1802
+ @subid 2054
@assert {
diff --git a/plugins/arm/v7/opdefs/A88388_vrshl.d b/plugins/arm/v7/opdefs/A88388_vrshl.d
index e050093..7291599 100644
--- a/plugins/arm/v7/opdefs/A88388_vrshl.d
+++ b/plugins/arm/v7/opdefs/A88388_vrshl.d
@@ -23,7 +23,7 @@
@title VRSHL
-@id 337
+@id 351
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1803
+ @subid 2055
@assert {
@@ -61,7 +61,7 @@
@syntax {
- @subid 1804
+ @subid 2056
@assert {
@@ -85,7 +85,7 @@
@syntax {
- @subid 1805
+ @subid 2057
@assert {
@@ -109,7 +109,7 @@
@syntax {
- @subid 1806
+ @subid 2058
@assert {
@@ -133,7 +133,7 @@
@syntax {
- @subid 1807
+ @subid 2059
@assert {
@@ -157,7 +157,7 @@
@syntax {
- @subid 1808
+ @subid 2060
@assert {
@@ -181,7 +181,7 @@
@syntax {
- @subid 1809
+ @subid 2061
@assert {
@@ -205,7 +205,7 @@
@syntax {
- @subid 1810
+ @subid 2062
@assert {
@@ -229,7 +229,7 @@
@syntax {
- @subid 1811
+ @subid 2063
@assert {
@@ -253,7 +253,7 @@
@syntax {
- @subid 1812
+ @subid 2064
@assert {
@@ -277,7 +277,7 @@
@syntax {
- @subid 1813
+ @subid 2065
@assert {
@@ -301,7 +301,7 @@
@syntax {
- @subid 1814
+ @subid 2066
@assert {
@@ -325,7 +325,7 @@
@syntax {
- @subid 1815
+ @subid 2067
@assert {
@@ -349,7 +349,7 @@
@syntax {
- @subid 1816
+ @subid 2068
@assert {
@@ -373,7 +373,7 @@
@syntax {
- @subid 1817
+ @subid 2069
@assert {
@@ -397,7 +397,7 @@
@syntax {
- @subid 1818
+ @subid 2070
@assert {
@@ -427,7 +427,7 @@
@syntax {
- @subid 1819
+ @subid 2071
@assert {
@@ -451,7 +451,7 @@
@syntax {
- @subid 1820
+ @subid 2072
@assert {
@@ -475,7 +475,7 @@
@syntax {
- @subid 1821
+ @subid 2073
@assert {
@@ -499,7 +499,7 @@
@syntax {
- @subid 1822
+ @subid 2074
@assert {
@@ -523,7 +523,7 @@
@syntax {
- @subid 1823
+ @subid 2075
@assert {
@@ -547,7 +547,7 @@
@syntax {
- @subid 1824
+ @subid 2076
@assert {
@@ -571,7 +571,7 @@
@syntax {
- @subid 1825
+ @subid 2077
@assert {
@@ -595,7 +595,7 @@
@syntax {
- @subid 1826
+ @subid 2078
@assert {
@@ -619,7 +619,7 @@
@syntax {
- @subid 1827
+ @subid 2079
@assert {
@@ -643,7 +643,7 @@
@syntax {
- @subid 1828
+ @subid 2080
@assert {
@@ -667,7 +667,7 @@
@syntax {
- @subid 1829
+ @subid 2081
@assert {
@@ -691,7 +691,7 @@
@syntax {
- @subid 1830
+ @subid 2082
@assert {
@@ -715,7 +715,7 @@
@syntax {
- @subid 1831
+ @subid 2083
@assert {
@@ -739,7 +739,7 @@
@syntax {
- @subid 1832
+ @subid 2084
@assert {
@@ -763,7 +763,7 @@
@syntax {
- @subid 1833
+ @subid 2085
@assert {
@@ -787,7 +787,7 @@
@syntax {
- @subid 1834
+ @subid 2086
@assert {
diff --git a/plugins/arm/v7/opdefs/A88391_vrsqrte.d b/plugins/arm/v7/opdefs/A88391_vrsqrte.d
index 23b9cfa..ef55798 100644
--- a/plugins/arm/v7/opdefs/A88391_vrsqrte.d
+++ b/plugins/arm/v7/opdefs/A88391_vrsqrte.d
@@ -23,7 +23,7 @@
@title VRSQRTE
-@id 338
+@id 352
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1835
+ @subid 2087
@assert {
@@ -60,7 +60,7 @@
@syntax {
- @subid 1836
+ @subid 2088
@assert {
@@ -83,7 +83,7 @@
@syntax {
- @subid 1837
+ @subid 2089
@assert {
@@ -106,7 +106,7 @@
@syntax {
- @subid 1838
+ @subid 2090
@assert {
@@ -135,7 +135,7 @@
@syntax {
- @subid 1839
+ @subid 2091
@assert {
@@ -158,7 +158,7 @@
@syntax {
- @subid 1840
+ @subid 2092
@assert {
@@ -181,7 +181,7 @@
@syntax {
- @subid 1841
+ @subid 2093
@assert {
@@ -204,7 +204,7 @@
@syntax {
- @subid 1842
+ @subid 2094
@assert {
diff --git a/plugins/arm/v7/opdefs/A88392_vrsqrts.d b/plugins/arm/v7/opdefs/A88392_vrsqrts.d
index eb16f2b..fdf4d41 100644
--- a/plugins/arm/v7/opdefs/A88392_vrsqrts.d
+++ b/plugins/arm/v7/opdefs/A88392_vrsqrts.d
@@ -23,7 +23,7 @@
@title VRSQRTS
-@id 339
+@id 353
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1843
+ @subid 2095
@assert {
@@ -60,7 +60,7 @@
@syntax {
- @subid 1844
+ @subid 2096
@assert {
@@ -89,7 +89,7 @@
@syntax {
- @subid 1845
+ @subid 2097
@assert {
@@ -112,7 +112,7 @@
@syntax {
- @subid 1846
+ @subid 2098
@assert {
diff --git a/plugins/arm/v7/opdefs/A88394_vrsubhn.d b/plugins/arm/v7/opdefs/A88394_vrsubhn.d
index 433377a..8ff3228 100644
--- a/plugins/arm/v7/opdefs/A88394_vrsubhn.d
+++ b/plugins/arm/v7/opdefs/A88394_vrsubhn.d
@@ -23,7 +23,7 @@
@title VRSUBHN
-@id 340
+@id 354
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1847
+ @subid 2099
@assert {
@@ -59,7 +59,7 @@
@syntax {
- @subid 1848
+ @subid 2100
@assert {
@@ -81,7 +81,7 @@
@syntax {
- @subid 1849
+ @subid 2101
@assert {
@@ -109,7 +109,7 @@
@syntax {
- @subid 1850
+ @subid 2102
@assert {
@@ -131,7 +131,7 @@
@syntax {
- @subid 1851
+ @subid 2103
@assert {
@@ -153,7 +153,7 @@
@syntax {
- @subid 1852
+ @subid 2104
@assert {
diff --git a/plugins/arm/v7/opdefs/A88396_vshl.d b/plugins/arm/v7/opdefs/A88396_vshl.d
index f72999d..85a0446 100644
--- a/plugins/arm/v7/opdefs/A88396_vshl.d
+++ b/plugins/arm/v7/opdefs/A88396_vshl.d
@@ -23,7 +23,7 @@
@title VSHL (register)
-@id 341
+@id 355
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1853
+ @subid 2105
@assert {
@@ -61,7 +61,7 @@
@syntax {
- @subid 1854
+ @subid 2106
@assert {
@@ -85,7 +85,7 @@
@syntax {
- @subid 1855
+ @subid 2107
@assert {
@@ -109,7 +109,7 @@
@syntax {
- @subid 1856
+ @subid 2108
@assert {
@@ -133,7 +133,7 @@
@syntax {
- @subid 1857
+ @subid 2109
@assert {
@@ -157,7 +157,7 @@
@syntax {
- @subid 1858
+ @subid 2110
@assert {
@@ -181,7 +181,7 @@
@syntax {
- @subid 1859
+ @subid 2111
@assert {
@@ -205,7 +205,7 @@
@syntax {
- @subid 1860
+ @subid 2112
@assert {
@@ -229,7 +229,7 @@
@syntax {
- @subid 1861
+ @subid 2113
@assert {
@@ -253,7 +253,7 @@
@syntax {
- @subid 1862
+ @subid 2114
@assert {
@@ -277,7 +277,7 @@
@syntax {
- @subid 1863
+ @subid 2115
@assert {
@@ -301,7 +301,7 @@
@syntax {
- @subid 1864
+ @subid 2116
@assert {
@@ -325,7 +325,7 @@
@syntax {
- @subid 1865
+ @subid 2117
@assert {
@@ -349,7 +349,7 @@
@syntax {
- @subid 1866
+ @subid 2118
@assert {
@@ -373,7 +373,7 @@
@syntax {
- @subid 1867
+ @subid 2119
@assert {
@@ -397,7 +397,7 @@
@syntax {
- @subid 1868
+ @subid 2120
@assert {
@@ -427,7 +427,7 @@
@syntax {
- @subid 1869
+ @subid 2121
@assert {
@@ -451,7 +451,7 @@
@syntax {
- @subid 1870
+ @subid 2122
@assert {
@@ -475,7 +475,7 @@
@syntax {
- @subid 1871
+ @subid 2123
@assert {
@@ -499,7 +499,7 @@
@syntax {
- @subid 1872
+ @subid 2124
@assert {
@@ -523,7 +523,7 @@
@syntax {
- @subid 1873
+ @subid 2125
@assert {
@@ -547,7 +547,7 @@
@syntax {
- @subid 1874
+ @subid 2126
@assert {
@@ -571,7 +571,7 @@
@syntax {
- @subid 1875
+ @subid 2127
@assert {
@@ -595,7 +595,7 @@
@syntax {
- @subid 1876
+ @subid 2128
@assert {
@@ -619,7 +619,7 @@
@syntax {
- @subid 1877
+ @subid 2129
@assert {
@@ -643,7 +643,7 @@
@syntax {
- @subid 1878
+ @subid 2130
@assert {
@@ -667,7 +667,7 @@
@syntax {
- @subid 1879
+ @subid 2131
@assert {
@@ -691,7 +691,7 @@
@syntax {
- @subid 1880
+ @subid 2132
@assert {
@@ -715,7 +715,7 @@
@syntax {
- @subid 1881
+ @subid 2133
@assert {
@@ -739,7 +739,7 @@
@syntax {
- @subid 1882
+ @subid 2134
@assert {
@@ -763,7 +763,7 @@
@syntax {
- @subid 1883
+ @subid 2135
@assert {
@@ -787,7 +787,7 @@
@syntax {
- @subid 1884
+ @subid 2136
@assert {
diff --git a/plugins/arm/v7/opdefs/A88401_vsqrt.d b/plugins/arm/v7/opdefs/A88401_vsqrt.d
index a3dd685..9cf2222 100644
--- a/plugins/arm/v7/opdefs/A88401_vsqrt.d
+++ b/plugins/arm/v7/opdefs/A88401_vsqrt.d
@@ -23,7 +23,7 @@
@title VSQRT
-@id 342
+@id 356
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1885
+ @subid 2137
@assert {
@@ -58,7 +58,7 @@
@syntax {
- @subid 1886
+ @subid 2138
@assert {
@@ -85,7 +85,7 @@
@syntax {
- @subid 1887
+ @subid 2139
@assert {
@@ -106,7 +106,7 @@
@syntax {
- @subid 1888
+ @subid 2140
@assert {
diff --git a/plugins/arm/v7/opdefs/A88413_vstr.d b/plugins/arm/v7/opdefs/A88413_vstr.d
new file mode 100644
index 0000000..cca3bc5
--- /dev/null
+++ b/plugins/arm/v7/opdefs/A88413_vstr.d
@@ -0,0 +1,125 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2017 Cyrille Bagard
+ *
+ * This file is part of Chrysalide.
+ *
+ * Chrysalide is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * Chrysalide is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title VSTR
+
+@id 357
+
+@desc {
+
+ This instruction stores a single extension register to memory, using an address from an ARM core register, with an optional offset. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of general controls of CP10 and CP11 functionality on page B1-1230 and Summary of access controls for Advanced SIMD functionality on page B1-1232 summarize these controls.
+
+}
+
+@encoding (T1) {
+
+ @word 1 1 1 0 1 1 0 1 U(1) D(1) 0 0 Rn(4) Vd(4) 1 0 1 1 imm8(8)
+
+ @syntax {
+
+ @subid 2141
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ reg_N = Register(Rn)
+ imm32 = ZeroExtend(imm8:'00', 32)
+ maccess = MemAccessOffset(reg_N, imm32)
+
+ }
+
+ @asm vstr dwvec_D maccess
+
+ }
+
+}
+
+@encoding (T2) {
+
+ @word 1 1 1 0 1 1 0 1 U(1) D(1) 0 0 Rn(4) Vd(4) 1 0 1 0 imm8(8)
+
+ @syntax {
+
+ @subid 2142
+
+ @conv {
+
+ swvec_D = SingleWordVector(Vd:D)
+ reg_N = Register(Rn)
+ imm32 = ZeroExtend(imm8:'00', 32)
+ maccess = MemAccessOffset(reg_N, imm32)
+
+ }
+
+ @asm vstr swvec_D maccess
+
+ }
+
+}
+
+@encoding (A1) {
+
+ @word 1 1 1 0 1 1 0 1 U(1) D(1) 0 0 Rn(4) Vd(4) 1 0 1 1 imm8(8)
+
+ @syntax {
+
+ @subid 2143
+
+ @conv {
+
+ dwvec_D = DoubleWordVector(D:Vd)
+ reg_N = Register(Rn)
+ imm32 = ZeroExtend(imm8:'00', 32)
+ maccess = MemAccessOffset(reg_N, imm32)
+
+ }
+
+ @asm vstr dwvec_D maccess
+
+ }
+
+}
+
+@encoding (A2) {
+
+ @word 1 1 1 0 1 1 0 1 U(1) D(1) 0 0 Rn(4) Vd(4) 1 0 1 0 imm8(8)
+
+ @syntax {
+
+ @subid 2144
+
+ @conv {
+
+ swvec_D = SingleWordVector(Vd:D)
+ reg_N = Register(Rn)
+ imm32 = ZeroExtend(imm8:'00', 32)
+ maccess = MemAccessOffset(reg_N, imm32)
+
+ }
+
+ @asm vstr swvec_D maccess
+
+ }
+
+}
+
diff --git a/plugins/arm/v7/opdefs/A88414_vsub.d b/plugins/arm/v7/opdefs/A88414_vsub.d
index 4b4e397..3081e98 100644
--- a/plugins/arm/v7/opdefs/A88414_vsub.d
+++ b/plugins/arm/v7/opdefs/A88414_vsub.d
@@ -23,7 +23,7 @@
@title VSUB (integer)
-@id 343
+@id 358
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1889
+ @subid 2145
@assert {
@@ -59,7 +59,7 @@
@syntax {
- @subid 1890
+ @subid 2146
@assert {
@@ -81,7 +81,7 @@
@syntax {
- @subid 1891
+ @subid 2147
@assert {
@@ -103,7 +103,7 @@
@syntax {
- @subid 1892
+ @subid 2148
@assert {
@@ -131,7 +131,7 @@
@syntax {
- @subid 1893
+ @subid 2149
@assert {
@@ -153,7 +153,7 @@
@syntax {
- @subid 1894
+ @subid 2150
@assert {
@@ -175,7 +175,7 @@
@syntax {
- @subid 1895
+ @subid 2151
@assert {
@@ -197,7 +197,7 @@
@syntax {
- @subid 1896
+ @subid 2152
@assert {
diff --git a/plugins/arm/v7/opdefs/A88415_vsub.d b/plugins/arm/v7/opdefs/A88415_vsub.d
index 382f5e2..21dc6e6 100644
--- a/plugins/arm/v7/opdefs/A88415_vsub.d
+++ b/plugins/arm/v7/opdefs/A88415_vsub.d
@@ -23,7 +23,7 @@
@title VSUB (floating-point)
-@id 344
+@id 359
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1897
+ @subid 2153
@assert {
@@ -60,7 +60,7 @@
@syntax {
- @subid 1898
+ @subid 2154
@assert {
@@ -89,7 +89,7 @@
@syntax {
- @subid 1899
+ @subid 2155
@assert {
@@ -111,7 +111,7 @@
@syntax {
- @subid 1900
+ @subid 2156
@assert {
@@ -139,7 +139,7 @@
@syntax {
- @subid 1901
+ @subid 2157
@assert {
@@ -162,7 +162,7 @@
@syntax {
- @subid 1902
+ @subid 2158
@assert {
@@ -191,7 +191,7 @@
@syntax {
- @subid 1903
+ @subid 2159
@assert {
@@ -213,7 +213,7 @@
@syntax {
- @subid 1904
+ @subid 2160
@assert {
diff --git a/plugins/arm/v7/opdefs/A88416_vsubhn.d b/plugins/arm/v7/opdefs/A88416_vsubhn.d
index 4a10208..19efab5 100644
--- a/plugins/arm/v7/opdefs/A88416_vsubhn.d
+++ b/plugins/arm/v7/opdefs/A88416_vsubhn.d
@@ -23,7 +23,7 @@
@title VSUBHN
-@id 345
+@id 360
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1905
+ @subid 2161
@assert {
@@ -59,7 +59,7 @@
@syntax {
- @subid 1906
+ @subid 2162
@assert {
@@ -81,7 +81,7 @@
@syntax {
- @subid 1907
+ @subid 2163
@assert {
@@ -109,7 +109,7 @@
@syntax {
- @subid 1908
+ @subid 2164
@assert {
@@ -131,7 +131,7 @@
@syntax {
- @subid 1909
+ @subid 2165
@assert {
@@ -153,7 +153,7 @@
@syntax {
- @subid 1910
+ @subid 2166
@assert {
diff --git a/plugins/arm/v7/opdefs/A88417_vsub.d b/plugins/arm/v7/opdefs/A88417_vsub.d
index ea0796d..e547bae 100644
--- a/plugins/arm/v7/opdefs/A88417_vsub.d
+++ b/plugins/arm/v7/opdefs/A88417_vsub.d
@@ -23,7 +23,7 @@
@title VSUBL, VSUBW
-@id 346
+@id 361
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1911
+ @subid 2167
@assert {
@@ -61,7 +61,7 @@
@syntax {
- @subid 1912
+ @subid 2168
@assert {
@@ -85,7 +85,7 @@
@syntax {
- @subid 1913
+ @subid 2169
@assert {
@@ -109,7 +109,7 @@
@syntax {
- @subid 1914
+ @subid 2170
@assert {
@@ -133,7 +133,7 @@
@syntax {
- @subid 1915
+ @subid 2171
@assert {
@@ -157,7 +157,7 @@
@syntax {
- @subid 1916
+ @subid 2172
@assert {
@@ -181,7 +181,7 @@
@syntax {
- @subid 1917
+ @subid 2173
@assert {
@@ -205,7 +205,7 @@
@syntax {
- @subid 1918
+ @subid 2174
@assert {
@@ -229,7 +229,7 @@
@syntax {
- @subid 1919
+ @subid 2175
@assert {
@@ -253,7 +253,7 @@
@syntax {
- @subid 1920
+ @subid 2176
@assert {
@@ -277,7 +277,7 @@
@syntax {
- @subid 1921
+ @subid 2177
@assert {
@@ -301,7 +301,7 @@
@syntax {
- @subid 1922
+ @subid 2178
@assert {
@@ -331,7 +331,7 @@
@syntax {
- @subid 1923
+ @subid 2179
@assert {
@@ -355,7 +355,7 @@
@syntax {
- @subid 1924
+ @subid 2180
@assert {
@@ -379,7 +379,7 @@
@syntax {
- @subid 1925
+ @subid 2181
@assert {
@@ -403,7 +403,7 @@
@syntax {
- @subid 1926
+ @subid 2182
@assert {
@@ -427,7 +427,7 @@
@syntax {
- @subid 1927
+ @subid 2183
@assert {
@@ -451,7 +451,7 @@
@syntax {
- @subid 1928
+ @subid 2184
@assert {
@@ -475,7 +475,7 @@
@syntax {
- @subid 1929
+ @subid 2185
@assert {
@@ -499,7 +499,7 @@
@syntax {
- @subid 1930
+ @subid 2186
@assert {
@@ -523,7 +523,7 @@
@syntax {
- @subid 1931
+ @subid 2187
@assert {
@@ -547,7 +547,7 @@
@syntax {
- @subid 1932
+ @subid 2188
@assert {
@@ -571,7 +571,7 @@
@syntax {
- @subid 1933
+ @subid 2189
@assert {
@@ -595,7 +595,7 @@
@syntax {
- @subid 1934
+ @subid 2190
@assert {
diff --git a/plugins/arm/v7/opdefs/A88418_vswp.d b/plugins/arm/v7/opdefs/A88418_vswp.d
index 39a29e2..68bb331 100644
--- a/plugins/arm/v7/opdefs/A88418_vswp.d
+++ b/plugins/arm/v7/opdefs/A88418_vswp.d
@@ -23,7 +23,7 @@
@title VSWP
-@id 347
+@id 362
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1935
+ @subid 2191
@assert {
@@ -59,7 +59,7 @@
@syntax {
- @subid 1936
+ @subid 2192
@assert {
@@ -87,7 +87,7 @@
@syntax {
- @subid 1937
+ @subid 2193
@assert {
@@ -109,7 +109,7 @@
@syntax {
- @subid 1938
+ @subid 2194
@assert {
diff --git a/plugins/arm/v7/opdefs/A88420_vtrn.d b/plugins/arm/v7/opdefs/A88420_vtrn.d
index f9ef77f..baf38c9 100644
--- a/plugins/arm/v7/opdefs/A88420_vtrn.d
+++ b/plugins/arm/v7/opdefs/A88420_vtrn.d
@@ -23,7 +23,7 @@
@title VTRN
-@id 348
+@id 363
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1939
+ @subid 2195
@assert {
@@ -59,7 +59,7 @@
@syntax {
- @subid 1940
+ @subid 2196
@assert {
@@ -81,7 +81,7 @@
@syntax {
- @subid 1941
+ @subid 2197
@assert {
@@ -103,7 +103,7 @@
@syntax {
- @subid 1942
+ @subid 2198
@assert {
@@ -125,7 +125,7 @@
@syntax {
- @subid 1943
+ @subid 2199
@assert {
@@ -147,7 +147,7 @@
@syntax {
- @subid 1944
+ @subid 2200
@assert {
@@ -175,7 +175,7 @@
@syntax {
- @subid 1945
+ @subid 2201
@assert {
@@ -197,7 +197,7 @@
@syntax {
- @subid 1946
+ @subid 2202
@assert {
@@ -219,7 +219,7 @@
@syntax {
- @subid 1947
+ @subid 2203
@assert {
@@ -241,7 +241,7 @@
@syntax {
- @subid 1948
+ @subid 2204
@assert {
@@ -263,7 +263,7 @@
@syntax {
- @subid 1949
+ @subid 2205
@assert {
@@ -285,7 +285,7 @@
@syntax {
- @subid 1950
+ @subid 2206
@assert {
diff --git a/plugins/arm/v7/opdefs/A88421_vtst.d b/plugins/arm/v7/opdefs/A88421_vtst.d
index bb0daf4..24471de 100644
--- a/plugins/arm/v7/opdefs/A88421_vtst.d
+++ b/plugins/arm/v7/opdefs/A88421_vtst.d
@@ -23,7 +23,7 @@
@title VTST
-@id 349
+@id 364
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1951
+ @subid 2207
@assert {
@@ -60,7 +60,7 @@
@syntax {
- @subid 1952
+ @subid 2208
@assert {
@@ -83,7 +83,7 @@
@syntax {
- @subid 1953
+ @subid 2209
@assert {
@@ -106,7 +106,7 @@
@syntax {
- @subid 1954
+ @subid 2210
@assert {
@@ -129,7 +129,7 @@
@syntax {
- @subid 1955
+ @subid 2211
@assert {
@@ -152,7 +152,7 @@
@syntax {
- @subid 1956
+ @subid 2212
@assert {
@@ -181,7 +181,7 @@
@syntax {
- @subid 1957
+ @subid 2213
@assert {
@@ -204,7 +204,7 @@
@syntax {
- @subid 1958
+ @subid 2214
@assert {
@@ -227,7 +227,7 @@
@syntax {
- @subid 1959
+ @subid 2215
@assert {
@@ -250,7 +250,7 @@
@syntax {
- @subid 1960
+ @subid 2216
@assert {
@@ -273,7 +273,7 @@
@syntax {
- @subid 1961
+ @subid 2217
@assert {
@@ -296,7 +296,7 @@
@syntax {
- @subid 1962
+ @subid 2218
@assert {
diff --git a/plugins/arm/v7/opdefs/A88422_vuzp.d b/plugins/arm/v7/opdefs/A88422_vuzp.d
index 8d4eff0..70d1426 100644
--- a/plugins/arm/v7/opdefs/A88422_vuzp.d
+++ b/plugins/arm/v7/opdefs/A88422_vuzp.d
@@ -23,7 +23,7 @@
@title VUZP
-@id 350
+@id 365
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1963
+ @subid 2219
@assert {
@@ -59,7 +59,7 @@
@syntax {
- @subid 1964
+ @subid 2220
@assert {
@@ -81,7 +81,7 @@
@syntax {
- @subid 1965
+ @subid 2221
@assert {
@@ -103,7 +103,7 @@
@syntax {
- @subid 1966
+ @subid 2222
@assert {
@@ -125,7 +125,7 @@
@syntax {
- @subid 1967
+ @subid 2223
@assert {
@@ -147,7 +147,7 @@
@syntax {
- @subid 1968
+ @subid 2224
@assert {
@@ -175,7 +175,7 @@
@syntax {
- @subid 1969
+ @subid 2225
@assert {
@@ -197,7 +197,7 @@
@syntax {
- @subid 1970
+ @subid 2226
@assert {
@@ -219,7 +219,7 @@
@syntax {
- @subid 1971
+ @subid 2227
@assert {
@@ -241,7 +241,7 @@
@syntax {
- @subid 1972
+ @subid 2228
@assert {
@@ -263,7 +263,7 @@
@syntax {
- @subid 1973
+ @subid 2229
@assert {
@@ -285,7 +285,7 @@
@syntax {
- @subid 1974
+ @subid 2230
@assert {
diff --git a/plugins/arm/v7/opdefs/A88423_vzip.d b/plugins/arm/v7/opdefs/A88423_vzip.d
index bdd1c49..bae666e 100644
--- a/plugins/arm/v7/opdefs/A88423_vzip.d
+++ b/plugins/arm/v7/opdefs/A88423_vzip.d
@@ -23,7 +23,7 @@
@title VZIP
-@id 351
+@id 366
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1975
+ @subid 2231
@assert {
@@ -59,7 +59,7 @@
@syntax {
- @subid 1976
+ @subid 2232
@assert {
@@ -81,7 +81,7 @@
@syntax {
- @subid 1977
+ @subid 2233
@assert {
@@ -103,7 +103,7 @@
@syntax {
- @subid 1978
+ @subid 2234
@assert {
@@ -125,7 +125,7 @@
@syntax {
- @subid 1979
+ @subid 2235
@assert {
@@ -147,7 +147,7 @@
@syntax {
- @subid 1980
+ @subid 2236
@assert {
@@ -175,7 +175,7 @@
@syntax {
- @subid 1981
+ @subid 2237
@assert {
@@ -197,7 +197,7 @@
@syntax {
- @subid 1982
+ @subid 2238
@assert {
@@ -219,7 +219,7 @@
@syntax {
- @subid 1983
+ @subid 2239
@assert {
@@ -241,7 +241,7 @@
@syntax {
- @subid 1984
+ @subid 2240
@assert {
@@ -263,7 +263,7 @@
@syntax {
- @subid 1985
+ @subid 2241
@assert {
@@ -285,7 +285,7 @@
@syntax {
- @subid 1986
+ @subid 2242
@assert {
diff --git a/plugins/arm/v7/opdefs/A88424_wfe.d b/plugins/arm/v7/opdefs/A88424_wfe.d
index 1196284..8f951a9 100644
--- a/plugins/arm/v7/opdefs/A88424_wfe.d
+++ b/plugins/arm/v7/opdefs/A88424_wfe.d
@@ -23,7 +23,7 @@
@title WFE
-@id 352
+@id 367
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1987
+ @subid 2243
@asm wfe
@@ -51,7 +51,7 @@
@syntax {
- @subid 1988
+ @subid 2244
@asm wfe.w
@@ -65,7 +65,7 @@
@syntax {
- @subid 1989
+ @subid 2245
@asm wfe
diff --git a/plugins/arm/v7/opdefs/A88425_wfi.d b/plugins/arm/v7/opdefs/A88425_wfi.d
index 2abe14c..95e1fad 100644
--- a/plugins/arm/v7/opdefs/A88425_wfi.d
+++ b/plugins/arm/v7/opdefs/A88425_wfi.d
@@ -23,7 +23,7 @@
@title WFI
-@id 353
+@id 368
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1990
+ @subid 2246
@asm wfi
@@ -51,7 +51,7 @@
@syntax {
- @subid 1991
+ @subid 2247
@asm wfi.w
@@ -65,7 +65,7 @@
@syntax {
- @subid 1992
+ @subid 2248
@asm wfi
diff --git a/plugins/arm/v7/opdefs/A88426_yield.d b/plugins/arm/v7/opdefs/A88426_yield.d
index 1f5ae2d..eef1730 100644
--- a/plugins/arm/v7/opdefs/A88426_yield.d
+++ b/plugins/arm/v7/opdefs/A88426_yield.d
@@ -23,7 +23,7 @@
@title YIELD
-@id 354
+@id 369
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1993
+ @subid 2249
@asm yield
@@ -51,7 +51,7 @@
@syntax {
- @subid 1994
+ @subid 2250
@asm yield.w
@@ -65,7 +65,7 @@
@syntax {
- @subid 1995
+ @subid 2251
@asm yield
diff --git a/plugins/arm/v7/opdefs/A931_enterx.d b/plugins/arm/v7/opdefs/A931_enterx.d
index 0d74778..f6ca54a 100644
--- a/plugins/arm/v7/opdefs/A931_enterx.d
+++ b/plugins/arm/v7/opdefs/A931_enterx.d
@@ -23,7 +23,7 @@
@title ENTERX, LEAVEX
-@id 355
+@id 370
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1996
+ @subid 2252
@assert {
@@ -51,7 +51,7 @@
@syntax {
- @subid 1997
+ @subid 2253
@assert {
diff --git a/plugins/arm/v7/opdefs/B9310_msr.d b/plugins/arm/v7/opdefs/B9310_msr.d
index 58f7985..1dd8ad6 100644
--- a/plugins/arm/v7/opdefs/B9310_msr.d
+++ b/plugins/arm/v7/opdefs/B9310_msr.d
@@ -23,7 +23,7 @@
@title MSR (Banked register)
-@id 365
+@id 380
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 2022
+ @subid 2278
@conv {
@@ -58,7 +58,7 @@
@syntax {
- @subid 2023
+ @subid 2279
@conv {
diff --git a/plugins/arm/v7/opdefs/B9311_msr.d b/plugins/arm/v7/opdefs/B9311_msr.d
index 56deb7d..a9d4f25 100644
--- a/plugins/arm/v7/opdefs/B9311_msr.d
+++ b/plugins/arm/v7/opdefs/B9311_msr.d
@@ -23,7 +23,7 @@
@title MSR (immediate)
-@id 366
+@id 381
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 2024
+ @subid 2280
@conv {
diff --git a/plugins/arm/v7/opdefs/B9312_msr.d b/plugins/arm/v7/opdefs/B9312_msr.d
index d627eb7..df86cd3 100644
--- a/plugins/arm/v7/opdefs/B9312_msr.d
+++ b/plugins/arm/v7/opdefs/B9312_msr.d
@@ -23,7 +23,7 @@
@title MSR (register)
-@id 367
+@id 382
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 2025
+ @subid 2281
@conv {
@@ -58,7 +58,7 @@
@syntax {
- @subid 2026
+ @subid 2282
@conv {
diff --git a/plugins/arm/v7/opdefs/B9313_rfe.d b/plugins/arm/v7/opdefs/B9313_rfe.d
index 07a1a06..ffaa207 100644
--- a/plugins/arm/v7/opdefs/B9313_rfe.d
+++ b/plugins/arm/v7/opdefs/B9313_rfe.d
@@ -23,7 +23,7 @@
@title RFE
-@id 368
+@id 383
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 2027
+ @subid 2283
@conv {
@@ -58,7 +58,7 @@
@syntax {
- @subid 2028
+ @subid 2284
@conv {
@@ -79,7 +79,7 @@
@syntax {
- @subid 2029
+ @subid 2285
@assert {
@@ -101,7 +101,7 @@
@syntax {
- @subid 2030
+ @subid 2286
@assert {
@@ -123,7 +123,7 @@
@syntax {
- @subid 2031
+ @subid 2287
@assert {
@@ -145,7 +145,7 @@
@syntax {
- @subid 2032
+ @subid 2288
@assert {
diff --git a/plugins/arm/v7/opdefs/B9314_smc.d b/plugins/arm/v7/opdefs/B9314_smc.d
index 94ff3e6..c20b6ca 100644
--- a/plugins/arm/v7/opdefs/B9314_smc.d
+++ b/plugins/arm/v7/opdefs/B9314_smc.d
@@ -23,7 +23,7 @@
@title SMC (previously SMI)
-@id 369
+@id 384
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 2033
+ @subid 2289
@conv {
@@ -57,7 +57,7 @@
@syntax {
- @subid 2034
+ @subid 2290
@conv {
diff --git a/plugins/arm/v7/opdefs/B9315_srs.d b/plugins/arm/v7/opdefs/B9315_srs.d
index 6c169a4..2e95dbc 100644
--- a/plugins/arm/v7/opdefs/B9315_srs.d
+++ b/plugins/arm/v7/opdefs/B9315_srs.d
@@ -23,7 +23,7 @@
@title SRS (Thumb)
-@id 370
+@id 385
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 2035
+ @subid 2291
@conv {
@@ -59,7 +59,7 @@
@syntax {
- @subid 2036
+ @subid 2292
@conv {
diff --git a/plugins/arm/v7/opdefs/B9316_srs.d b/plugins/arm/v7/opdefs/B9316_srs.d
index b70e57c..7793314 100644
--- a/plugins/arm/v7/opdefs/B9316_srs.d
+++ b/plugins/arm/v7/opdefs/B9316_srs.d
@@ -23,7 +23,7 @@
@title SRS (ARM)
-@id 371
+@id 386
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 2037
+ @subid 2293
@assert {
@@ -60,7 +60,7 @@
@syntax {
- @subid 2038
+ @subid 2294
@assert {
@@ -83,7 +83,7 @@
@syntax {
- @subid 2039
+ @subid 2295
@assert {
@@ -106,7 +106,7 @@
@syntax {
- @subid 2040
+ @subid 2296
@assert {
diff --git a/plugins/arm/v7/opdefs/B9317_stm.d b/plugins/arm/v7/opdefs/B9317_stm.d
index e914416..88b2f02 100644
--- a/plugins/arm/v7/opdefs/B9317_stm.d
+++ b/plugins/arm/v7/opdefs/B9317_stm.d
@@ -23,7 +23,7 @@
@title STM (User registers)
-@id 372
+@id 387
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 2041
+ @subid 2297
@assert {
@@ -65,7 +65,7 @@
@syntax {
- @subid 2042
+ @subid 2298
@assert {
@@ -93,7 +93,7 @@
@syntax {
- @subid 2043
+ @subid 2299
@assert {
@@ -121,7 +121,7 @@
@syntax {
- @subid 2044
+ @subid 2300
@assert {
diff --git a/plugins/arm/v7/opdefs/B9319_subs.d b/plugins/arm/v7/opdefs/B9319_subs.d
index 3f26879..21377a9 100644
--- a/plugins/arm/v7/opdefs/B9319_subs.d
+++ b/plugins/arm/v7/opdefs/B9319_subs.d
@@ -23,7 +23,7 @@
@title SUBS PC, LR (Thumb)
-@id 374
+@id 389
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 2045
+ @subid 2301
@conv {
diff --git a/plugins/arm/v7/opdefs/B931_cps.d b/plugins/arm/v7/opdefs/B931_cps.d
index b211619..60c19f8 100644
--- a/plugins/arm/v7/opdefs/B931_cps.d
+++ b/plugins/arm/v7/opdefs/B931_cps.d
@@ -23,7 +23,7 @@
@title CPS (Thumb)
-@id 356
+@id 371
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 1998
+ @subid 2254
@assert {
@@ -57,7 +57,7 @@
@syntax {
- @subid 1999
+ @subid 2255
@assert {
@@ -83,7 +83,7 @@
@syntax {
- @subid 2000
+ @subid 2256
@assert {
@@ -104,7 +104,7 @@
@syntax {
- @subid 2001
+ @subid 2257
@assert {
@@ -125,7 +125,7 @@
@syntax {
- @subid 2002
+ @subid 2258
@assert {
diff --git a/plugins/arm/v7/opdefs/B9320_subs.d b/plugins/arm/v7/opdefs/B9320_subs.d
index 661100c..c381676 100644
--- a/plugins/arm/v7/opdefs/B9320_subs.d
+++ b/plugins/arm/v7/opdefs/B9320_subs.d
@@ -23,7 +23,7 @@
@title SUBS PC, LR and related instructions (ARM)
-@id 375
+@id 390
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 2046
+ @subid 2302
@conv {
@@ -65,7 +65,7 @@
@syntax {
- @subid 2047
+ @subid 2303
@assert {
diff --git a/plugins/arm/v7/opdefs/B9321_vmrs.d b/plugins/arm/v7/opdefs/B9321_vmrs.d
index a90412b..f862120 100644
--- a/plugins/arm/v7/opdefs/B9321_vmrs.d
+++ b/plugins/arm/v7/opdefs/B9321_vmrs.d
@@ -23,7 +23,7 @@
@title VMRS
-@id 376
+@id 391
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 2048
+ @subid 2304
@conv {
@@ -58,7 +58,7 @@
@syntax {
- @subid 2049
+ @subid 2305
@conv {
diff --git a/plugins/arm/v7/opdefs/B9322_vmsr.d b/plugins/arm/v7/opdefs/B9322_vmsr.d
index 35859ce..aac4f4b 100644
--- a/plugins/arm/v7/opdefs/B9322_vmsr.d
+++ b/plugins/arm/v7/opdefs/B9322_vmsr.d
@@ -23,7 +23,7 @@
@title VMSR
-@id 377
+@id 392
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 2050
+ @subid 2306
@conv {
@@ -58,7 +58,7 @@
@syntax {
- @subid 2051
+ @subid 2307
@conv {
diff --git a/plugins/arm/v7/opdefs/B932_cps.d b/plugins/arm/v7/opdefs/B932_cps.d
index 5f28983..cad958f 100644
--- a/plugins/arm/v7/opdefs/B932_cps.d
+++ b/plugins/arm/v7/opdefs/B932_cps.d
@@ -23,7 +23,7 @@
@title CPS (ARM)
-@id 357
+@id 372
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 2003
+ @subid 2259
@assert {
@@ -58,7 +58,7 @@
@syntax {
- @subid 2004
+ @subid 2260
@assert {
@@ -79,7 +79,7 @@
@syntax {
- @subid 2005
+ @subid 2261
@assert {
diff --git a/plugins/arm/v7/opdefs/B933_eret.d b/plugins/arm/v7/opdefs/B933_eret.d
index c90e419..fae8572 100644
--- a/plugins/arm/v7/opdefs/B933_eret.d
+++ b/plugins/arm/v7/opdefs/B933_eret.d
@@ -23,7 +23,7 @@
@title ERET
-@id 358
+@id 373
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 2006
+ @subid 2262
@asm eret
@@ -51,7 +51,7 @@
@syntax {
- @subid 2007
+ @subid 2263
@asm eret
diff --git a/plugins/arm/v7/opdefs/B934_hvc.d b/plugins/arm/v7/opdefs/B934_hvc.d
index a4e6aa7..2a47638 100644
--- a/plugins/arm/v7/opdefs/B934_hvc.d
+++ b/plugins/arm/v7/opdefs/B934_hvc.d
@@ -23,7 +23,7 @@
@title HVC
-@id 359
+@id 374
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 2008
+ @subid 2264
@conv {
@@ -57,7 +57,7 @@
@syntax {
- @subid 2009
+ @subid 2265
@conv {
diff --git a/plugins/arm/v7/opdefs/B935_ldm.d b/plugins/arm/v7/opdefs/B935_ldm.d
index 1d5056f..f6501d0 100644
--- a/plugins/arm/v7/opdefs/B935_ldm.d
+++ b/plugins/arm/v7/opdefs/B935_ldm.d
@@ -23,7 +23,7 @@
@title LDM (exception return)
-@id 360
+@id 375
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 2010
+ @subid 2266
@assert {
@@ -66,7 +66,7 @@
@syntax {
- @subid 2011
+ @subid 2267
@assert {
@@ -95,7 +95,7 @@
@syntax {
- @subid 2012
+ @subid 2268
@assert {
@@ -124,7 +124,7 @@
@syntax {
- @subid 2013
+ @subid 2269
@assert {
diff --git a/plugins/arm/v7/opdefs/B936_ldm.d b/plugins/arm/v7/opdefs/B936_ldm.d
index 76776c2..b0e15ca 100644
--- a/plugins/arm/v7/opdefs/B936_ldm.d
+++ b/plugins/arm/v7/opdefs/B936_ldm.d
@@ -23,7 +23,7 @@
@title LDM (User registers)
-@id 361
+@id 376
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 2014
+ @subid 2270
@assert {
@@ -65,7 +65,7 @@
@syntax {
- @subid 2015
+ @subid 2271
@assert {
@@ -93,7 +93,7 @@
@syntax {
- @subid 2016
+ @subid 2272
@assert {
@@ -121,7 +121,7 @@
@syntax {
- @subid 2017
+ @subid 2273
@assert {
diff --git a/plugins/arm/v7/opdefs/B938_mrs.d b/plugins/arm/v7/opdefs/B938_mrs.d
index 9a49c02..44fc840 100644
--- a/plugins/arm/v7/opdefs/B938_mrs.d
+++ b/plugins/arm/v7/opdefs/B938_mrs.d
@@ -23,7 +23,7 @@
@title MRS
-@id 363
+@id 378
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 2018
+ @subid 2274
@conv {
@@ -58,7 +58,7 @@
@syntax {
- @subid 2019
+ @subid 2275
@conv {
diff --git a/plugins/arm/v7/opdefs/B939_mrs.d b/plugins/arm/v7/opdefs/B939_mrs.d
index c58c4da..7087264 100644
--- a/plugins/arm/v7/opdefs/B939_mrs.d
+++ b/plugins/arm/v7/opdefs/B939_mrs.d
@@ -23,7 +23,7 @@
@title MRS (Banked register)
-@id 364
+@id 379
@desc {
@@ -37,7 +37,7 @@
@syntax {
- @subid 2020
+ @subid 2276
@conv {
@@ -58,7 +58,7 @@
@syntax {
- @subid 2021
+ @subid 2277
@conv {
diff --git a/plugins/arm/v7/opdefs/Makefile.am b/plugins/arm/v7/opdefs/Makefile.am
index b2f6be0..877f27d 100644
--- a/plugins/arm/v7/opdefs/Makefile.am
+++ b/plugins/arm/v7/opdefs/Makefile.am
@@ -338,19 +338,31 @@ ARMV7_DEFS = \
A88303_vcmp.d \
A88304_vcnt.d \
A88305_vcvt.d \
+ A88306_vcvt.d \
+ A88309_vcvt.d \
+ A88310_vcvt.d \
+ A88311_vcvt.d \
A88312_vdiv.d \
A88314_vdup.d \
A88315_veor.d \
+ A88316_vext.d \
A88317_vfm.d \
A88318_vfnm.d \
A88319_vh.d \
A88334_vmax.d \
A88335_vmax.d \
+ A88336_vmla.d \
A88337_vmla.d \
+ A88343_vmov.d \
+ A88344_vmov.d \
A88345_vmov.d \
A88346_vmovl.d \
A88347_vmovn.d \
+ A88348_vmrs.d \
+ A88349_vmsr.d \
+ A88350_vmul.d \
A88351_vmul.d \
+ A88353_vmvn.d \
A88354_vmvn.d \
A88355_vneg.d \
A88356_vnm.d \
@@ -364,6 +376,8 @@ ARMV7_DEFS = \
A88365_vpmax.d \
A88366_vpmax.d \
A88369_vqabs.d \
+ A88370_vqadd.d \
+ A88374_vqmov.d \
A88375_vqneg.d \
A88377_vqrshl.d \
A88379_vqshl.d \
@@ -379,6 +393,7 @@ ARMV7_DEFS = \
A88394_vrsubhn.d \
A88396_vshl.d \
A88401_vsqrt.d \
+ A88413_vstr.d \
A88414_vsub.d \
A88415_vsub.d \
A88416_vsubhn.d \