diff options
| author | Cyrille Bagard <nocbos@gmail.com> | 2018-05-28 20:34:24 (GMT) |
|---|---|---|
| committer | Cyrille Bagard <nocbos@gmail.com> | 2018-05-28 20:34:24 (GMT) |
| commit | 5311a943dffcc410739509b9215ca464f6d1e54c (patch) | |
| tree | 9c34b5176606aa7bb3dcfb5970a20e3f9b27f1c3 /plugins/arm/v7/opdefs/eor_A8846.d | |
| parent | 9f5ed46de568d3db882c939c8ca9d0117bff3369 (diff) | |
Included support for ARMv7 system instructions.
Diffstat (limited to 'plugins/arm/v7/opdefs/eor_A8846.d')
| -rw-r--r-- | plugins/arm/v7/opdefs/eor_A8846.d | 145 |
1 files changed, 0 insertions, 145 deletions
diff --git a/plugins/arm/v7/opdefs/eor_A8846.d b/plugins/arm/v7/opdefs/eor_A8846.d deleted file mode 100644 index dfafa9b..0000000 --- a/plugins/arm/v7/opdefs/eor_A8846.d +++ /dev/null @@ -1,145 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title EOR (immediate) - -@id 45 - -@desc { - - Bitwise Exclusive OR (immediate) performs a bitwise Exclusive OR of a register value and an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -} - -@encoding (T1) { - - @word 1 1 1 1 0 i(1) 0 0 1 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - - @syntax { - - @subid 127 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) - - } - - @asm eor ?reg_D reg_N const - - } - - @syntax { - - @subid 128 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) - - } - - @asm eors ?reg_D reg_N const - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 0 0 0 1 S(1) Rn(4) Rd(4) imm12(12) - - @syntax { - - @subid 129 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - const = ARMExpandImm_C(imm12, APSR_C) - - } - - @asm eor ?reg_D reg_N const - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 130 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - const = ARMExpandImm_C(imm12, APSR_C) - - } - - @asm eors ?reg_D reg_N const - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - |