Included support for ARMv7 system instructions.

280 files changed, 2483 insertions, 476 deletions

diff --git a/plugins/arm/v7/opdefs/mla_A88100.d b/plugins/arm/v7/opdefs/A88100_mla.d
index ec8b92b..d5d0b94 100644
--- a/plugins/arm/v7/opdefs/mla_A88100.d
+++ b/plugins/arm/v7/opdefs/A88100_mla.d
@@ -23,7 +23,7 @@
 
 @title MLA
 
-@id 99
+@id 94
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/mls_A88101.d b/plugins/arm/v7/opdefs/A88101_mls.d
index 083e4e1..7fc527b 100644
--- a/plugins/arm/v7/opdefs/mls_A88101.d
+++ b/plugins/arm/v7/opdefs/A88101_mls.d
@@ -23,7 +23,7 @@
 
 @title MLS
 
-@id 100
+@id 95
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/mov_A88102.d b/plugins/arm/v7/opdefs/A88102_mov.d
index 805bc16..d3925b6 100644
--- a/plugins/arm/v7/opdefs/mov_A88102.d
+++ b/plugins/arm/v7/opdefs/A88102_mov.d
@@ -23,7 +23,7 @@
 
 @title MOV (immediate)
 
-@id 101
+@id 96
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/mov_A88103.d b/plugins/arm/v7/opdefs/A88103_mov.d
index 9497800..4f40758 100644
--- a/plugins/arm/v7/opdefs/mov_A88103.d
+++ b/plugins/arm/v7/opdefs/A88103_mov.d
@@ -23,7 +23,7 @@
 
 @title MOV (register, Thumb)
 
-@id 102
+@id 97
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/mov_A88104.d b/plugins/arm/v7/opdefs/A88104_mov.d
index 3d7eb99..e6a758c 100644
--- a/plugins/arm/v7/opdefs/mov_A88104.d
+++ b/plugins/arm/v7/opdefs/A88104_mov.d
@@ -23,7 +23,7 @@
 
 @title MOV (register, ARM)
 
-@id 103
+@id 98
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/movt_A88106.d b/plugins/arm/v7/opdefs/A88106_movt.d
index dc024df..fc6bd84 100644
--- a/plugins/arm/v7/opdefs/movt_A88106.d
+++ b/plugins/arm/v7/opdefs/A88106_movt.d
@@ -23,7 +23,7 @@
 
 @title MOVT
 
-@id 105
+@id 100
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/mrc_A88107.d b/plugins/arm/v7/opdefs/A88107_mrc.d
index ab3f0a1..1053e95 100644
--- a/plugins/arm/v7/opdefs/mrc_A88107.d
+++ b/plugins/arm/v7/opdefs/A88107_mrc.d
@@ -23,7 +23,7 @@
 
 @title MRC, MRC2
 
-@id 106
+@id 101
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/mrrc_A88108.d b/plugins/arm/v7/opdefs/A88108_mrrc.d
index ea25147..3f451d5 100644
--- a/plugins/arm/v7/opdefs/mrrc_A88108.d
+++ b/plugins/arm/v7/opdefs/A88108_mrrc.d
@@ -23,7 +23,7 @@
 
 @title MRRC, MRRC2
 
-@id 107
+@id 102
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/mrs_A88109.d b/plugins/arm/v7/opdefs/A88109_mrs.d
index 6ea0208..dd6215c 100644
--- a/plugins/arm/v7/opdefs/mrs_A88109.d
+++ b/plugins/arm/v7/opdefs/A88109_mrs.d
@@ -23,7 +23,7 @@
 
 @title MRS
 
-@id 108
+@id 103
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/add_A8810.d b/plugins/arm/v7/opdefs/A8810_add.d
index 357dadc..357dadc 100644
--- a/plugins/arm/v7/opdefs/add_A8810.d
+++ b/plugins/arm/v7/opdefs/A8810_add.d
diff --git a/plugins/arm/v7/opdefs/msr_A88111.d b/plugins/arm/v7/opdefs/A88111_msr.d
index ccf86df..5def4c5 100644
--- a/plugins/arm/v7/opdefs/msr_A88111.d
+++ b/plugins/arm/v7/opdefs/A88111_msr.d
@@ -23,7 +23,7 @@
 
 @title MSR (immediate)
 
-@id 110
+@id 105
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/msr_A88112.d b/plugins/arm/v7/opdefs/A88112_msr.d
index 89aedc3..4967f01 100644
--- a/plugins/arm/v7/opdefs/msr_A88112.d
+++ b/plugins/arm/v7/opdefs/A88112_msr.d
@@ -23,7 +23,7 @@
 
 @title MSR (register)
 
-@id 111
+@id 106
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/mul_A88114.d b/plugins/arm/v7/opdefs/A88114_mul.d
index 9eb245f..341de39 100644
--- a/plugins/arm/v7/opdefs/mul_A88114.d
+++ b/plugins/arm/v7/opdefs/A88114_mul.d
@@ -23,7 +23,7 @@
 
 @title MUL
 
-@id 113
+@id 108
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/mvn_A88115.d b/plugins/arm/v7/opdefs/A88115_mvn.d
index 23d9525..ed0e7b8 100644
--- a/plugins/arm/v7/opdefs/mvn_A88115.d
+++ b/plugins/arm/v7/opdefs/A88115_mvn.d
@@ -23,7 +23,7 @@
 
 @title MVN (immediate)
 
-@id 114
+@id 109
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/mvn_A88116.d b/plugins/arm/v7/opdefs/A88116_mvn.d
index db9e070..208e7ad 100644
--- a/plugins/arm/v7/opdefs/mvn_A88116.d
+++ b/plugins/arm/v7/opdefs/A88116_mvn.d
@@ -23,7 +23,7 @@
 
 @title MVN (register)
 
-@id 115
+@id 110
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/mvn_A88117.d b/plugins/arm/v7/opdefs/A88117_mvn.d
index 8e88096..a4cd19f 100644
--- a/plugins/arm/v7/opdefs/mvn_A88117.d
+++ b/plugins/arm/v7/opdefs/A88117_mvn.d
@@ -23,7 +23,7 @@
 
 @title MVN (register-shifted register)
 
-@id 116
+@id 111
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/nop_A88119.d b/plugins/arm/v7/opdefs/A88119_nop.d
index 8efcb03..a46e84a 100644
--- a/plugins/arm/v7/opdefs/nop_A88119.d
+++ b/plugins/arm/v7/opdefs/A88119_nop.d
@@ -23,7 +23,7 @@
 
 @title NOP
 
-@id 118
+@id 113
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/add_A8811.d b/plugins/arm/v7/opdefs/A8811_add.d
index f5c19aa..f5c19aa 100644
--- a/plugins/arm/v7/opdefs/add_A8811.d
+++ b/plugins/arm/v7/opdefs/A8811_add.d
diff --git a/plugins/arm/v7/opdefs/orn_A88120.d b/plugins/arm/v7/opdefs/A88120_orn.d
index b90857d..61c2b20 100644
--- a/plugins/arm/v7/opdefs/orn_A88120.d
+++ b/plugins/arm/v7/opdefs/A88120_orn.d
@@ -23,7 +23,7 @@
 
 @title ORN (immediate)
 
-@id 119
+@id 114
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/orn_A88121.d b/plugins/arm/v7/opdefs/A88121_orn.d
index 4e98abe..cacb69d 100644
--- a/plugins/arm/v7/opdefs/orn_A88121.d
+++ b/plugins/arm/v7/opdefs/A88121_orn.d
@@ -23,7 +23,7 @@
 
 @title ORN (register)
 
-@id 120
+@id 115
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/orr_A88122.d b/plugins/arm/v7/opdefs/A88122_orr.d
index 9855ad2..0f502a5 100644
--- a/plugins/arm/v7/opdefs/orr_A88122.d
+++ b/plugins/arm/v7/opdefs/A88122_orr.d
@@ -23,7 +23,7 @@
 
 @title ORR (immediate)
 
-@id 121
+@id 116
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/orr_A88123.d b/plugins/arm/v7/opdefs/A88123_orr.d
index 0a28002..c7a82dd 100644
--- a/plugins/arm/v7/opdefs/orr_A88123.d
+++ b/plugins/arm/v7/opdefs/A88123_orr.d
@@ -23,7 +23,7 @@
 
 @title ORR (register)
 
-@id 122
+@id 117
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/orr_A88124.d b/plugins/arm/v7/opdefs/A88124_orr.d
index adc1d42..f38333d 100644
--- a/plugins/arm/v7/opdefs/orr_A88124.d
+++ b/plugins/arm/v7/opdefs/A88124_orr.d
@@ -23,7 +23,7 @@
 
 @title ORR (register-shifted register)
 
-@id 123
+@id 118
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/pkh_A88125.d b/plugins/arm/v7/opdefs/A88125_pkh.d
index 1ca6a30..4b0c330 100644
--- a/plugins/arm/v7/opdefs/pkh_A88125.d
+++ b/plugins/arm/v7/opdefs/A88125_pkh.d
@@ -23,7 +23,7 @@
 
 @title PKH
 
-@id 124
+@id 119
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/pld_A88126.d b/plugins/arm/v7/opdefs/A88126_pld.d
index 3a82fe4..174ef24 100644
--- a/plugins/arm/v7/opdefs/pld_A88126.d
+++ b/plugins/arm/v7/opdefs/A88126_pld.d
@@ -23,7 +23,7 @@
 
 @title PLD, PLDW (immediate)
 
-@id 125
+@id 120
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/pld_A88127.d b/plugins/arm/v7/opdefs/A88127_pld.d
index e753579..5f85a38 100644
--- a/plugins/arm/v7/opdefs/pld_A88127.d
+++ b/plugins/arm/v7/opdefs/A88127_pld.d
@@ -23,7 +23,7 @@
 
 @title PLD (literal)
 
-@id 126
+@id 121
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/pld_A88128.d b/plugins/arm/v7/opdefs/A88128_pld.d
index 5c7eb2d..cfe6b0c 100644
--- a/plugins/arm/v7/opdefs/pld_A88128.d
+++ b/plugins/arm/v7/opdefs/A88128_pld.d
@@ -23,7 +23,7 @@
 
 @title PLD, PLDW (register)
 
-@id 127
+@id 122
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/adr_A8812.d b/plugins/arm/v7/opdefs/A8812_adr.d
index 1f77eea..1f77eea 100644
--- a/plugins/arm/v7/opdefs/adr_A8812.d
+++ b/plugins/arm/v7/opdefs/A8812_adr.d
diff --git a/plugins/arm/v7/opdefs/pli_A88130.d b/plugins/arm/v7/opdefs/A88130_pli.d
index e669ff8..97cff04 100644
--- a/plugins/arm/v7/opdefs/pli_A88130.d
+++ b/plugins/arm/v7/opdefs/A88130_pli.d
@@ -23,7 +23,7 @@
 
 @title PLI (register)
 
-@id 129
+@id 123
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/pop_A88131.d b/plugins/arm/v7/opdefs/A88131_pop.d
index 12f1254..41fe0b7 100644
--- a/plugins/arm/v7/opdefs/pop_A88131.d
+++ b/plugins/arm/v7/opdefs/A88131_pop.d
@@ -23,7 +23,7 @@
 
 @title POP (Thumb)
 
-@id 130
+@id 124
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/pop_A88132.d b/plugins/arm/v7/opdefs/A88132_pop.d
index f4e681e..9b95613 100644
--- a/plugins/arm/v7/opdefs/pop_A88132.d
+++ b/plugins/arm/v7/opdefs/A88132_pop.d
@@ -23,7 +23,7 @@
 
 @title POP (ARM)
 
-@id 131
+@id 125
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/push_A88133.d b/plugins/arm/v7/opdefs/A88133_push.d
index 6240e66..bb1502d 100644
--- a/plugins/arm/v7/opdefs/push_A88133.d
+++ b/plugins/arm/v7/opdefs/A88133_push.d
@@ -23,7 +23,7 @@
 
 @title PUSH
 
-@id 132
+@id 126
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/qadd_A88134.d b/plugins/arm/v7/opdefs/A88134_qadd.d
index 11d86b1..4617c02 100644
--- a/plugins/arm/v7/opdefs/qadd_A88134.d
+++ b/plugins/arm/v7/opdefs/A88134_qadd.d
@@ -23,7 +23,7 @@
 
 @title QADD
 
-@id 133
+@id 127
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/qadd16_A88135.d b/plugins/arm/v7/opdefs/A88135_qadd16.d
index 4bcaff9..7aa565b 100644
--- a/plugins/arm/v7/opdefs/qadd16_A88135.d
+++ b/plugins/arm/v7/opdefs/A88135_qadd16.d
@@ -23,7 +23,7 @@
 
 @title QADD16
 
-@id 134
+@id 128
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/qadd8_A88136.d b/plugins/arm/v7/opdefs/A88136_qadd8.d
index 7ceda6a..0b00037 100644
--- a/plugins/arm/v7/opdefs/qadd8_A88136.d
+++ b/plugins/arm/v7/opdefs/A88136_qadd8.d
@@ -23,7 +23,7 @@
 
 @title QADD8
 
-@id 135
+@id 129
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/qasx_A88137.d b/plugins/arm/v7/opdefs/A88137_qasx.d
index 4c62bca..be7a880 100644
--- a/plugins/arm/v7/opdefs/qasx_A88137.d
+++ b/plugins/arm/v7/opdefs/A88137_qasx.d
@@ -23,7 +23,7 @@
 
 @title QASX
 
-@id 136
+@id 130
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/qdadd_A88138.d b/plugins/arm/v7/opdefs/A88138_qdadd.d
index 8f49b67..0058e44 100644
--- a/plugins/arm/v7/opdefs/qdadd_A88138.d
+++ b/plugins/arm/v7/opdefs/A88138_qdadd.d
@@ -23,7 +23,7 @@
 
 @title QDADD
 
-@id 137
+@id 131
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/qdsub_A88139.d b/plugins/arm/v7/opdefs/A88139_qdsub.d
index 2747f27..cd7cd21 100644
--- a/plugins/arm/v7/opdefs/qdsub_A88139.d
+++ b/plugins/arm/v7/opdefs/A88139_qdsub.d
@@ -23,7 +23,7 @@
 
 @title QDSUB
 
-@id 138
+@id 132
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/and_A8813.d b/plugins/arm/v7/opdefs/A8813_and.d
index 988bdd7..988bdd7 100644
--- a/plugins/arm/v7/opdefs/and_A8813.d
+++ b/plugins/arm/v7/opdefs/A8813_and.d
diff --git a/plugins/arm/v7/opdefs/qsax_A88140.d b/plugins/arm/v7/opdefs/A88140_qsax.d
index f8217b2..3aec301 100644
--- a/plugins/arm/v7/opdefs/qsax_A88140.d
+++ b/plugins/arm/v7/opdefs/A88140_qsax.d
@@ -23,7 +23,7 @@
 
 @title QSAX
 
-@id 139
+@id 133
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/qsub_A88141.d b/plugins/arm/v7/opdefs/A88141_qsub.d
index 89d034b..6f9631f 100644
--- a/plugins/arm/v7/opdefs/qsub_A88141.d
+++ b/plugins/arm/v7/opdefs/A88141_qsub.d
@@ -23,7 +23,7 @@
 
 @title QSUB
 
-@id 140
+@id 134
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/qsub16_A88142.d b/plugins/arm/v7/opdefs/A88142_qsub16.d
index b971c85..9d9eb8a 100644
--- a/plugins/arm/v7/opdefs/qsub16_A88142.d
+++ b/plugins/arm/v7/opdefs/A88142_qsub16.d
@@ -23,7 +23,7 @@
 
 @title QSUB16
 
-@id 141
+@id 135
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/qsub8_A88143.d b/plugins/arm/v7/opdefs/A88143_qsub8.d
index d7f96c7..23e77be 100644
--- a/plugins/arm/v7/opdefs/qsub8_A88143.d
+++ b/plugins/arm/v7/opdefs/A88143_qsub8.d
@@ -23,7 +23,7 @@
 
 @title QSUB8
 
-@id 142
+@id 136
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/rbit_A88144.d b/plugins/arm/v7/opdefs/A88144_rbit.d
index b5c610c..f28a7d9 100644
--- a/plugins/arm/v7/opdefs/rbit_A88144.d
+++ b/plugins/arm/v7/opdefs/A88144_rbit.d
@@ -23,7 +23,7 @@
 
 @title RBIT
 
-@id 143
+@id 137
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/rev_A88145.d b/plugins/arm/v7/opdefs/A88145_rev.d
index cb81837..33ed857 100644
--- a/plugins/arm/v7/opdefs/rev_A88145.d
+++ b/plugins/arm/v7/opdefs/A88145_rev.d
@@ -23,7 +23,7 @@
 
 @title REV
 
-@id 144
+@id 138
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/rev16_A88146.d b/plugins/arm/v7/opdefs/A88146_rev16.d
index 49821e5..326a5e6 100644
--- a/plugins/arm/v7/opdefs/rev16_A88146.d
+++ b/plugins/arm/v7/opdefs/A88146_rev16.d
@@ -23,7 +23,7 @@
 
 @title REV16
 
-@id 145
+@id 139
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/revsh_A88147.d b/plugins/arm/v7/opdefs/A88147_revsh.d
index bf04a89..824e46d 100644
--- a/plugins/arm/v7/opdefs/revsh_A88147.d
+++ b/plugins/arm/v7/opdefs/A88147_revsh.d
@@ -23,7 +23,7 @@
 
 @title REVSH
 
-@id 146
+@id 140
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/ror_A88149.d b/plugins/arm/v7/opdefs/A88149_ror.d
index 98735fd..402cbbd 100644
--- a/plugins/arm/v7/opdefs/ror_A88149.d
+++ b/plugins/arm/v7/opdefs/A88149_ror.d
@@ -23,7 +23,7 @@
 
 @title ROR (immediate)
 
-@id 148
+@id 142
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/and_A8814.d b/plugins/arm/v7/opdefs/A8814_and.d
index 1a807f9..1a807f9 100644
--- a/plugins/arm/v7/opdefs/and_A8814.d
+++ b/plugins/arm/v7/opdefs/A8814_and.d
diff --git a/plugins/arm/v7/opdefs/ror_A88150.d b/plugins/arm/v7/opdefs/A88150_ror.d
index 031f56e..c2ff476 100644
--- a/plugins/arm/v7/opdefs/ror_A88150.d
+++ b/plugins/arm/v7/opdefs/A88150_ror.d
@@ -23,7 +23,7 @@
 
 @title ROR (register)
 
-@id 149
+@id 143
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/rrx_A88151.d b/plugins/arm/v7/opdefs/A88151_rrx.d
index 445a5d3..f78791d 100644
--- a/plugins/arm/v7/opdefs/rrx_A88151.d
+++ b/plugins/arm/v7/opdefs/A88151_rrx.d
@@ -23,7 +23,7 @@
 
 @title RRX
 
-@id 150
+@id 144
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/rsb_A88152.d b/plugins/arm/v7/opdefs/A88152_rsb.d
index 9b5e13e..cc5a1c6 100644
--- a/plugins/arm/v7/opdefs/rsb_A88152.d
+++ b/plugins/arm/v7/opdefs/A88152_rsb.d
@@ -23,7 +23,7 @@
 
 @title RSB (immediate)
 
-@id 151
+@id 145
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/rsb_A88153.d b/plugins/arm/v7/opdefs/A88153_rsb.d
index cb8ad6d..aedd51d 100644
--- a/plugins/arm/v7/opdefs/rsb_A88153.d
+++ b/plugins/arm/v7/opdefs/A88153_rsb.d
@@ -23,7 +23,7 @@
 
 @title RSB (register)
 
-@id 152
+@id 146
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/rsb_A88154.d b/plugins/arm/v7/opdefs/A88154_rsb.d
index cfc0a11..8fe52ef 100644
--- a/plugins/arm/v7/opdefs/rsb_A88154.d
+++ b/plugins/arm/v7/opdefs/A88154_rsb.d
@@ -23,7 +23,7 @@
 
 @title RSB (register-shifted register)
 
-@id 153
+@id 147
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/rsc_A88155.d b/plugins/arm/v7/opdefs/A88155_rsc.d
index e30a4a1..8f2688f 100644
--- a/plugins/arm/v7/opdefs/rsc_A88155.d
+++ b/plugins/arm/v7/opdefs/A88155_rsc.d
@@ -23,7 +23,7 @@
 
 @title RSC (immediate)
 
-@id 154
+@id 148
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/rsc_A88156.d b/plugins/arm/v7/opdefs/A88156_rsc.d
index 63d39fb..0efd043 100644
--- a/plugins/arm/v7/opdefs/rsc_A88156.d
+++ b/plugins/arm/v7/opdefs/A88156_rsc.d
@@ -23,7 +23,7 @@
 
 @title RSC (register)
 
-@id 155
+@id 149
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/rsc_A88157.d b/plugins/arm/v7/opdefs/A88157_rsc.d
index 25d1ea2..6d2a46f 100644
--- a/plugins/arm/v7/opdefs/rsc_A88157.d
+++ b/plugins/arm/v7/opdefs/A88157_rsc.d
@@ -23,7 +23,7 @@
 
 @title RSC (register-shifted register)
 
-@id 156
+@id 150
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/sadd16_A88158.d b/plugins/arm/v7/opdefs/A88158_sadd16.d
index b181221..10917ec 100644
--- a/plugins/arm/v7/opdefs/sadd16_A88158.d
+++ b/plugins/arm/v7/opdefs/A88158_sadd16.d
@@ -23,7 +23,7 @@
 
 @title SADD16
 
-@id 157
+@id 151
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/sadd8_A88159.d b/plugins/arm/v7/opdefs/A88159_sadd8.d
index 94a91d7..cf9bb74 100644
--- a/plugins/arm/v7/opdefs/sadd8_A88159.d
+++ b/plugins/arm/v7/opdefs/A88159_sadd8.d
@@ -23,7 +23,7 @@
 
 @title SADD8
 
-@id 158
+@id 152
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/and_A8815.d b/plugins/arm/v7/opdefs/A8815_and.d
index 3d890cb..3d890cb 100644
--- a/plugins/arm/v7/opdefs/and_A8815.d
+++ b/plugins/arm/v7/opdefs/A8815_and.d
diff --git a/plugins/arm/v7/opdefs/sasx_A88160.d b/plugins/arm/v7/opdefs/A88160_sasx.d
index 30c86be..676915a 100644
--- a/plugins/arm/v7/opdefs/sasx_A88160.d
+++ b/plugins/arm/v7/opdefs/A88160_sasx.d
@@ -23,7 +23,7 @@
 
 @title SASX
 
-@id 159
+@id 153
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/sbc_A88161.d b/plugins/arm/v7/opdefs/A88161_sbc.d
index 8d307fa..9962438 100644
--- a/plugins/arm/v7/opdefs/sbc_A88161.d
+++ b/plugins/arm/v7/opdefs/A88161_sbc.d
@@ -23,7 +23,7 @@
 
 @title SBC (immediate)
 
-@id 160
+@id 154
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/sbc_A88162.d b/plugins/arm/v7/opdefs/A88162_sbc.d
index 27f97fc..f931d4d 100644
--- a/plugins/arm/v7/opdefs/sbc_A88162.d
+++ b/plugins/arm/v7/opdefs/A88162_sbc.d
@@ -23,7 +23,7 @@
 
 @title SBC (register)
 
-@id 161
+@id 155
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/sbc_A88163.d b/plugins/arm/v7/opdefs/A88163_sbc.d
index a7e7c27..f287959 100644
--- a/plugins/arm/v7/opdefs/sbc_A88163.d
+++ b/plugins/arm/v7/opdefs/A88163_sbc.d
@@ -23,7 +23,7 @@
 
 @title SBC (register-shifted register)
 
-@id 162
+@id 156
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/sbfx_A88164.d b/plugins/arm/v7/opdefs/A88164_sbfx.d
index 8a3f4de..bdc3fbd 100644
--- a/plugins/arm/v7/opdefs/sbfx_A88164.d
+++ b/plugins/arm/v7/opdefs/A88164_sbfx.d
@@ -23,7 +23,7 @@
 
 @title SBFX
 
-@id 163
+@id 157
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/sdiv_A88165.d b/plugins/arm/v7/opdefs/A88165_sdiv.d
index 0e74d6c..498cafd 100644
--- a/plugins/arm/v7/opdefs/sdiv_A88165.d
+++ b/plugins/arm/v7/opdefs/A88165_sdiv.d
@@ -23,7 +23,7 @@
 
 @title SDIV
 
-@id 164
+@id 158
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/sel_A88166.d b/plugins/arm/v7/opdefs/A88166_sel.d
index 660dd46..3fb9747 100644
--- a/plugins/arm/v7/opdefs/sel_A88166.d
+++ b/plugins/arm/v7/opdefs/A88166_sel.d
@@ -23,7 +23,7 @@
 
 @title SEL
 
-@id 165
+@id 159
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/setend_A88167.d b/plugins/arm/v7/opdefs/A88167_setend.d
index ac6d59b..c9d3f0a 100644
--- a/plugins/arm/v7/opdefs/setend_A88167.d
+++ b/plugins/arm/v7/opdefs/A88167_setend.d
@@ -23,7 +23,7 @@
 
 @title SETEND
 
-@id 166
+@id 160
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/sev_A88168.d b/plugins/arm/v7/opdefs/A88168_sev.d
index 8695ace..23d7cae 100644
--- a/plugins/arm/v7/opdefs/sev_A88168.d
+++ b/plugins/arm/v7/opdefs/A88168_sev.d
@@ -23,7 +23,7 @@
 
 @title SEV
 
-@id 167
+@id 161
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/shadd16_A88169.d b/plugins/arm/v7/opdefs/A88169_shadd16.d
index 0ecbd43..c0f8fd5 100644
--- a/plugins/arm/v7/opdefs/shadd16_A88169.d
+++ b/plugins/arm/v7/opdefs/A88169_shadd16.d
@@ -23,7 +23,7 @@
 
 @title SHADD16
 
-@id 168
+@id 162
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/asr_A8816.d b/plugins/arm/v7/opdefs/A8816_asr.d
index 401c4c5..401c4c5 100644
--- a/plugins/arm/v7/opdefs/asr_A8816.d
+++ b/plugins/arm/v7/opdefs/A8816_asr.d
diff --git a/plugins/arm/v7/opdefs/shadd8_A88170.d b/plugins/arm/v7/opdefs/A88170_shadd8.d
index c1d358a..d08052e 100644
--- a/plugins/arm/v7/opdefs/shadd8_A88170.d
+++ b/plugins/arm/v7/opdefs/A88170_shadd8.d
@@ -23,7 +23,7 @@
 
 @title SHADD8
 
-@id 169
+@id 163
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/shasx_A88171.d b/plugins/arm/v7/opdefs/A88171_shasx.d
index b48ef07..5761f3d 100644
--- a/plugins/arm/v7/opdefs/shasx_A88171.d
+++ b/plugins/arm/v7/opdefs/A88171_shasx.d
@@ -23,7 +23,7 @@
 
 @title SHASX
 
-@id 170
+@id 164
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/shsax_A88172.d b/plugins/arm/v7/opdefs/A88172_shsax.d
index f9d0742..af81443 100644
--- a/plugins/arm/v7/opdefs/shsax_A88172.d
+++ b/plugins/arm/v7/opdefs/A88172_shsax.d
@@ -23,7 +23,7 @@
 
 @title SHSAX
 
-@id 171
+@id 165
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/shsub16_A88173.d b/plugins/arm/v7/opdefs/A88173_shsub16.d
index 802def4..de01a16 100644
--- a/plugins/arm/v7/opdefs/shsub16_A88173.d
+++ b/plugins/arm/v7/opdefs/A88173_shsub16.d
@@ -23,7 +23,7 @@
 
 @title SHSUB16
 
-@id 172
+@id 166
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/shsub8_A88174.d b/plugins/arm/v7/opdefs/A88174_shsub8.d
index a4113db..e8b6eab 100644
--- a/plugins/arm/v7/opdefs/shsub8_A88174.d
+++ b/plugins/arm/v7/opdefs/A88174_shsub8.d
@@ -23,7 +23,7 @@
 
 @title SHSUB8
 
-@id 173
+@id 167
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/smla_A88176.d b/plugins/arm/v7/opdefs/A88176_smla.d
index b167f82..10d9bcc 100644
--- a/plugins/arm/v7/opdefs/smla_A88176.d
+++ b/plugins/arm/v7/opdefs/A88176_smla.d
@@ -23,7 +23,7 @@
 
 @title SMLABB, SMLABT, SMLATB, SMLATT
 
-@id 175
+@id 169
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/smlad_A88177.d b/plugins/arm/v7/opdefs/A88177_smlad.d
index ff62a60..c27b907 100644
--- a/plugins/arm/v7/opdefs/smlad_A88177.d
+++ b/plugins/arm/v7/opdefs/A88177_smlad.d
@@ -23,7 +23,7 @@
 
 @title SMLAD
 
-@id 176
+@id 170
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/smlal_A88178.d b/plugins/arm/v7/opdefs/A88178_smlal.d
index 311ae7d..cb1909a 100644
--- a/plugins/arm/v7/opdefs/smlal_A88178.d
+++ b/plugins/arm/v7/opdefs/A88178_smlal.d
@@ -23,7 +23,7 @@
 
 @title SMLAL
 
-@id 177
+@id 171
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/smlal_A88179.d b/plugins/arm/v7/opdefs/A88179_smlal.d
index f7ce190..fa09e7c 100644
--- a/plugins/arm/v7/opdefs/smlal_A88179.d
+++ b/plugins/arm/v7/opdefs/A88179_smlal.d
@@ -23,7 +23,7 @@
 
 @title SMLALBB, SMLALBT, SMLALTB, SMLALTT
 
-@id 178
+@id 172
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/asr_A8817.d b/plugins/arm/v7/opdefs/A8817_asr.d
index 0ddeae9..0ddeae9 100644
--- a/plugins/arm/v7/opdefs/asr_A8817.d
+++ b/plugins/arm/v7/opdefs/A8817_asr.d
diff --git a/plugins/arm/v7/opdefs/smlald_A88180.d b/plugins/arm/v7/opdefs/A88180_smlald.d
index ed8e718..39a475c 100644
--- a/plugins/arm/v7/opdefs/smlald_A88180.d
+++ b/plugins/arm/v7/opdefs/A88180_smlald.d
@@ -23,7 +23,7 @@
 
 @title SMLALD
 
-@id 179
+@id 173
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/smlaw_A88181.d b/plugins/arm/v7/opdefs/A88181_smlaw.d
index d9b8918..d7aaa7f 100644
--- a/plugins/arm/v7/opdefs/smlaw_A88181.d
+++ b/plugins/arm/v7/opdefs/A88181_smlaw.d
@@ -23,7 +23,7 @@
 
 @title SMLAWB, SMLAWT
 
-@id 180
+@id 174
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/smlsd_A88182.d b/plugins/arm/v7/opdefs/A88182_smlsd.d
index e24eb18..90a2ca7 100644
--- a/plugins/arm/v7/opdefs/smlsd_A88182.d
+++ b/plugins/arm/v7/opdefs/A88182_smlsd.d
@@ -23,7 +23,7 @@
 
 @title SMLSD
 
-@id 181
+@id 175
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/smlsld_A88183.d b/plugins/arm/v7/opdefs/A88183_smlsld.d
index 2b82705..bca92d9 100644
--- a/plugins/arm/v7/opdefs/smlsld_A88183.d
+++ b/plugins/arm/v7/opdefs/A88183_smlsld.d
@@ -23,7 +23,7 @@
 
 @title SMLSLD
 
-@id 182
+@id 176
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/smmla_A88184.d b/plugins/arm/v7/opdefs/A88184_smmla.d
index a025895..a805bff 100644
--- a/plugins/arm/v7/opdefs/smmla_A88184.d
+++ b/plugins/arm/v7/opdefs/A88184_smmla.d
@@ -23,7 +23,7 @@
 
 @title SMMLA
 
-@id 183
+@id 177
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/smmls_A88185.d b/plugins/arm/v7/opdefs/A88185_smmls.d
index 18bd82c..e195b3b 100644
--- a/plugins/arm/v7/opdefs/smmls_A88185.d
+++ b/plugins/arm/v7/opdefs/A88185_smmls.d
@@ -23,7 +23,7 @@
 
 @title SMMLS
 
-@id 184
+@id 178
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/smmul_A88186.d b/plugins/arm/v7/opdefs/A88186_smmul.d
index f1b2579..31ed01d 100644
--- a/plugins/arm/v7/opdefs/smmul_A88186.d
+++ b/plugins/arm/v7/opdefs/A88186_smmul.d
@@ -23,7 +23,7 @@
 
 @title SMMUL
 
-@id 185
+@id 179
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/smuad_A88187.d b/plugins/arm/v7/opdefs/A88187_smuad.d
index c5fc1e8..47d4d9e 100644
--- a/plugins/arm/v7/opdefs/smuad_A88187.d
+++ b/plugins/arm/v7/opdefs/A88187_smuad.d
@@ -23,7 +23,7 @@
 
 @title SMUAD
 
-@id 186
+@id 180
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/smul_A88188.d b/plugins/arm/v7/opdefs/A88188_smul.d
index 18d8631..6d01041 100644
--- a/plugins/arm/v7/opdefs/smul_A88188.d
+++ b/plugins/arm/v7/opdefs/A88188_smul.d
@@ -23,7 +23,7 @@
 
 @title SMULBB, SMULBT, SMULTB, SMULTT
 
-@id 187
+@id 181
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/smull_A88189.d b/plugins/arm/v7/opdefs/A88189_smull.d
index 1903894..35e1d46 100644
--- a/plugins/arm/v7/opdefs/smull_A88189.d
+++ b/plugins/arm/v7/opdefs/A88189_smull.d
@@ -23,7 +23,7 @@
 
 @title SMULL
 
-@id 188
+@id 182
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/b_A8818.d b/plugins/arm/v7/opdefs/A8818_b.d
index d10b297..d10b297 100644
--- a/plugins/arm/v7/opdefs/b_A8818.d
+++ b/plugins/arm/v7/opdefs/A8818_b.d
diff --git a/plugins/arm/v7/opdefs/smulw_A88190.d b/plugins/arm/v7/opdefs/A88190_smulw.d
index 5b5d5d3..8c3a2e1 100644
--- a/plugins/arm/v7/opdefs/smulw_A88190.d
+++ b/plugins/arm/v7/opdefs/A88190_smulw.d
@@ -23,7 +23,7 @@
 
 @title SMULWB, SMULWT
 
-@id 189
+@id 183
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/smusd_A88191.d b/plugins/arm/v7/opdefs/A88191_smusd.d
index 7ab2e6d..d6f8aed 100644
--- a/plugins/arm/v7/opdefs/smusd_A88191.d
+++ b/plugins/arm/v7/opdefs/A88191_smusd.d
@@ -23,7 +23,7 @@
 
 @title SMUSD
 
-@id 190
+@id 184
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/ssat_A88193.d b/plugins/arm/v7/opdefs/A88193_ssat.d
index 835b80f..e381f92 100644
--- a/plugins/arm/v7/opdefs/ssat_A88193.d
+++ b/plugins/arm/v7/opdefs/A88193_ssat.d
@@ -23,7 +23,7 @@
 
 @title SSAT
 
-@id 192
+@id 186
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/ssat16_A88194.d b/plugins/arm/v7/opdefs/A88194_ssat16.d
index 6cae060..02c52df 100644
--- a/plugins/arm/v7/opdefs/ssat16_A88194.d
+++ b/plugins/arm/v7/opdefs/A88194_ssat16.d
@@ -23,7 +23,7 @@
 
 @title SSAT16
 
-@id 193
+@id 187
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/ssax_A88195.d b/plugins/arm/v7/opdefs/A88195_ssax.d
index be5e94a..257be5e 100644
--- a/plugins/arm/v7/opdefs/ssax_A88195.d
+++ b/plugins/arm/v7/opdefs/A88195_ssax.d
@@ -23,7 +23,7 @@
 
 @title SSAX
 
-@id 194
+@id 188
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/ssub16_A88196.d b/plugins/arm/v7/opdefs/A88196_ssub16.d
index b3a1935..54ed2dd 100644
--- a/plugins/arm/v7/opdefs/ssub16_A88196.d
+++ b/plugins/arm/v7/opdefs/A88196_ssub16.d
@@ -23,7 +23,7 @@
 
 @title SSUB16
 
-@id 195
+@id 189
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/ssub8_A88197.d b/plugins/arm/v7/opdefs/A88197_ssub8.d
index b7b9d9c..43f32ba 100644
--- a/plugins/arm/v7/opdefs/ssub8_A88197.d
+++ b/plugins/arm/v7/opdefs/A88197_ssub8.d
@@ -23,7 +23,7 @@
 
 @title SSUB8
 
-@id 196
+@id 190
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/stc_A88198.d b/plugins/arm/v7/opdefs/A88198_stc.d
index 88b68ac..764d611 100644
--- a/plugins/arm/v7/opdefs/stc_A88198.d
+++ b/plugins/arm/v7/opdefs/A88198_stc.d
@@ -23,7 +23,7 @@
 
 @title STC, STC2
 
-@id 197
+@id 191
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/stm_A88199.d b/plugins/arm/v7/opdefs/A88199_stm.d
index 0b519e6..610c757 100644
--- a/plugins/arm/v7/opdefs/stm_A88199.d
+++ b/plugins/arm/v7/opdefs/A88199_stm.d
@@ -23,7 +23,7 @@
 
 @title STM (STMIA, STMEA)
 
-@id 198
+@id 192
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/bfc_A8819.d b/plugins/arm/v7/opdefs/A8819_bfc.d
index f8875e5..f8875e5 100644
--- a/plugins/arm/v7/opdefs/bfc_A8819.d
+++ b/plugins/arm/v7/opdefs/A8819_bfc.d
diff --git a/plugins/arm/v7/opdefs/adc_A881.d b/plugins/arm/v7/opdefs/A881_adc.d
index d470638..d470638 100644
--- a/plugins/arm/v7/opdefs/adc_A881.d
+++ b/plugins/arm/v7/opdefs/A881_adc.d
diff --git a/plugins/arm/v7/opdefs/stmda_A88200.d b/plugins/arm/v7/opdefs/A88200_stmda.d
index 8515c74..192f7e9 100644
--- a/plugins/arm/v7/opdefs/stmda_A88200.d
+++ b/plugins/arm/v7/opdefs/A88200_stmda.d
@@ -23,7 +23,7 @@
 
 @title STMDA (STMED)
 
-@id 199
+@id 193
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/stmdb_A88201.d b/plugins/arm/v7/opdefs/A88201_stmdb.d
index 52d7bfb..cce1a8b 100644
--- a/plugins/arm/v7/opdefs/stmdb_A88201.d
+++ b/plugins/arm/v7/opdefs/A88201_stmdb.d
@@ -23,7 +23,7 @@
 
 @title STMDB (STMFD)
 
-@id 200
+@id 194
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/stmib_A88202.d b/plugins/arm/v7/opdefs/A88202_stmib.d
index 9ce1840..fa881e0 100644
--- a/plugins/arm/v7/opdefs/stmib_A88202.d
+++ b/plugins/arm/v7/opdefs/A88202_stmib.d
@@ -23,7 +23,7 @@
 
 @title STMIB (STMFA)
 
-@id 201
+@id 195
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/str_A88203.d b/plugins/arm/v7/opdefs/A88203_str.d
index 591641b..680562f 100644
--- a/plugins/arm/v7/opdefs/str_A88203.d
+++ b/plugins/arm/v7/opdefs/A88203_str.d
@@ -23,7 +23,7 @@
 
 @title STR (immediate, Thumb)
 
-@id 202
+@id 196
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/str_A88204.d b/plugins/arm/v7/opdefs/A88204_str.d
index 6182de8..d280fb4 100644
--- a/plugins/arm/v7/opdefs/str_A88204.d
+++ b/plugins/arm/v7/opdefs/A88204_str.d
@@ -23,7 +23,7 @@
 
 @title STR (immediate, ARM)
 
-@id 203
+@id 197
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/str_A88205.d b/plugins/arm/v7/opdefs/A88205_str.d
index cbc9f78..0e33f0e 100644
--- a/plugins/arm/v7/opdefs/str_A88205.d
+++ b/plugins/arm/v7/opdefs/A88205_str.d
@@ -23,7 +23,7 @@
 
 @title STR (register)
 
-@id 204
+@id 198
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/strb_A88206.d b/plugins/arm/v7/opdefs/A88206_strb.d
index cb7b74a..acceb11 100644
--- a/plugins/arm/v7/opdefs/strb_A88206.d
+++ b/plugins/arm/v7/opdefs/A88206_strb.d
@@ -23,7 +23,7 @@
 
 @title STRB (immediate, Thumb)
 
-@id 205
+@id 199
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/strb_A88207.d b/plugins/arm/v7/opdefs/A88207_strb.d
index 3ee78b9..74e43c8 100644
--- a/plugins/arm/v7/opdefs/strb_A88207.d
+++ b/plugins/arm/v7/opdefs/A88207_strb.d
@@ -23,7 +23,7 @@
 
 @title STRB (immediate, ARM)
 
-@id 206
+@id 200
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/strb_A88208.d b/plugins/arm/v7/opdefs/A88208_strb.d
index 8ecc962..07801b0 100644
--- a/plugins/arm/v7/opdefs/strb_A88208.d
+++ b/plugins/arm/v7/opdefs/A88208_strb.d
@@ -23,7 +23,7 @@
 
 @title STRB (register)
 
-@id 207
+@id 201
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/strbt_A88209.d b/plugins/arm/v7/opdefs/A88209_strbt.d
index ac91408..b7f4bfb 100644
--- a/plugins/arm/v7/opdefs/strbt_A88209.d
+++ b/plugins/arm/v7/opdefs/A88209_strbt.d
@@ -23,7 +23,7 @@
 
 @title STRBT
 
-@id 208
+@id 202
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/bfi_A8820.d b/plugins/arm/v7/opdefs/A8820_bfi.d
index aa71aa8..aa71aa8 100644
--- a/plugins/arm/v7/opdefs/bfi_A8820.d
+++ b/plugins/arm/v7/opdefs/A8820_bfi.d
diff --git a/plugins/arm/v7/opdefs/strd_A88210.d b/plugins/arm/v7/opdefs/A88210_strd.d
index 83e7af7..41a9cf8 100644
--- a/plugins/arm/v7/opdefs/strd_A88210.d
+++ b/plugins/arm/v7/opdefs/A88210_strd.d
@@ -23,7 +23,7 @@
 
 @title STRD (immediate)
 
-@id 209
+@id 203
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/strd_A88211.d b/plugins/arm/v7/opdefs/A88211_strd.d
index 817d2f1..407dfe3 100644
--- a/plugins/arm/v7/opdefs/strd_A88211.d
+++ b/plugins/arm/v7/opdefs/A88211_strd.d
@@ -23,7 +23,7 @@
 
 @title STRD (register)
 
-@id 210
+@id 204
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/strex_A88212.d b/plugins/arm/v7/opdefs/A88212_strex.d
index 8a3ab87..b73767e 100644
--- a/plugins/arm/v7/opdefs/strex_A88212.d
+++ b/plugins/arm/v7/opdefs/A88212_strex.d
@@ -23,7 +23,7 @@
 
 @title STREX
 
-@id 211
+@id 205
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/strexb_A88213.d b/plugins/arm/v7/opdefs/A88213_strexb.d
index 45ec2f2..40aa68e 100644
--- a/plugins/arm/v7/opdefs/strexb_A88213.d
+++ b/plugins/arm/v7/opdefs/A88213_strexb.d
@@ -23,7 +23,7 @@
 
 @title STREXB
 
-@id 212
+@id 206
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/strexd_A88214.d b/plugins/arm/v7/opdefs/A88214_strexd.d
index ec1f4f6..cef38ed 100644
--- a/plugins/arm/v7/opdefs/strexd_A88214.d
+++ b/plugins/arm/v7/opdefs/A88214_strexd.d
@@ -23,7 +23,7 @@
 
 @title STREXD
 
-@id 213
+@id 207
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/strexh_A88215.d b/plugins/arm/v7/opdefs/A88215_strexh.d
index 6ca68ce..3066ddc 100644
--- a/plugins/arm/v7/opdefs/strexh_A88215.d
+++ b/plugins/arm/v7/opdefs/A88215_strexh.d
@@ -23,7 +23,7 @@
 
 @title STREXH
 
-@id 214
+@id 208
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/strh_A88216.d b/plugins/arm/v7/opdefs/A88216_strh.d
index fadbcbe..5376406 100644
--- a/plugins/arm/v7/opdefs/strh_A88216.d
+++ b/plugins/arm/v7/opdefs/A88216_strh.d
@@ -23,7 +23,7 @@
 
 @title STRH (immediate, Thumb)
 
-@id 215
+@id 209
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/strh_A88217.d b/plugins/arm/v7/opdefs/A88217_strh.d
index 76fc365..b3f7763 100644
--- a/plugins/arm/v7/opdefs/strh_A88217.d
+++ b/plugins/arm/v7/opdefs/A88217_strh.d
@@ -23,7 +23,7 @@
 
 @title STRH (immediate, ARM)
 
-@id 216
+@id 210
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/strh_A88218.d b/plugins/arm/v7/opdefs/A88218_strh.d
index 0d222a8..7a5a23b 100644
--- a/plugins/arm/v7/opdefs/strh_A88218.d
+++ b/plugins/arm/v7/opdefs/A88218_strh.d
@@ -23,7 +23,7 @@
 
 @title STRH (register)
 
-@id 217
+@id 211
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/strht_A88219.d b/plugins/arm/v7/opdefs/A88219_strht.d
index a15db3a..5ed4f1b 100644
--- a/plugins/arm/v7/opdefs/strht_A88219.d
+++ b/plugins/arm/v7/opdefs/A88219_strht.d
@@ -23,7 +23,7 @@
 
 @title STRHT
 
-@id 218
+@id 212
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/bic_A8821.d b/plugins/arm/v7/opdefs/A8821_bic.d
index 59d4bb0..59d4bb0 100644
--- a/plugins/arm/v7/opdefs/bic_A8821.d
+++ b/plugins/arm/v7/opdefs/A8821_bic.d
diff --git a/plugins/arm/v7/opdefs/strt_A88220.d b/plugins/arm/v7/opdefs/A88220_strt.d
index 0750a0d..feb9927 100644
--- a/plugins/arm/v7/opdefs/strt_A88220.d
+++ b/plugins/arm/v7/opdefs/A88220_strt.d
@@ -23,7 +23,7 @@
 
 @title STRT
 
-@id 219
+@id 213
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/sub_A88221.d b/plugins/arm/v7/opdefs/A88221_sub.d
index 30ccb68..415c99e 100644
--- a/plugins/arm/v7/opdefs/sub_A88221.d
+++ b/plugins/arm/v7/opdefs/A88221_sub.d
@@ -23,7 +23,7 @@
 
 @title SUB (immediate, Thumb)
 
-@id 220
+@id 214
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/sub_A88222.d b/plugins/arm/v7/opdefs/A88222_sub.d
index 74bb4e0..14489a7 100644
--- a/plugins/arm/v7/opdefs/sub_A88222.d
+++ b/plugins/arm/v7/opdefs/A88222_sub.d
@@ -23,7 +23,7 @@
 
 @title SUB (immediate, ARM)
 
-@id 221
+@id 215
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/sub_A88223.d b/plugins/arm/v7/opdefs/A88223_sub.d
index 1498889..585fa60 100644
--- a/plugins/arm/v7/opdefs/sub_A88223.d
+++ b/plugins/arm/v7/opdefs/A88223_sub.d
@@ -23,7 +23,7 @@
 
 @title SUB (register)
 
-@id 222
+@id 216
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/sub_A88224.d b/plugins/arm/v7/opdefs/A88224_sub.d
index e52e818..bf7cee4 100644
--- a/plugins/arm/v7/opdefs/sub_A88224.d
+++ b/plugins/arm/v7/opdefs/A88224_sub.d
@@ -23,7 +23,7 @@
 
 @title SUB (register-shifted register)
 
-@id 223
+@id 217
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/sub_A88225.d b/plugins/arm/v7/opdefs/A88225_sub.d
index 3248f19..c8b95d4 100644
--- a/plugins/arm/v7/opdefs/sub_A88225.d
+++ b/plugins/arm/v7/opdefs/A88225_sub.d
@@ -23,7 +23,7 @@
 
 @title SUB (SP minus immediate)
 
-@id 224
+@id 218
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/sub_A88226.d b/plugins/arm/v7/opdefs/A88226_sub.d
index cdbd277..3f42232 100644
--- a/plugins/arm/v7/opdefs/sub_A88226.d
+++ b/plugins/arm/v7/opdefs/A88226_sub.d
@@ -23,7 +23,7 @@
 
 @title SUB (SP minus register)
 
-@id 225
+@id 219
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/svc_A88228.d b/plugins/arm/v7/opdefs/A88228_svc.d
index d9f709e..c74f818 100644
--- a/plugins/arm/v7/opdefs/svc_A88228.d
+++ b/plugins/arm/v7/opdefs/A88228_svc.d
@@ -23,7 +23,7 @@
 
 @title SVC (previously SWI)
 
-@id 227
+@id 221
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/swp_A88229.d b/plugins/arm/v7/opdefs/A88229_swp.d
index 09a8110..6d8261a 100644
--- a/plugins/arm/v7/opdefs/swp_A88229.d
+++ b/plugins/arm/v7/opdefs/A88229_swp.d
@@ -23,7 +23,7 @@
 
 @title SWP, SWPB
 
-@id 228
+@id 222
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/bic_A8822.d b/plugins/arm/v7/opdefs/A8822_bic.d
index f4746b9..f4746b9 100644
--- a/plugins/arm/v7/opdefs/bic_A8822.d
+++ b/plugins/arm/v7/opdefs/A8822_bic.d
diff --git a/plugins/arm/v7/opdefs/sxtab_A88230.d b/plugins/arm/v7/opdefs/A88230_sxtab.d
index ccd1859..138c0a5 100644
--- a/plugins/arm/v7/opdefs/sxtab_A88230.d
+++ b/plugins/arm/v7/opdefs/A88230_sxtab.d
@@ -23,7 +23,7 @@
 
 @title SXTAB
 
-@id 229
+@id 223
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/sxtab16_A88231.d b/plugins/arm/v7/opdefs/A88231_sxtab16.d
index f60a624..6fac4ba 100644
--- a/plugins/arm/v7/opdefs/sxtab16_A88231.d
+++ b/plugins/arm/v7/opdefs/A88231_sxtab16.d
@@ -23,7 +23,7 @@
 
 @title SXTAB16
 
-@id 230
+@id 224
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/sxtah_A88232.d b/plugins/arm/v7/opdefs/A88232_sxtah.d
index e1d4135..d2170b6 100644
--- a/plugins/arm/v7/opdefs/sxtah_A88232.d
+++ b/plugins/arm/v7/opdefs/A88232_sxtah.d
@@ -23,7 +23,7 @@
 
 @title SXTAH
 
-@id 231
+@id 225
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/sxtb_A88233.d b/plugins/arm/v7/opdefs/A88233_sxtb.d
index 99b43c0..84d7ed4 100644
--- a/plugins/arm/v7/opdefs/sxtb_A88233.d
+++ b/plugins/arm/v7/opdefs/A88233_sxtb.d
@@ -23,7 +23,7 @@
 
 @title SXTB
 
-@id 232
+@id 226
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/sxtb16_A88234.d b/plugins/arm/v7/opdefs/A88234_sxtb16.d
index fe9fb17..5f690be 100644
--- a/plugins/arm/v7/opdefs/sxtb16_A88234.d
+++ b/plugins/arm/v7/opdefs/A88234_sxtb16.d
@@ -23,7 +23,7 @@
 
 @title SXTB16
 
-@id 233
+@id 227
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/sxth_A88235.d b/plugins/arm/v7/opdefs/A88235_sxth.d
index 76e09d2..c75cdf3 100644
--- a/plugins/arm/v7/opdefs/sxth_A88235.d
+++ b/plugins/arm/v7/opdefs/A88235_sxth.d
@@ -23,7 +23,7 @@
 
 @title SXTH
 
-@id 234
+@id 228
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/teq_A88237.d b/plugins/arm/v7/opdefs/A88237_teq.d
index 9972918..148d76d 100644
--- a/plugins/arm/v7/opdefs/teq_A88237.d
+++ b/plugins/arm/v7/opdefs/A88237_teq.d
@@ -23,7 +23,7 @@
 
 @title TEQ (immediate)
 
-@id 236
+@id 229
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/teq_A88238.d b/plugins/arm/v7/opdefs/A88238_teq.d
index def4bc4..2fc99bb 100644
--- a/plugins/arm/v7/opdefs/teq_A88238.d
+++ b/plugins/arm/v7/opdefs/A88238_teq.d
@@ -23,7 +23,7 @@
 
 @title TEQ (register)
 
-@id 237
+@id 230
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/teq_A88239.d b/plugins/arm/v7/opdefs/A88239_teq.d
index 3c6ab33..806328e 100644
--- a/plugins/arm/v7/opdefs/teq_A88239.d
+++ b/plugins/arm/v7/opdefs/A88239_teq.d
@@ -23,7 +23,7 @@
 
 @title TEQ (register-shifted register)
 
-@id 238
+@id 231
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/bic_A8823.d b/plugins/arm/v7/opdefs/A8823_bic.d
index fb57338..fb57338 100644
--- a/plugins/arm/v7/opdefs/bic_A8823.d
+++ b/plugins/arm/v7/opdefs/A8823_bic.d
diff --git a/plugins/arm/v7/opdefs/tst_A88240.d b/plugins/arm/v7/opdefs/A88240_tst.d
index 125febc..d1258d4 100644
--- a/plugins/arm/v7/opdefs/tst_A88240.d
+++ b/plugins/arm/v7/opdefs/A88240_tst.d
@@ -23,7 +23,7 @@
 
 @title TST (immediate)
 
-@id 239
+@id 232
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/tst_A88241.d b/plugins/arm/v7/opdefs/A88241_tst.d
index 1be33f8..98e820e 100644
--- a/plugins/arm/v7/opdefs/tst_A88241.d
+++ b/plugins/arm/v7/opdefs/A88241_tst.d
@@ -23,7 +23,7 @@
 
 @title TST (register)
 
-@id 240
+@id 233
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/tst_A88242.d b/plugins/arm/v7/opdefs/A88242_tst.d
index 04bfdd2..ef1c4df 100644
--- a/plugins/arm/v7/opdefs/tst_A88242.d
+++ b/plugins/arm/v7/opdefs/A88242_tst.d
@@ -23,7 +23,7 @@
 
 @title TST (register-shifted register)
 
-@id 241
+@id 234
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/uadd16_A88243.d b/plugins/arm/v7/opdefs/A88243_uadd16.d
index ba9ad7a..3a220d2 100644
--- a/plugins/arm/v7/opdefs/uadd16_A88243.d
+++ b/plugins/arm/v7/opdefs/A88243_uadd16.d
@@ -23,7 +23,7 @@
 
 @title UADD16
 
-@id 242
+@id 235
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/uadd8_A88244.d b/plugins/arm/v7/opdefs/A88244_uadd8.d
index bf8e18d..a2d4a97 100644
--- a/plugins/arm/v7/opdefs/uadd8_A88244.d
+++ b/plugins/arm/v7/opdefs/A88244_uadd8.d
@@ -23,7 +23,7 @@
 
 @title UADD8
 
-@id 243
+@id 236
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/uasx_A88245.d b/plugins/arm/v7/opdefs/A88245_uasx.d
index b802f43..eca3303 100644
--- a/plugins/arm/v7/opdefs/uasx_A88245.d
+++ b/plugins/arm/v7/opdefs/A88245_uasx.d
@@ -23,7 +23,7 @@
 
 @title UASX
 
-@id 244
+@id 237
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/ubfx_A88246.d b/plugins/arm/v7/opdefs/A88246_ubfx.d
index 3fe25c7..cd39cb3 100644
--- a/plugins/arm/v7/opdefs/ubfx_A88246.d
+++ b/plugins/arm/v7/opdefs/A88246_ubfx.d
@@ -23,7 +23,7 @@
 
 @title UBFX
 
-@id 245
+@id 238
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/udf_A88247.d b/plugins/arm/v7/opdefs/A88247_udf.d
index 500e714..f6aeb3a 100644
--- a/plugins/arm/v7/opdefs/udf_A88247.d
+++ b/plugins/arm/v7/opdefs/A88247_udf.d
@@ -23,7 +23,7 @@
 
 @title UDF
 
-@id 246
+@id 239
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/udiv_A88248.d b/plugins/arm/v7/opdefs/A88248_udiv.d
index 27ef02b..b142ffb 100644
--- a/plugins/arm/v7/opdefs/udiv_A88248.d
+++ b/plugins/arm/v7/opdefs/A88248_udiv.d
@@ -23,7 +23,7 @@
 
 @title UDIV
 
-@id 247
+@id 240
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/uhadd16_A88249.d b/plugins/arm/v7/opdefs/A88249_uhadd16.d
index 379b0e9..4d220ae 100644
--- a/plugins/arm/v7/opdefs/uhadd16_A88249.d
+++ b/plugins/arm/v7/opdefs/A88249_uhadd16.d
@@ -23,7 +23,7 @@
 
 @title UHADD16
 
-@id 248
+@id 241
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/bkpt_A8824.d b/plugins/arm/v7/opdefs/A8824_bkpt.d
index e9c9f4b..e9c9f4b 100644
--- a/plugins/arm/v7/opdefs/bkpt_A8824.d
+++ b/plugins/arm/v7/opdefs/A8824_bkpt.d
diff --git a/plugins/arm/v7/opdefs/uhadd8_A88250.d b/plugins/arm/v7/opdefs/A88250_uhadd8.d
index 1f4a626..e28cb14 100644
--- a/plugins/arm/v7/opdefs/uhadd8_A88250.d
+++ b/plugins/arm/v7/opdefs/A88250_uhadd8.d
@@ -23,7 +23,7 @@
 
 @title UHADD8
 
-@id 249
+@id 242
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/uhasx_A88251.d b/plugins/arm/v7/opdefs/A88251_uhasx.d
index 148d120..6aa7d7e 100644
--- a/plugins/arm/v7/opdefs/uhasx_A88251.d
+++ b/plugins/arm/v7/opdefs/A88251_uhasx.d
@@ -23,7 +23,7 @@
 
 @title UHASX
 
-@id 250
+@id 243
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/uhsax_A88252.d b/plugins/arm/v7/opdefs/A88252_uhsax.d
index eb7dd83..6639e6c 100644
--- a/plugins/arm/v7/opdefs/uhsax_A88252.d
+++ b/plugins/arm/v7/opdefs/A88252_uhsax.d
@@ -23,7 +23,7 @@
 
 @title UHSAX
 
-@id 251
+@id 244
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/uhsub16_A88253.d b/plugins/arm/v7/opdefs/A88253_uhsub16.d
index f526389..c64a424 100644
--- a/plugins/arm/v7/opdefs/uhsub16_A88253.d
+++ b/plugins/arm/v7/opdefs/A88253_uhsub16.d
@@ -23,7 +23,7 @@
 
 @title UHSUB16
 
-@id 252
+@id 245
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/uhsub8_A88254.d b/plugins/arm/v7/opdefs/A88254_uhsub8.d
index a2d27ac..1e1d7d1 100644
--- a/plugins/arm/v7/opdefs/uhsub8_A88254.d
+++ b/plugins/arm/v7/opdefs/A88254_uhsub8.d
@@ -23,7 +23,7 @@
 
 @title UHSUB8
 
-@id 253
+@id 246
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/umaal_A88255.d b/plugins/arm/v7/opdefs/A88255_umaal.d
index 6e5f7e9..69623a2 100644
--- a/plugins/arm/v7/opdefs/umaal_A88255.d
+++ b/plugins/arm/v7/opdefs/A88255_umaal.d
@@ -23,7 +23,7 @@
 
 @title UMAAL
 
-@id 254
+@id 247
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/umlal_A88256.d b/plugins/arm/v7/opdefs/A88256_umlal.d
index 0eccc37..64d7cc1 100644
--- a/plugins/arm/v7/opdefs/umlal_A88256.d
+++ b/plugins/arm/v7/opdefs/A88256_umlal.d
@@ -23,7 +23,7 @@
 
 @title UMLAL
 
-@id 255
+@id 248
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/umull_A88257.d b/plugins/arm/v7/opdefs/A88257_umull.d
index b016016..3ded23c 100644
--- a/plugins/arm/v7/opdefs/umull_A88257.d
+++ b/plugins/arm/v7/opdefs/A88257_umull.d
@@ -23,7 +23,7 @@
 
 @title UMULL
 
-@id 256
+@id 249
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/uqadd16_A88258.d b/plugins/arm/v7/opdefs/A88258_uqadd16.d
index ed4c130..bc37e8c 100644
--- a/plugins/arm/v7/opdefs/uqadd16_A88258.d
+++ b/plugins/arm/v7/opdefs/A88258_uqadd16.d
@@ -23,7 +23,7 @@
 
 @title UQADD16
 
-@id 257
+@id 250
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/uqadd8_A88259.d b/plugins/arm/v7/opdefs/A88259_uqadd8.d
index ca6054d..349b1b8 100644
--- a/plugins/arm/v7/opdefs/uqadd8_A88259.d
+++ b/plugins/arm/v7/opdefs/A88259_uqadd8.d
@@ -23,7 +23,7 @@
 
 @title UQADD8
 
-@id 258
+@id 251
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/bl_A8825.d b/plugins/arm/v7/opdefs/A8825_bl.d
index 221bbc5..221bbc5 100644
--- a/plugins/arm/v7/opdefs/bl_A8825.d
+++ b/plugins/arm/v7/opdefs/A8825_bl.d
diff --git a/plugins/arm/v7/opdefs/uqasx_A88260.d b/plugins/arm/v7/opdefs/A88260_uqasx.d
index 12930a2..4733d58 100644
--- a/plugins/arm/v7/opdefs/uqasx_A88260.d
+++ b/plugins/arm/v7/opdefs/A88260_uqasx.d
@@ -23,7 +23,7 @@
 
 @title UQASX
 
-@id 259
+@id 252
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/uqsax_A88261.d b/plugins/arm/v7/opdefs/A88261_uqsax.d
index d39f0f4..92bef77 100644
--- a/plugins/arm/v7/opdefs/uqsax_A88261.d
+++ b/plugins/arm/v7/opdefs/A88261_uqsax.d
@@ -23,7 +23,7 @@
 
 @title UQSAX
 
-@id 260
+@id 253
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/uqsub16_A88262.d b/plugins/arm/v7/opdefs/A88262_uqsub16.d
index cd77b0a..9b9611d 100644
--- a/plugins/arm/v7/opdefs/uqsub16_A88262.d
+++ b/plugins/arm/v7/opdefs/A88262_uqsub16.d
@@ -23,7 +23,7 @@
 
 @title UQSUB16
 
-@id 261
+@id 254
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/uqsub8_A88263.d b/plugins/arm/v7/opdefs/A88263_uqsub8.d
index aa42724..ea041bc 100644
--- a/plugins/arm/v7/opdefs/uqsub8_A88263.d
+++ b/plugins/arm/v7/opdefs/A88263_uqsub8.d
@@ -23,7 +23,7 @@
 
 @title UQSUB8
 
-@id 262
+@id 255
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/usad8_A88264.d b/plugins/arm/v7/opdefs/A88264_usad8.d
index 286ba2c..d804b6f 100644
--- a/plugins/arm/v7/opdefs/usad8_A88264.d
+++ b/plugins/arm/v7/opdefs/A88264_usad8.d
@@ -23,7 +23,7 @@
 
 @title USAD8
 
-@id 263
+@id 256
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/usada8_A88265.d b/plugins/arm/v7/opdefs/A88265_usada8.d
index bce78eb..faace0c 100644
--- a/plugins/arm/v7/opdefs/usada8_A88265.d
+++ b/plugins/arm/v7/opdefs/A88265_usada8.d
@@ -23,7 +23,7 @@
 
 @title USADA8
 
-@id 264
+@id 257
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/usat_A88266.d b/plugins/arm/v7/opdefs/A88266_usat.d
index d2a2819..7275113 100644
--- a/plugins/arm/v7/opdefs/usat_A88266.d
+++ b/plugins/arm/v7/opdefs/A88266_usat.d
@@ -23,7 +23,7 @@
 
 @title USAT
 
-@id 265
+@id 258
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/usat16_A88267.d b/plugins/arm/v7/opdefs/A88267_usat16.d
index d36f52f..eaaaa3f 100644
--- a/plugins/arm/v7/opdefs/usat16_A88267.d
+++ b/plugins/arm/v7/opdefs/A88267_usat16.d
@@ -23,7 +23,7 @@
 
 @title USAT16
 
-@id 266
+@id 259
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/usax_A88268.d b/plugins/arm/v7/opdefs/A88268_usax.d
index d85083c..89731f1 100644
--- a/plugins/arm/v7/opdefs/usax_A88268.d
+++ b/plugins/arm/v7/opdefs/A88268_usax.d
@@ -23,7 +23,7 @@
 
 @title USAX
 
-@id 267
+@id 260
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/usub16_A88269.d b/plugins/arm/v7/opdefs/A88269_usub16.d
index 6a9a2f5..192d7bf 100644
--- a/plugins/arm/v7/opdefs/usub16_A88269.d
+++ b/plugins/arm/v7/opdefs/A88269_usub16.d
@@ -23,7 +23,7 @@
 
 @title USUB16
 
-@id 268
+@id 261
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/blx_A8826.d b/plugins/arm/v7/opdefs/A8826_blx.d
index 2c975d3..2c975d3 100644
--- a/plugins/arm/v7/opdefs/blx_A8826.d
+++ b/plugins/arm/v7/opdefs/A8826_blx.d
diff --git a/plugins/arm/v7/opdefs/usub8_A88270.d b/plugins/arm/v7/opdefs/A88270_usub8.d
index 2987469..a2e921e 100644
--- a/plugins/arm/v7/opdefs/usub8_A88270.d
+++ b/plugins/arm/v7/opdefs/A88270_usub8.d
@@ -23,7 +23,7 @@
 
 @title USUB8
 
-@id 269
+@id 262
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/uxtab_A88271.d b/plugins/arm/v7/opdefs/A88271_uxtab.d
index 104d379..f84b7d4 100644
--- a/plugins/arm/v7/opdefs/uxtab_A88271.d
+++ b/plugins/arm/v7/opdefs/A88271_uxtab.d
@@ -23,7 +23,7 @@
 
 @title UXTAB
 
-@id 270
+@id 263
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/uxtab16_A88272.d b/plugins/arm/v7/opdefs/A88272_uxtab16.d
index 0cbc980..ac2e47d 100644
--- a/plugins/arm/v7/opdefs/uxtab16_A88272.d
+++ b/plugins/arm/v7/opdefs/A88272_uxtab16.d
@@ -23,7 +23,7 @@
 
 @title UXTAB16
 
-@id 271
+@id 264
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/uxtah_A88273.d b/plugins/arm/v7/opdefs/A88273_uxtah.d
index 9e454ac..9a30d32 100644
--- a/plugins/arm/v7/opdefs/uxtah_A88273.d
+++ b/plugins/arm/v7/opdefs/A88273_uxtah.d
@@ -23,7 +23,7 @@
 
 @title UXTAH
 
-@id 272
+@id 265
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/uxtb_A88274.d b/plugins/arm/v7/opdefs/A88274_uxtb.d
index 0ac40b6..d2a46ae 100644
--- a/plugins/arm/v7/opdefs/uxtb_A88274.d
+++ b/plugins/arm/v7/opdefs/A88274_uxtb.d
@@ -23,7 +23,7 @@
 
 @title UXTB
 
-@id 273
+@id 266
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/uxtb16_A88275.d b/plugins/arm/v7/opdefs/A88275_uxtb16.d
index 5d67eb8..f1b3384 100644
--- a/plugins/arm/v7/opdefs/uxtb16_A88275.d
+++ b/plugins/arm/v7/opdefs/A88275_uxtb16.d
@@ -23,7 +23,7 @@
 
 @title UXTB16
 
-@id 274
+@id 267
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/uxth_A88276.d b/plugins/arm/v7/opdefs/A88276_uxth.d
index 3ebf512..90c3310 100644
--- a/plugins/arm/v7/opdefs/uxth_A88276.d
+++ b/plugins/arm/v7/opdefs/A88276_uxth.d
@@ -23,7 +23,7 @@
 
 @title UXTH
 
-@id 275
+@id 268
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/bx_A8827.d b/plugins/arm/v7/opdefs/A8827_bx.d
index 64ad628..64ad628 100644
--- a/plugins/arm/v7/opdefs/bx_A8827.d
+++ b/plugins/arm/v7/opdefs/A8827_bx.d
diff --git a/plugins/arm/v7/opdefs/bxj_A8828.d b/plugins/arm/v7/opdefs/A8828_bxj.d
index 7c6ddb5..7c6ddb5 100644
--- a/plugins/arm/v7/opdefs/bxj_A8828.d
+++ b/plugins/arm/v7/opdefs/A8828_bxj.d
diff --git a/plugins/arm/v7/opdefs/cb_A8829.d b/plugins/arm/v7/opdefs/A8829_cb.d
index 5e004b7..5e004b7 100644
--- a/plugins/arm/v7/opdefs/cb_A8829.d
+++ b/plugins/arm/v7/opdefs/A8829_cb.d
diff --git a/plugins/arm/v7/opdefs/adc_A882.d b/plugins/arm/v7/opdefs/A882_adc.d
index aaca002..aaca002 100644
--- a/plugins/arm/v7/opdefs/adc_A882.d
+++ b/plugins/arm/v7/opdefs/A882_adc.d
diff --git a/plugins/arm/v7/opdefs/cdp_A8830.d b/plugins/arm/v7/opdefs/A8830_cdp.d
index 32fc2f1..32fc2f1 100644
--- a/plugins/arm/v7/opdefs/cdp_A8830.d
+++ b/plugins/arm/v7/opdefs/A8830_cdp.d
diff --git a/plugins/arm/v7/opdefs/clrex_A8832.d b/plugins/arm/v7/opdefs/A8832_clrex.d
index 5edfb58..5edfb58 100644
--- a/plugins/arm/v7/opdefs/clrex_A8832.d
+++ b/plugins/arm/v7/opdefs/A8832_clrex.d
diff --git a/plugins/arm/v7/opdefs/clz_A8833.d b/plugins/arm/v7/opdefs/A8833_clz.d
index 7cbb51c..7cbb51c 100644
--- a/plugins/arm/v7/opdefs/clz_A8833.d
+++ b/plugins/arm/v7/opdefs/A8833_clz.d
diff --git a/plugins/arm/v7/opdefs/cmn_A8834.d b/plugins/arm/v7/opdefs/A8834_cmn.d
index 45462c7..45462c7 100644
--- a/plugins/arm/v7/opdefs/cmn_A8834.d
+++ b/plugins/arm/v7/opdefs/A8834_cmn.d
diff --git a/plugins/arm/v7/opdefs/cmn_A8835.d b/plugins/arm/v7/opdefs/A8835_cmn.d
index 55c281c..55c281c 100644
--- a/plugins/arm/v7/opdefs/cmn_A8835.d
+++ b/plugins/arm/v7/opdefs/A8835_cmn.d
diff --git a/plugins/arm/v7/opdefs/cmn_A8836.d b/plugins/arm/v7/opdefs/A8836_cmn.d
index e1052a8..e1052a8 100644
--- a/plugins/arm/v7/opdefs/cmn_A8836.d
+++ b/plugins/arm/v7/opdefs/A8836_cmn.d
diff --git a/plugins/arm/v7/opdefs/cmp_A8837.d b/plugins/arm/v7/opdefs/A8837_cmp.d
index 261467b..261467b 100644
--- a/plugins/arm/v7/opdefs/cmp_A8837.d
+++ b/plugins/arm/v7/opdefs/A8837_cmp.d
diff --git a/plugins/arm/v7/opdefs/cmp_A8838.d b/plugins/arm/v7/opdefs/A8838_cmp.d
index 401e4ac..401e4ac 100644
--- a/plugins/arm/v7/opdefs/cmp_A8838.d
+++ b/plugins/arm/v7/opdefs/A8838_cmp.d
diff --git a/plugins/arm/v7/opdefs/cmp_A8839.d b/plugins/arm/v7/opdefs/A8839_cmp.d
index 6bdafb3..6bdafb3 100644
--- a/plugins/arm/v7/opdefs/cmp_A8839.d
+++ b/plugins/arm/v7/opdefs/A8839_cmp.d
diff --git a/plugins/arm/v7/opdefs/adc_A883.d b/plugins/arm/v7/opdefs/A883_adc.d
index 0270402..0270402 100644
--- a/plugins/arm/v7/opdefs/adc_A883.d
+++ b/plugins/arm/v7/opdefs/A883_adc.d
diff --git a/plugins/arm/v7/opdefs/wfe_A88424.d b/plugins/arm/v7/opdefs/A88424_wfe.d
index dc0f72e..6c245a2 100644
--- a/plugins/arm/v7/opdefs/wfe_A88424.d
+++ b/plugins/arm/v7/opdefs/A88424_wfe.d
@@ -23,7 +23,7 @@
 
 @title WFE
 
-@id 423
+@id 349
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/wfi_A88425.d b/plugins/arm/v7/opdefs/A88425_wfi.d
index 961c293..ef3c73b 100644
--- a/plugins/arm/v7/opdefs/wfi_A88425.d
+++ b/plugins/arm/v7/opdefs/A88425_wfi.d
@@ -23,7 +23,7 @@
 
 @title WFI
 
-@id 424
+@id 350
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/yield_A88426.d b/plugins/arm/v7/opdefs/A88426_yield.d
index 66e8f39..f782682 100644
--- a/plugins/arm/v7/opdefs/yield_A88426.d
+++ b/plugins/arm/v7/opdefs/A88426_yield.d
@@ -23,7 +23,7 @@
 
 @title YIELD
 
-@id 425
+@id 351
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/dbg_A8842.d b/plugins/arm/v7/opdefs/A8842_dbg.d
index d053ca3..d053ca3 100644
--- a/plugins/arm/v7/opdefs/dbg_A8842.d
+++ b/plugins/arm/v7/opdefs/A8842_dbg.d
diff --git a/plugins/arm/v7/opdefs/dmb_A8843.d b/plugins/arm/v7/opdefs/A8843_dmb.d
index b8d9717..b8d9717 100644
--- a/plugins/arm/v7/opdefs/dmb_A8843.d
+++ b/plugins/arm/v7/opdefs/A8843_dmb.d
diff --git a/plugins/arm/v7/opdefs/dsb_A8844.d b/plugins/arm/v7/opdefs/A8844_dsb.d
index e8ede64..e8ede64 100644
--- a/plugins/arm/v7/opdefs/dsb_A8844.d
+++ b/plugins/arm/v7/opdefs/A8844_dsb.d
diff --git a/plugins/arm/v7/opdefs/eor_A8846.d b/plugins/arm/v7/opdefs/A8846_eor.d
index dfafa9b..dfafa9b 100644
--- a/plugins/arm/v7/opdefs/eor_A8846.d
+++ b/plugins/arm/v7/opdefs/A8846_eor.d
diff --git a/plugins/arm/v7/opdefs/eor_A8847.d b/plugins/arm/v7/opdefs/A8847_eor.d
index f6e3387..f6e3387 100644
--- a/plugins/arm/v7/opdefs/eor_A8847.d
+++ b/plugins/arm/v7/opdefs/A8847_eor.d
diff --git a/plugins/arm/v7/opdefs/eor_A8848.d b/plugins/arm/v7/opdefs/A8848_eor.d
index 94f0e92..94f0e92 100644
--- a/plugins/arm/v7/opdefs/eor_A8848.d
+++ b/plugins/arm/v7/opdefs/A8848_eor.d
diff --git a/plugins/arm/v7/opdefs/add_A884.d b/plugins/arm/v7/opdefs/A884_add.d
index c35685f..c35685f 100644
--- a/plugins/arm/v7/opdefs/add_A884.d
+++ b/plugins/arm/v7/opdefs/A884_add.d
diff --git a/plugins/arm/v7/opdefs/it_A8854.d b/plugins/arm/v7/opdefs/A8854_it.d
index 42ee4c9..5d0fe36 100644
--- a/plugins/arm/v7/opdefs/it_A8854.d
+++ b/plugins/arm/v7/opdefs/A8854_it.d
@@ -23,7 +23,7 @@
 
 @title IT
 
-@id 53
+@id 48
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/ldc_A8855.d b/plugins/arm/v7/opdefs/A8855_ldc.d
index 96cf4a5..958adb1 100644
--- a/plugins/arm/v7/opdefs/ldc_A8855.d
+++ b/plugins/arm/v7/opdefs/A8855_ldc.d
@@ -23,7 +23,7 @@
 
 @title LDC, LDC2 (immediate)
 
-@id 54
+@id 49
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/ldc_A8856.d b/plugins/arm/v7/opdefs/A8856_ldc.d
index 4731ff0..3cead5c 100644
--- a/plugins/arm/v7/opdefs/ldc_A8856.d
+++ b/plugins/arm/v7/opdefs/A8856_ldc.d
@@ -23,7 +23,7 @@
 
 @title LDC, LDC2 (literal)
 
-@id 55
+@id 50
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/ldm_A8857.d b/plugins/arm/v7/opdefs/A8857_ldm.d
index e7733e0..817a2a2 100644
--- a/plugins/arm/v7/opdefs/ldm_A8857.d
+++ b/plugins/arm/v7/opdefs/A8857_ldm.d
@@ -23,7 +23,7 @@
 
 @title LDM/LDMIA/LDMFD (Thumb)
 
-@id 56
+@id 51
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/ldm_A8858.d b/plugins/arm/v7/opdefs/A8858_ldm.d
index 8b41183..a5670e8 100644
--- a/plugins/arm/v7/opdefs/ldm_A8858.d
+++ b/plugins/arm/v7/opdefs/A8858_ldm.d
@@ -23,7 +23,7 @@
 
 @title LDM/LDMIA/LDMFD (ARM)
 
-@id 57
+@id 52
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/ldmda_A8859.d b/plugins/arm/v7/opdefs/A8859_ldmda.d
index 6eb27d1..cc8ee05 100644
--- a/plugins/arm/v7/opdefs/ldmda_A8859.d
+++ b/plugins/arm/v7/opdefs/A8859_ldmda.d
@@ -23,7 +23,7 @@
 
 @title LDMDA/LDMFA
 
-@id 58
+@id 53
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/add_A885.d b/plugins/arm/v7/opdefs/A885_add.d
index 87b92a6..87b92a6 100644
--- a/plugins/arm/v7/opdefs/add_A885.d
+++ b/plugins/arm/v7/opdefs/A885_add.d
diff --git a/plugins/arm/v7/opdefs/ldmdb_A8860.d b/plugins/arm/v7/opdefs/A8860_ldmdb.d
index a66d2a4..ccc409b 100644
--- a/plugins/arm/v7/opdefs/ldmdb_A8860.d
+++ b/plugins/arm/v7/opdefs/A8860_ldmdb.d
@@ -23,7 +23,7 @@
 
 @title LDMDB/LDMEA
 
-@id 59
+@id 54
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/ldmib_A8861.d b/plugins/arm/v7/opdefs/A8861_ldmib.d
index fa12e8a..3f76523 100644
--- a/plugins/arm/v7/opdefs/ldmib_A8861.d
+++ b/plugins/arm/v7/opdefs/A8861_ldmib.d
@@ -23,7 +23,7 @@
 
 @title LDMIB/LDMED
 
-@id 60
+@id 55
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/ldr_A8862.d b/plugins/arm/v7/opdefs/A8862_ldr.d
index 9771bae..2f8dd08 100644
--- a/plugins/arm/v7/opdefs/ldr_A8862.d
+++ b/plugins/arm/v7/opdefs/A8862_ldr.d
@@ -23,7 +23,7 @@
 
 @title LDR (immediate, Thumb)
 
-@id 61
+@id 56
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/ldr_A8863.d b/plugins/arm/v7/opdefs/A8863_ldr.d
index e2a443c..9842cc9 100644
--- a/plugins/arm/v7/opdefs/ldr_A8863.d
+++ b/plugins/arm/v7/opdefs/A8863_ldr.d
@@ -23,7 +23,7 @@
 
 @title LDR (immediate, ARM)
 
-@id 62
+@id 57
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/ldr_A8864.d b/plugins/arm/v7/opdefs/A8864_ldr.d
index fc19f13..c10421f 100644
--- a/plugins/arm/v7/opdefs/ldr_A8864.d
+++ b/plugins/arm/v7/opdefs/A8864_ldr.d
@@ -23,7 +23,7 @@
 
 @title LDR (literal)
 
-@id 63
+@id 58
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/ldr_A8865.d b/plugins/arm/v7/opdefs/A8865_ldr.d
index 8851ea2..a810586 100644
--- a/plugins/arm/v7/opdefs/ldr_A8865.d
+++ b/plugins/arm/v7/opdefs/A8865_ldr.d
@@ -23,7 +23,7 @@
 
 @title LDR (register, Thumb)
 
-@id 64
+@id 59
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/ldr_A8866.d b/plugins/arm/v7/opdefs/A8866_ldr.d
index e676fec..6ad2086 100644
--- a/plugins/arm/v7/opdefs/ldr_A8866.d
+++ b/plugins/arm/v7/opdefs/A8866_ldr.d
@@ -23,7 +23,7 @@
 
 @title LDR (register, ARM)
 
-@id 65
+@id 60
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/ldrb_A8867.d b/plugins/arm/v7/opdefs/A8867_ldrb.d
index a5c1a35..0155850 100644
--- a/plugins/arm/v7/opdefs/ldrb_A8867.d
+++ b/plugins/arm/v7/opdefs/A8867_ldrb.d
@@ -23,7 +23,7 @@
 
 @title LDRB (immediate, Thumb)
 
-@id 66
+@id 61
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/ldrb_A8868.d b/plugins/arm/v7/opdefs/A8868_ldrb.d
index 67f122c..6c19871 100644
--- a/plugins/arm/v7/opdefs/ldrb_A8868.d
+++ b/plugins/arm/v7/opdefs/A8868_ldrb.d
@@ -23,7 +23,7 @@
 
 @title LDRB (immediate, ARM)
 
-@id 67
+@id 62
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/ldrb_A8869.d b/plugins/arm/v7/opdefs/A8869_ldrb.d
index defb999..ca9863d 100644
--- a/plugins/arm/v7/opdefs/ldrb_A8869.d
+++ b/plugins/arm/v7/opdefs/A8869_ldrb.d
@@ -23,7 +23,7 @@
 
 @title LDRB (literal)
 
-@id 68
+@id 63
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/add_A886.d b/plugins/arm/v7/opdefs/A886_add.d
index 856272e..856272e 100644
--- a/plugins/arm/v7/opdefs/add_A886.d
+++ b/plugins/arm/v7/opdefs/A886_add.d
diff --git a/plugins/arm/v7/opdefs/ldrb_A8870.d b/plugins/arm/v7/opdefs/A8870_ldrb.d
index b99d19b..c20c8cc 100644
--- a/plugins/arm/v7/opdefs/ldrb_A8870.d
+++ b/plugins/arm/v7/opdefs/A8870_ldrb.d
@@ -23,7 +23,7 @@
 
 @title LDRB (register)
 
-@id 69
+@id 64
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/ldrbt_A8871.d b/plugins/arm/v7/opdefs/A8871_ldrbt.d
index fdd9176..5aacaf1 100644
--- a/plugins/arm/v7/opdefs/ldrbt_A8871.d
+++ b/plugins/arm/v7/opdefs/A8871_ldrbt.d
@@ -23,7 +23,7 @@
 
 @title LDRBT
 
-@id 70
+@id 65
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/ldrd_A8872.d b/plugins/arm/v7/opdefs/A8872_ldrd.d
index 752f956..e27a114 100644
--- a/plugins/arm/v7/opdefs/ldrd_A8872.d
+++ b/plugins/arm/v7/opdefs/A8872_ldrd.d
@@ -23,7 +23,7 @@
 
 @title LDRD (immediate)
 
-@id 71
+@id 66
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/ldrd_A8873.d b/plugins/arm/v7/opdefs/A8873_ldrd.d
index 031fb31..d3d44c3 100644
--- a/plugins/arm/v7/opdefs/ldrd_A8873.d
+++ b/plugins/arm/v7/opdefs/A8873_ldrd.d
@@ -23,7 +23,7 @@
 
 @title LDRD (literal)
 
-@id 72
+@id 67
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/ldrd_A8874.d b/plugins/arm/v7/opdefs/A8874_ldrd.d
index c35f2cc..e48844d 100644
--- a/plugins/arm/v7/opdefs/ldrd_A8874.d
+++ b/plugins/arm/v7/opdefs/A8874_ldrd.d
@@ -23,7 +23,7 @@
 
 @title LDRD (register)
 
-@id 73
+@id 68
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/ldrex_A8875.d b/plugins/arm/v7/opdefs/A8875_ldrex.d
index af19077..39c708c 100644
--- a/plugins/arm/v7/opdefs/ldrex_A8875.d
+++ b/plugins/arm/v7/opdefs/A8875_ldrex.d
@@ -23,7 +23,7 @@
 
 @title LDREX
 
-@id 74
+@id 69
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/ldrexb_A8876.d b/plugins/arm/v7/opdefs/A8876_ldrexb.d
index 39b07b3..4a00839 100644
--- a/plugins/arm/v7/opdefs/ldrexb_A8876.d
+++ b/plugins/arm/v7/opdefs/A8876_ldrexb.d
@@ -23,7 +23,7 @@
 
 @title LDREXB
 
-@id 75
+@id 70
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/ldrexd_A8877.d b/plugins/arm/v7/opdefs/A8877_ldrexd.d
index 232f4fa..44a6984 100644
--- a/plugins/arm/v7/opdefs/ldrexd_A8877.d
+++ b/plugins/arm/v7/opdefs/A8877_ldrexd.d
@@ -23,7 +23,7 @@
 
 @title LDREXD
 
-@id 76
+@id 71
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/ldrexh_A8878.d b/plugins/arm/v7/opdefs/A8878_ldrexh.d
index ac124f5..8687ded 100644
--- a/plugins/arm/v7/opdefs/ldrexh_A8878.d
+++ b/plugins/arm/v7/opdefs/A8878_ldrexh.d
@@ -23,7 +23,7 @@
 
 @title LDREXH
 
-@id 77
+@id 72
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/ldrh_A8879.d b/plugins/arm/v7/opdefs/A8879_ldrh.d
index 674a7d4..2fcbd0c 100644
--- a/plugins/arm/v7/opdefs/ldrh_A8879.d
+++ b/plugins/arm/v7/opdefs/A8879_ldrh.d
@@ -23,7 +23,7 @@
 
 @title LDRH (immediate, Thumb)
 
-@id 78
+@id 73
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/add_A887.d b/plugins/arm/v7/opdefs/A887_add.d
index 6105f18..6105f18 100644
--- a/plugins/arm/v7/opdefs/add_A887.d
+++ b/plugins/arm/v7/opdefs/A887_add.d
diff --git a/plugins/arm/v7/opdefs/ldrh_A8880.d b/plugins/arm/v7/opdefs/A8880_ldrh.d
index 7f7f1f7..a517a23 100644
--- a/plugins/arm/v7/opdefs/ldrh_A8880.d
+++ b/plugins/arm/v7/opdefs/A8880_ldrh.d
@@ -23,7 +23,7 @@
 
 @title LDRH (immediate, ARM)
 
-@id 79
+@id 74
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/ldrh_A8881.d b/plugins/arm/v7/opdefs/A8881_ldrh.d
index 43346e9..000974f 100644
--- a/plugins/arm/v7/opdefs/ldrh_A8881.d
+++ b/plugins/arm/v7/opdefs/A8881_ldrh.d
@@ -23,7 +23,7 @@
 
 @title LDRH (literal)
 
-@id 80
+@id 75
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/ldrh_A8882.d b/plugins/arm/v7/opdefs/A8882_ldrh.d
index 6f9fb73..9697112 100644
--- a/plugins/arm/v7/opdefs/ldrh_A8882.d
+++ b/plugins/arm/v7/opdefs/A8882_ldrh.d
@@ -23,7 +23,7 @@
 
 @title LDRH (register)
 
-@id 81
+@id 76
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/ldrht_A8883.d b/plugins/arm/v7/opdefs/A8883_ldrht.d
index 46bd025..e02c949 100644
--- a/plugins/arm/v7/opdefs/ldrht_A8883.d
+++ b/plugins/arm/v7/opdefs/A8883_ldrht.d
@@ -23,7 +23,7 @@
 
 @title LDRHT
 
-@id 82
+@id 77
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/ldrsb_A8884.d b/plugins/arm/v7/opdefs/A8884_ldrsb.d
index 828918f..bacfa6a 100644
--- a/plugins/arm/v7/opdefs/ldrsb_A8884.d
+++ b/plugins/arm/v7/opdefs/A8884_ldrsb.d
@@ -23,7 +23,7 @@
 
 @title LDRSB (immediate)
 
-@id 83
+@id 78
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/ldrsb_A8885.d b/plugins/arm/v7/opdefs/A8885_ldrsb.d
index 5d5c1c4..6ea8617 100644
--- a/plugins/arm/v7/opdefs/ldrsb_A8885.d
+++ b/plugins/arm/v7/opdefs/A8885_ldrsb.d
@@ -23,7 +23,7 @@
 
 @title LDRSB (literal)
 
-@id 84
+@id 79
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/ldrsb_A8886.d b/plugins/arm/v7/opdefs/A8886_ldrsb.d
index 9ce942b..1dbd651 100644
--- a/plugins/arm/v7/opdefs/ldrsb_A8886.d
+++ b/plugins/arm/v7/opdefs/A8886_ldrsb.d
@@ -23,7 +23,7 @@
 
 @title LDRSB (register)
 
-@id 85
+@id 80
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/ldrsbt_A8887.d b/plugins/arm/v7/opdefs/A8887_ldrsbt.d
index 181739c..fc145ac 100644
--- a/plugins/arm/v7/opdefs/ldrsbt_A8887.d
+++ b/plugins/arm/v7/opdefs/A8887_ldrsbt.d
@@ -23,7 +23,7 @@
 
 @title LDRSBT
 
-@id 86
+@id 81
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/ldrsh_A8888.d b/plugins/arm/v7/opdefs/A8888_ldrsh.d
index 3d9c2a3..b908ec1 100644
--- a/plugins/arm/v7/opdefs/ldrsh_A8888.d
+++ b/plugins/arm/v7/opdefs/A8888_ldrsh.d
@@ -23,7 +23,7 @@
 
 @title LDRSH (immediate)
 
-@id 87
+@id 82
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/ldrsh_A8889.d b/plugins/arm/v7/opdefs/A8889_ldrsh.d
index d6a6197..a3ca43f 100644
--- a/plugins/arm/v7/opdefs/ldrsh_A8889.d
+++ b/plugins/arm/v7/opdefs/A8889_ldrsh.d
@@ -23,7 +23,7 @@
 
 @title LDRSH (literal)
 
-@id 88
+@id 83
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/add_A888.d b/plugins/arm/v7/opdefs/A888_add.d
index 8fd6078..8fd6078 100644
--- a/plugins/arm/v7/opdefs/add_A888.d
+++ b/plugins/arm/v7/opdefs/A888_add.d
diff --git a/plugins/arm/v7/opdefs/ldrsh_A8890.d b/plugins/arm/v7/opdefs/A8890_ldrsh.d
index 9269ca0..3efd231 100644
--- a/plugins/arm/v7/opdefs/ldrsh_A8890.d
+++ b/plugins/arm/v7/opdefs/A8890_ldrsh.d
@@ -23,7 +23,7 @@
 
 @title LDRSH (register)
 
-@id 89
+@id 84
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/ldrsht_A8891.d b/plugins/arm/v7/opdefs/A8891_ldrsht.d
index b1402f7..ffeb9fd 100644
--- a/plugins/arm/v7/opdefs/ldrsht_A8891.d
+++ b/plugins/arm/v7/opdefs/A8891_ldrsht.d
@@ -23,7 +23,7 @@
 
 @title LDRSHT
 
-@id 90
+@id 85
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/ldrt_A8892.d b/plugins/arm/v7/opdefs/A8892_ldrt.d
index 23d1d6f..86699de 100644
--- a/plugins/arm/v7/opdefs/ldrt_A8892.d
+++ b/plugins/arm/v7/opdefs/A8892_ldrt.d
@@ -23,7 +23,7 @@
 
 @title LDRT
 
-@id 91
+@id 86
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/lsl_A8894.d b/plugins/arm/v7/opdefs/A8894_lsl.d
index b4689bb..b8cde63 100644
--- a/plugins/arm/v7/opdefs/lsl_A8894.d
+++ b/plugins/arm/v7/opdefs/A8894_lsl.d
@@ -23,7 +23,7 @@
 
 @title LSL (immediate)
 
-@id 93
+@id 88
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/lsl_A8895.d b/plugins/arm/v7/opdefs/A8895_lsl.d
index 59bbb91..3cdc75d 100644
--- a/plugins/arm/v7/opdefs/lsl_A8895.d
+++ b/plugins/arm/v7/opdefs/A8895_lsl.d
@@ -23,7 +23,7 @@
 
 @title LSL (register)
 
-@id 94
+@id 89
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/lsr_A8896.d b/plugins/arm/v7/opdefs/A8896_lsr.d
index 07f12da..2efcbed 100644
--- a/plugins/arm/v7/opdefs/lsr_A8896.d
+++ b/plugins/arm/v7/opdefs/A8896_lsr.d
@@ -23,7 +23,7 @@
 
 @title LSR (immediate)
 
-@id 95
+@id 90
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/lsr_A8897.d b/plugins/arm/v7/opdefs/A8897_lsr.d
index fa0b70f..6e05dd4 100644
--- a/plugins/arm/v7/opdefs/lsr_A8897.d
+++ b/plugins/arm/v7/opdefs/A8897_lsr.d
@@ -23,7 +23,7 @@
 
 @title LSR (register)
 
-@id 96
+@id 91
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/mcr_A8898.d b/plugins/arm/v7/opdefs/A8898_mcr.d
index 8a2252b..06f5aa2 100644
--- a/plugins/arm/v7/opdefs/mcr_A8898.d
+++ b/plugins/arm/v7/opdefs/A8898_mcr.d
@@ -23,7 +23,7 @@
 
 @title MCR, MCR2
 
-@id 97
+@id 92
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/mcrr_A8899.d b/plugins/arm/v7/opdefs/A8899_mcrr.d
index b500446..6177a4c 100644
--- a/plugins/arm/v7/opdefs/mcrr_A8899.d
+++ b/plugins/arm/v7/opdefs/A8899_mcrr.d
@@ -23,7 +23,7 @@
 
 @title MCRR, MCRR2
 
-@id 98
+@id 93
 
 @desc {
 
diff --git a/plugins/arm/v7/opdefs/add_A889.d b/plugins/arm/v7/opdefs/A889_add.d
index 834de50..834de50 100644
--- a/plugins/arm/v7/opdefs/add_A889.d
+++ b/plugins/arm/v7/opdefs/A889_add.d
diff --git a/plugins/arm/v7/opdefs/B9310_msr.d b/plugins/arm/v7/opdefs/B9310_msr.d
new file mode 100644
index 0000000..79c569a
--- /dev/null
+++ b/plugins/arm/v7/opdefs/B9310_msr.d
@@ -0,0 +1,81 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2017 Cyrille Bagard
+ *
+ *  This file is part of Chrysalide.
+ *
+ *  Chrysalide is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  Chrysalide is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Chrysalide.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title MSR (Banked register)
+
+@id 361
+
+@desc {
+
+	Move to Banked or Special register from ARM core register moves the value of an ARM core register to the Banked ARM core register or SPSR of the specified mode, or to ELR_hyp. MSR (Banked register) is UNPREDICTABLE if executed in User mode. The effect of using an MSR (Banked register) instruction with a register argument that is not valid for the current mode is UNPREDICTABLE. For more information see Usage restrictions on the Banked register transfer instructions on page B9-1972.
+
+}
+
+@encoding (T1) {
+
+	@word 1 1 1 1 0 0 1 1 1 0 0 R(1) Rn(4) 1 0 0 0 m1(4) 0 0 1 m(1) 0 0 0 0
+
+	@syntax {
+
+		@subid 2012
+
+		@conv {
+
+			banked_reg = BankedRegister(R, m:m1)
+			reg_N = Register(Rn)
+
+		}
+
+		@asm msr banked_reg reg_N
+
+	}
+
+}
+
+@encoding (A1) {
+
+	@word cond(4) 0 0 0 1 0 R(1) 1 0 m1(4) 1 1 1 1 0 0 1 m(1) 0 0 0 0 Rn(4)
+
+	@syntax {
+
+		@subid 2013
+
+		@conv {
+
+			banked_reg = BankedRegister(R, m:m1)
+			reg_N = Register(Rn)
+
+		}
+
+		@asm msr banked_reg reg_N
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
+
+		}
+
+	}
+
+}
+
diff --git a/plugins/arm/v7/opdefs/B9311_msr.d b/plugins/arm/v7/opdefs/B9311_msr.d
new file mode 100644
index 0000000..f996e5d
--- /dev/null
+++ b/plugins/arm/v7/opdefs/B9311_msr.d
@@ -0,0 +1,60 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2017 Cyrille Bagard
+ *
+ *  This file is part of Chrysalide.
+ *
+ *  Chrysalide is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  Chrysalide is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Chrysalide.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title MSR (immediate)
+
+@id 362
+
+@desc {
+
+	Move immediate value to Special register moves selected bits of an immediate value to the CPSR or the SPSR of the current mode. MSR (immediate) is UNPREDICTABLE if: • In Non-debug state, it is attempting to update the CPSR, and that update would change to a mode that is not permitted in the context in which the instruction is executed, see Restrictions on updates to the CPSR.M field on page B9-1970. • In Debug state, it is attempting an update to the CPSR with a <fields> value that is not <fsxc>. See Behavior of MRS and MSR instructions that access the CPSR in Debug state on page C5-2097. An MSR (immediate) executed in User mode: • is UNPREDICTABLE if it attempts to update the SPSR • otherwise, does not update any CPSR field that is accessible only at PL1 or higher, Note MSR (immediate) on page A8-498 describes the valid application level uses of the MSR (immediate) instruction. An MSR (immediate) executed in System mode is UNPREDICTABLE if it attempts to update the SPSR.
+
+}
+
+@encoding (A1) {
+
+	@word cond(4) 0 0 1 1 0 R(1) 1 0 mask(4) 1 1 1 1 imm12(12)
+
+	@syntax {
+
+		@subid 2014
+
+		@conv {
+
+			spec_reg = SpecRegFromMask(mask)
+			imm32 = ARMExpandImm(imm12)
+
+		}
+
+		@asm msr spec_reg imm32
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
+
+		}
+
+	}
+
+}
+
diff --git a/plugins/arm/v7/opdefs/B9312_msr.d b/plugins/arm/v7/opdefs/B9312_msr.d
new file mode 100644
index 0000000..76ae378
--- /dev/null
+++ b/plugins/arm/v7/opdefs/B9312_msr.d
@@ -0,0 +1,81 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2017 Cyrille Bagard
+ *
+ *  This file is part of Chrysalide.
+ *
+ *  Chrysalide is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  Chrysalide is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Chrysalide.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title MSR (register)
+
+@id 363
+
+@desc {
+
+	Move to Special register from ARM core register moves the value of an ARM core register to the CPSR or the SPSR of the current mode. MSR (register) is UNPREDICTABLE if: • In Non-debug state, it is attempting to update the CPSR, and that update would change to a mode that is not permitted in the context in which the instruction is executed, see Restrictions on updates to the CPSR.M field on page B9-1970. • In Debug state, it is attempting an update to the CPSR with a <fields> value that is not <fsxc>. See Behavior of MRS and MSR instructions that access the CPSR in Debug state on page C5-2097. An MSR (register) executed in User mode: • is UNPREDICTABLE if it attempts to update the SPSR • otherwise, does not update any CPSR field that is accessible only at PL1 or higher, Note MSR (register) on page A8-500 describes the valid application level uses of the MSR (register) instruction. An MSR (register) executed in System mode is UNPREDICTABLE if it attempts to update the SPSR.
+
+}
+
+@encoding (T1) {
+
+	@word 1 1 1 1 0 0 1 1 1 0 0 R(1) Rn(4) 1 0 0 0 mask(4) 0 0 0 0 0 0 0 0
+
+	@syntax {
+
+		@subid 2015
+
+		@conv {
+
+			spec_reg = SpecRegFromMask(mask)
+			reg_N = Register(Rn)
+
+		}
+
+		@asm msr spec_reg reg_N
+
+	}
+
+}
+
+@encoding (A1) {
+
+	@word cond(4) 0 0 0 1 0 R(1) 1 0 mask(4) 1 1 1 1 0 0 0 0 0 0 0 0 Rn(4)
+
+	@syntax {
+
+		@subid 2016
+
+		@conv {
+
+			spec_reg = SpecRegFromMask(mask)
+			reg_N = Register(Rn)
+
+		}
+
+		@asm msr spec_reg reg_N
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
+
+		}
+
+	}
+
+}
+
diff --git a/plugins/arm/v7/opdefs/B9313_rfe.d b/plugins/arm/v7/opdefs/B9313_rfe.d
new file mode 100644
index 0000000..fae2d56
--- /dev/null
+++ b/plugins/arm/v7/opdefs/B9313_rfe.d
@@ -0,0 +1,169 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2017 Cyrille Bagard
+ *
+ *  This file is part of Chrysalide.
+ *
+ *  Chrysalide is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  Chrysalide is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Chrysalide.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title RFE
+
+@id 364
+
+@desc {
+
+	Return From Exception loads the PC and the CPSR from the word at the specified address and the following word respectively. For information about memory accesses see Memory accesses on page A8-294. RFE is: • UNDEFINED in Hyp mode. • UNPREDICTABLE in: — The cases described in Restrictions on exception return instructions on page B9-1970. Note As identified in Restrictions on exception return instructions on page B9-1970, RFE differs from other exception return instructions in that it can be executed in System mode. — Debug state.
+
+}
+
+@encoding (T1) {
+
+	@word 1 1 1 0 1 0 0 0 0 0 W(1) 1 Rn(4) 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+
+	@syntax {
+
+		@subid 2017
+
+		@conv {
+
+			reg_N = Register(Rn)
+			wb_reg = WrittenBackReg(reg_N, W)
+
+		}
+
+		@asm rfedb wb_reg
+
+	}
+
+}
+
+@encoding (T2) {
+
+	@word 1 1 1 0 1 0 0 1 1 0 W(1) 1 Rn(4) 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+
+	@syntax {
+
+		@subid 2018
+
+		@conv {
+
+			reg_N = Register(Rn)
+			wb_reg = WrittenBackReg(reg_N, W)
+
+		}
+
+		@asm rfeia wb_reg
+
+	}
+
+}
+
+@encoding (A1) {
+
+	@word 1 1 1 1 1 0 0 P(1) U(1) 0 W(1) 1 Rn(4) 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0
+
+	@syntax {
+
+		@subid 2019
+
+		@assert {
+
+			P == 0
+			U == 0
+
+		}
+
+		@conv {
+
+			reg_N = Register(Rn)
+			wb_reg = WrittenBackReg(reg_N, W)
+
+		}
+
+		@asm rfeda wb_reg
+
+	}
+
+	@syntax {
+
+		@subid 2020
+
+		@assert {
+
+			P == 1
+			U == 0
+
+		}
+
+		@conv {
+
+			reg_N = Register(Rn)
+			wb_reg = WrittenBackReg(reg_N, W)
+
+		}
+
+		@asm rfedb wb_reg
+
+	}
+
+	@syntax {
+
+		@subid 2021
+
+		@assert {
+
+			P == 0
+			U == 1
+
+		}
+
+		@conv {
+
+			reg_N = Register(Rn)
+			wb_reg = WrittenBackReg(reg_N, W)
+
+		}
+
+		@asm rfeia wb_reg
+
+	}
+
+	@syntax {
+
+		@subid 2022
+
+		@assert {
+
+			P == 1
+			U == 1
+
+		}
+
+		@conv {
+
+			reg_N = Register(Rn)
+			wb_reg = WrittenBackReg(reg_N, W)
+
+		}
+
+		@asm rfeib wb_reg
+
+	}
+
+}
+
diff --git a/plugins/arm/v7/opdefs/B9314_smc.d b/plugins/arm/v7/opdefs/B9314_smc.d
new file mode 100644
index 0000000..cf2bcf2
--- /dev/null
+++ b/plugins/arm/v7/opdefs/B9314_smc.d
@@ -0,0 +1,79 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2017 Cyrille Bagard
+ *
+ *  This file is part of Chrysalide.
+ *
+ *  Chrysalide is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  Chrysalide is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Chrysalide.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title SMC (previously SMI)
+
+@id 365
+
+@desc {
+
+	Secure Monitor Call causes a Secure Monitor Call exception. For more information see Secure Monitor Call (SMC) exception on page B1-1210. SMC is available only from software executing at PL1 or higher. It is UNDEFINED in User mode. In an implementation that includes the Virtualization Extensions: • If HCR.TSC is set to 1, execution of an SMC instruction in a Non-secure PL1 mode generates a Hyp Trap exception, regardless of the value of SCR.SCD. For more information see Trapping use of the SMC instruction on page B1-1254. • Otherwise, when SCR.SCD is set to 1, the SMC instruction is: — UNDEFINED in Non-secure state — UNPREDICTABLE if executed in a Secure PL1 mode.
+
+}
+
+@encoding (T1) {
+
+	@word 1 1 1 1 0 1 1 1 1 1 1 1 imm4(4) 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+
+	@syntax {
+
+		@subid 2023
+
+		@conv {
+
+			direct_imm4 = UInt(imm4)
+
+		}
+
+		@asm smc direct_imm4
+
+	}
+
+}
+
+@encoding (A1) {
+
+	@word cond(4) 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 imm4(4)
+
+	@syntax {
+
+		@subid 2024
+
+		@conv {
+
+			direct_imm4 = UInt(imm4)
+
+		}
+
+		@asm smc direct_imm4
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
+
+		}
+
+	}
+
+}
+
diff --git a/plugins/arm/v7/opdefs/B9315_srs.d b/plugins/arm/v7/opdefs/B9315_srs.d
new file mode 100644
index 0000000..e03935c
--- /dev/null
+++ b/plugins/arm/v7/opdefs/B9315_srs.d
@@ -0,0 +1,77 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2017 Cyrille Bagard
+ *
+ *  This file is part of Chrysalide.
+ *
+ *  Chrysalide is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  Chrysalide is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Chrysalide.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title SRS (Thumb)
+
+@id 366
+
+@desc {
+
+	Store Return State stores the LR and SPSR of the current mode to the stack of a specified mode. For information about memory accesses see Memory accesses on page A8-294. SRS is: • UNDEFINED in Hyp mode • UNPREDICTABLE if: — it is executed in ThumbEE state — it is executed in User or System mode — it attempts to store the Monitor mode SP when in Non-secure state — NSACR.RFR is set to 1 and it attempts to store the FIQ mode SP when in Non-secure state — it attempts to store the Hyp mode SP.
+
+}
+
+@encoding (T1) {
+
+	@word 1 1 1 0 1 0 0 0 0 0 W(1) 0 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 mode(5)
+
+	@syntax {
+
+		@subid 2025
+
+		@conv {
+
+			reg_SP = Register(13)
+			wb_reg = WrittenBackReg(reg_SP, W)
+			direct_mode = UInt(mode)
+
+		}
+
+		@asm srsdb wb_reg direct_mode
+
+	}
+
+}
+
+@encoding (T2) {
+
+	@word 1 1 1 0 1 0 0 1 1 0 W(1) 0 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 mode(5)
+
+	@syntax {
+
+		@subid 2026
+
+		@conv {
+
+			reg_SP = Register(13)
+			wb_reg = WrittenBackReg(reg_SP, W)
+			direct_mode = UInt(mode)
+
+		}
+
+		@asm srsia wb_reg direct_mode
+
+	}
+
+}
+
diff --git a/plugins/arm/v7/opdefs/B9316_srs.d b/plugins/arm/v7/opdefs/B9316_srs.d
new file mode 100644
index 0000000..2fbdb5d
--- /dev/null
+++ b/plugins/arm/v7/opdefs/B9316_srs.d
@@ -0,0 +1,131 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2017 Cyrille Bagard
+ *
+ *  This file is part of Chrysalide.
+ *
+ *  Chrysalide is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  Chrysalide is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Chrysalide.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title SRS (ARM)
+
+@id 367
+
+@desc {
+
+	Store Return State stores the LR and SPSR of the current mode to the stack of a specified mode. For information about memory accesses see Memory accesses on page A8-294. SRS is: • UNDEFINED in Hyp mode • UNPREDICTABLE if: — it is executed in User or System mode — it attempts to store the Monitor mode SP when in Non-secure state — NSACR.RFR is set to 1 and it attempts to store the FIQ mode SP when in Non-secure state — if it attempts to store the Hyp mode SP.
+
+}
+
+@encoding (A1) {
+
+	@word 1 1 1 1 1 0 0 P(1) U(1) 1 W(1) 0 1 1 0 1 0 0 0 0 0 1 0 1 0 0 0 mode(5)
+
+	@syntax {
+
+		@subid 2027
+
+		@assert {
+
+			P == 0
+			U == 0
+
+		}
+
+		@conv {
+
+			reg_SP = Register(13)
+			wb_reg = WrittenBackReg(reg_SP, W)
+			direct_mode = UInt(mode)
+
+		}
+
+		@asm srsda wb_reg direct_mode
+
+	}
+
+	@syntax {
+
+		@subid 2028
+
+		@assert {
+
+			P == 1
+			U == 0
+
+		}
+
+		@conv {
+
+			reg_SP = Register(13)
+			wb_reg = WrittenBackReg(reg_SP, W)
+			direct_mode = UInt(mode)
+
+		}
+
+		@asm srsdb wb_reg direct_mode
+
+	}
+
+	@syntax {
+
+		@subid 2029
+
+		@assert {
+
+			P == 0
+			U == 1
+
+		}
+
+		@conv {
+
+			reg_SP = Register(13)
+			wb_reg = WrittenBackReg(reg_SP, W)
+			direct_mode = UInt(mode)
+
+		}
+
+		@asm srsia wb_reg direct_mode
+
+	}
+
+	@syntax {
+
+		@subid 2030
+
+		@assert {
+
+			P == 1
+			U == 1
+
+		}
+
+		@conv {
+
+			reg_SP = Register(13)
+			wb_reg = WrittenBackReg(reg_SP, W)
+			direct_mode = UInt(mode)
+
+		}
+
+		@asm srsib wb_reg direct_mode
+
+	}
+
+}
+
diff --git a/plugins/arm/v7/opdefs/B9317_stm.d b/plugins/arm/v7/opdefs/B9317_stm.d
new file mode 100644
index 0000000..552640f
--- /dev/null
+++ b/plugins/arm/v7/opdefs/B9317_stm.d
@@ -0,0 +1,151 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2017 Cyrille Bagard
+ *
+ *  This file is part of Chrysalide.
+ *
+ *  Chrysalide is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  Chrysalide is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Chrysalide.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title STM (User registers)
+
+@id 368
+
+@desc {
+
+	In a PL1 mode other than System mode, Store Multiple (user registers) stores multiple User mode registers to consecutive memory locations using an address from a base register. The processor reads the base register value normally, using the current mode to determine the correct Banked version of the register. This instruction cannot writeback to the base register. STM (User registers) is UNDEFINED in Hyp mode, and UNPREDICTABLE in User or System modes.
+
+}
+
+@encoding (A1) {
+
+	@word cond(4) 1 0 0 P(1) U(1) 1 0 0 Rn(4) register_list(16)
+
+	@syntax {
+
+		@subid 2031
+
+		@assert {
+
+			P == 0
+			U == 0
+
+		}
+
+		@conv {
+
+			reg_N = Register(Rn)
+			registers = RegList(register_list)
+
+		}
+
+		@asm stmda reg_N registers
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
+
+		}
+
+	}
+
+	@syntax {
+
+		@subid 2032
+
+		@assert {
+
+			P == 1
+			U == 0
+
+		}
+
+		@conv {
+
+			reg_N = Register(Rn)
+			registers = RegList(register_list)
+
+		}
+
+		@asm stmdb reg_N registers
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
+
+		}
+
+	}
+
+	@syntax {
+
+		@subid 2033
+
+		@assert {
+
+			P == 0
+			U == 1
+
+		}
+
+		@conv {
+
+			reg_N = Register(Rn)
+			registers = RegList(register_list)
+
+		}
+
+		@asm stmia reg_N registers
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
+
+		}
+
+	}
+
+	@syntax {
+
+		@subid 2034
+
+		@assert {
+
+			P == 1
+			U == 1
+
+		}
+
+		@conv {
+
+			reg_N = Register(Rn)
+			registers = RegList(register_list)
+
+		}
+
+		@asm stmib reg_N registers
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
+
+		}
+
+	}
+
+}
+
diff --git a/plugins/arm/v7/opdefs/B9319_subs.d b/plugins/arm/v7/opdefs/B9319_subs.d
new file mode 100644
index 0000000..eaf6eca
--- /dev/null
+++ b/plugins/arm/v7/opdefs/B9319_subs.d
@@ -0,0 +1,55 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2017 Cyrille Bagard
+ *
+ *  This file is part of Chrysalide.
+ *
+ *  Chrysalide is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  Chrysalide is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Chrysalide.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title SUBS PC, LR (Thumb)
+
+@id 370
+
+@desc {
+
+	The SUBS PC, LR, #<const> instruction provides an exception return without the use of the stack. It subtracts the immediate constant from LR, branches to the resulting address, and also copies the SPSR to the CPSR. Note • The instruction SUBS PC, LR, #0 is equivalent to MOVS PC, LR and ERET. • For an implementation that includes the Virtualization Extensions, ERET is the preferred disassembly of the T1 encoding defined in this section. Therefore, a disassembler might report an ERET where the original assembler code used SUBS PC, LR, #0. When executing in Hyp mode: • the encoding for SUBS PC, LR, #0 is the encoding of the ERET instruction, see ERET on page B9-1980 • SUBS PC, LR, #<const> with a nonzero constant is UNDEFINED. SUBS PC, LR, #<const> is UNPREDICTABLE: • in the cases described in Restrictions on exception return instructions on page B9-1970 • if it is executed in Debug state.
+
+}
+
+@encoding (T1) {
+
+	@word 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 0 1 0 0 0 1 1 1 1 imm8(8)
+
+	@syntax {
+
+		@subid 2035
+
+		@conv {
+
+			reg_PC = Register(15)
+			reg_LR = Register(14)
+			imm32 = ZeroExtend(imm8, 32)
+
+		}
+
+		@asm subs reg_PC reg_LR imm32
+
+	}
+
+}
+
diff --git a/plugins/arm/v7/opdefs/B931_cps.d b/plugins/arm/v7/opdefs/B931_cps.d
new file mode 100644
index 0000000..e04d320
--- /dev/null
+++ b/plugins/arm/v7/opdefs/B931_cps.d
@@ -0,0 +1,147 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2017 Cyrille Bagard
+ *
+ *  This file is part of Chrysalide.
+ *
+ *  Chrysalide is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  Chrysalide is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Chrysalide.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title CPS (Thumb)
+
+@id 352
+
+@desc {
+
+	Change Processor State changes one or more of the CPSR.{A, I, F} interrupt mask bits and the CPSR.M mode field, without changing the other CPSR bits. CPS is treated as NOP if executed in User mode. CPS is UNPREDICTABLE if it is either: • attempting to change to a mode that is not permitted in the context in which it is executed, see Restrictions on updates to the CPSR.M field on page B9-1970 • executed in Debug state.
+
+}
+
+@encoding (t1) {
+
+	@half 1 0 1 1 0 1 1 0 0 1 1 im(1) 0 A(1) I(1) F(1)
+
+	@syntax {
+
+		@subid 1988
+
+		@assert {
+
+			im == 0
+
+		}
+
+		@conv {
+
+			iflags = IFlagsDefinition(a, i, f)
+
+		}
+
+		@asm cpsie iflags
+
+	}
+
+	@syntax {
+
+		@subid 1989
+
+		@assert {
+
+			im == 1
+
+		}
+
+		@conv {
+
+			iflags = IFlagsDefinition(a, i, f)
+
+		}
+
+		@asm cpsid iflags
+
+	}
+
+}
+
+@encoding (T2) {
+
+	@word 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 0 0 0 0 imod(2) M(1) A(1) I(1) F(1) mode(5)
+
+	@syntax {
+
+		@subid 1990
+
+		@assert {
+
+			M == 0
+			imod == 10
+
+		}
+
+		@conv {
+
+			iflags = IFlagsDefinition(a, i, f)
+
+		}
+
+		@asm cpsie.w iflags
+
+	}
+
+	@syntax {
+
+		@subid 1991
+
+		@assert {
+
+			M == 0
+			imod == 11
+
+		}
+
+		@conv {
+
+			iflags = IFlagsDefinition(a, i, f)
+
+		}
+
+		@asm cpsid.w iflags
+
+	}
+
+	@syntax {
+
+		@subid 1992
+
+		@assert {
+
+			M == 1
+
+		}
+
+		@conv {
+
+			direct_mode = UInt(mode)
+
+		}
+
+		@asm cps.w direct_mode
+
+	}
+
+}
+
diff --git a/plugins/arm/v7/opdefs/B9320_subs.d b/plugins/arm/v7/opdefs/B9320_subs.d
new file mode 100644
index 0000000..ed14d60
--- /dev/null
+++ b/plugins/arm/v7/opdefs/B9320_subs.d
@@ -0,0 +1,95 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2017 Cyrille Bagard
+ *
+ *  This file is part of Chrysalide.
+ *
+ *  Chrysalide is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  Chrysalide is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Chrysalide.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title SUBS PC, LR and related instructions (ARM)
+
+@id 371
+
+@desc {
+
+	The SUBS PC, LR, #<const> instruction provides an exception return without the use of the stack. It subtracts the immediate constant from LR, branches to the resulting address, and also copies the SPSR to the CPSR. The ARM instruction set contains similar instructions based on other data-processing operations, or with a wider range of operands, or both. ARM deprecates using these other instructions, except for MOVS PC, LR. All of these instructions are: • UNDEFINED in Hyp mode • UNPREDICTABLE: — in the cases described in Restrictions on exception return instructions on page B9-1970 — if executed in Debug state.
+
+}
+
+@encoding (A1) {
+
+	@word cond(4) 0 0 1 opcode(4) 1 Rn(4) 1 1 1 1 imm12(12)
+
+	@syntax {
+
+		@subid 2036
+
+		@conv {
+
+			reg_PC = Register(15)
+			reg_LR = Register(14)
+			imm32 = ARMExpandImm(imm12)
+
+		}
+
+		@asm subs reg_PC reg_LR imm32
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
+
+		}
+
+	}
+
+}
+
+@encoding (A2) {
+
+	@word cond(4) 0 0 0 opcode(4) 1 Rn(4) 1 1 1 1 imm5(5) type(2) 0 Rm(4)
+
+	@syntax {
+
+		@subid 2037
+
+		@assert {
+
+			opcode == 1111
+
+		}
+
+		@conv {
+
+			reg_PC = Register(15)
+			reg_M = Register(Rm)
+			shift = DecodeImmShift(type, imm5)
+
+		}
+
+		@asm mvns reg_PC reg_M ?shift
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
+
+		}
+
+	}
+
+}
+
diff --git a/plugins/arm/v7/opdefs/B9321_vmrs.d b/plugins/arm/v7/opdefs/B9321_vmrs.d
new file mode 100644
index 0000000..4dcb42d
--- /dev/null
+++ b/plugins/arm/v7/opdefs/B9321_vmrs.d
@@ -0,0 +1,75 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2017 Cyrille Bagard
+ *
+ *  This file is part of Chrysalide.
+ *
+ *  Chrysalide is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  Chrysalide is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Chrysalide.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title VMRS
+
+@id 372
+
+@desc {
+
+	Move to ARM core register from Advanced SIMD and Floating-point Extension System Register moves the value of an extension system register to an ARM core register. When the specified Floating-point Extension System Register is the FPSCR, a form of the instruction transfers the FPSCR.{N, Z, C, V} condition flags to the APSR.{N, Z, C, V} condition flags. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the security state and mode in which the instruction is executed, an attempt to execute a VMRS instruction might be UNDEFINED, or trapped to Hyp mode. Summary of general controls of CP10 and CP11 functionality on page B1-1230 and Summary of access controls for Advanced SIMD functionality on page B1-1232 summarize these controls. When these settings permit the execution of floating-point and Advanced SIMD instructions, if the specified Floating-point Extension System Register is not the FPSCR, the instruction is UNDEFINED if executed in User mode. In an implementation that includes the Virtualization Extensions, when HCR.TID0 is set to 1, any VMRS access to FPSID from a Non-secure PL1 mode, that would be permitted if HCR.TID0 was set to 0, generates a Hyp Trap exception. For more information, see ID group 0, Primary device identification registers on page B1-1251. Note • VMRS on page A8-954 describes the valid application level uses of the VMRS instruction • for simplicity, the VMRS pseudocode does not show the possible trap to Hyp mode.
+
+}
+
+@encoding (T1) {
+
+	@word 1 1 1 0 1 1 1 0 1 1 1 1 reg(4) Rt(4) 1 0 1 0 0 0 0 1 0 0 0 0
+
+	@syntax {
+
+		@subid 2038
+
+		@conv {
+
+			reg_T = Register(Rt)
+			spec_reg = SpecRegFromReg(reg)
+
+		}
+
+		@asm vmrs reg_T spec_reg
+
+	}
+
+}
+
+@encoding (A1) {
+
+	@word 1 1 1 0 1 1 1 0 1 1 1 1 reg(4) Rt(4) 1 0 1 0 0 0 0 1 0 0 0 0
+
+	@syntax {
+
+		@subid 2039
+
+		@conv {
+
+			reg_T = Register(Rt)
+			spec_reg = SpecRegFromReg(reg)
+
+		}
+
+		@asm vmrs reg_T spec_reg
+
+	}
+
+}
+
diff --git a/plugins/arm/v7/opdefs/B9322_vmsr.d b/plugins/arm/v7/opdefs/B9322_vmsr.d
new file mode 100644
index 0000000..8fdc8ab
--- /dev/null
+++ b/plugins/arm/v7/opdefs/B9322_vmsr.d
@@ -0,0 +1,75 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2017 Cyrille Bagard
+ *
+ *  This file is part of Chrysalide.
+ *
+ *  Chrysalide is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  Chrysalide is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Chrysalide.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title VMSR
+
+@id 373
+
+@desc {
+
+	Move to Advanced SIMD and Floating-point Extension System Register from ARM core register moves the value of an ARM core register to a Floating-point system register. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the security state and mode in which the instruction is executed, an attempt to execute a VMSR instruction might be UNDEFINED, or trapped to Hyp mode. Summary of general controls of CP10 and CP11 functionality on page B1-1230 and Summary of access controls for Advanced SIMD functionality on page B1-1232 summarize these controls. When these settings permit the execution of floating-point and Advanced SIMD instructions, if the specified Floating-point Extension System Register is not the FPSCR, the instruction is UNDEFINED if executed in User mode. Note VMSR on page A8-956 describes the valid application level uses of the VMSR instruction.
+
+}
+
+@encoding (T1) {
+
+	@word 1 1 1 0 1 1 1 0 1 1 1 0 reg(4) Rt(4) 1 0 1 0 0 0 0 1 0 0 0 0
+
+	@syntax {
+
+		@subid 2040
+
+		@conv {
+
+			spec_reg = SpecRegFromReg(reg)
+			reg_T = Register(Rt)
+
+		}
+
+		@asm vmsr spec_reg reg_T
+
+	}
+
+}
+
+@encoding (A1) {
+
+	@word 1 1 1 0 1 1 1 0 1 1 1 0 reg(4) Rt(4) 1 0 1 0 0 0 0 1 0 0 0 0
+
+	@syntax {
+
+		@subid 2041
+
+		@conv {
+
+			spec_reg = SpecRegFromReg(reg)
+			reg_T = Register(Rt)
+
+		}
+
+		@asm vmsr spec_reg reg_T
+
+	}
+
+}
+
diff --git a/plugins/arm/v7/opdefs/B932_cps.d b/plugins/arm/v7/opdefs/B932_cps.d
new file mode 100644
index 0000000..2d93d60
--- /dev/null
+++ b/plugins/arm/v7/opdefs/B932_cps.d
@@ -0,0 +1,101 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2017 Cyrille Bagard
+ *
+ *  This file is part of Chrysalide.
+ *
+ *  Chrysalide is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  Chrysalide is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Chrysalide.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title CPS (ARM)
+
+@id 353
+
+@desc {
+
+	Change Processor State changes one or more of the CPSR.{A, I, F} interrupt mask bits and the CPSR.M mode field, without changing the other CPSR bits. CPS is treated as NOP if executed in User mode. CPS is UNPREDICTABLE if it is either: • attempting to change to a mode that is not permitted in the context in which it is executed, see Restrictions on updates to the CPSR.M field on page B9-1970 • executed in Debug state.
+
+}
+
+@encoding (A1) {
+
+	@word 1 1 1 1 0 0 0 1 0 0 0 0 imod(2) M(1) 0 0 0 0 0 0 0 0 A(1) I(1) F(1) 0 mode(5)
+
+	@syntax {
+
+		@subid 1993
+
+		@assert {
+
+			M == 0
+			imod == 10
+
+		}
+
+		@conv {
+
+			iflags = IFlagsDefinition(a, i, f)
+
+		}
+
+		@asm cpsie iflags
+
+	}
+
+	@syntax {
+
+		@subid 1994
+
+		@assert {
+
+			M == 0
+			imod == 11
+
+		}
+
+		@conv {
+
+			iflags = IFlagsDefinition(a, i, f)
+
+		}
+
+		@asm cpsid iflags
+
+	}
+
+	@syntax {
+
+		@subid 1995
+
+		@assert {
+
+			M == 1
+
+		}
+
+		@conv {
+
+			direct_mode = UInt(mode)
+
+		}
+
+		@asm cps direct_mode
+
+	}
+
+}
+
diff --git a/plugins/arm/v7/opdefs/B933_eret.d b/plugins/arm/v7/opdefs/B933_eret.d
new file mode 100644
index 0000000..0beb321
--- /dev/null
+++ b/plugins/arm/v7/opdefs/B933_eret.d
@@ -0,0 +1,67 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2017 Cyrille Bagard
+ *
+ *  This file is part of Chrysalide.
+ *
+ *  Chrysalide is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  Chrysalide is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Chrysalide.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title ERET
+
+@id 354
+
+@desc {
+
+	When executed in Hyp mode, Exception Return loads the PC from ELR_hyp and loads the CPSR from SPSR_hyp. When executed in a Secure or Non-secure PL1 mode, ERET behaves as: MOVS PC, • LR in the ARM instruction set, see SUBS PC, LR and related instructions (ARM) on page B9-2010 • the equivalent SUBS PC, LR, #0 in the Thumb instruction set, see SUBS PC, LR (Thumb) on page B9-2008. ERET is UNPREDICTABLE: • in the cases described in Restrictions on exception return instructions on page B9-1970 • if it is executed in Debug state. Note In an implementation that includes the Virtualization Extensions: • LR, #0 in the Thumb The T1 encoding of ERET is not a new encoding but, is the preferred synonym of SUBS PC, instruction set. See SUBS PC, LR (Thumb) on page B9-2008 for more information. • Because ERET is the preferred encoding, when decoding Thumb instructions, a disassembler will report an ERET where the original assembler code used SUBS PC, LR, #0.
+
+}
+
+@encoding (T1) {
+
+	@word 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 0 1 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0
+
+	@syntax {
+
+		@subid 1996
+
+		@asm eret
+
+	}
+
+}
+
+@encoding (A1) {
+
+	@word cond(4) 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 0
+
+	@syntax {
+
+		@subid 1997
+
+		@asm eret
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
+
+		}
+
+	}
+
+}
+
diff --git a/plugins/arm/v7/opdefs/B934_hvc.d b/plugins/arm/v7/opdefs/B934_hvc.d
new file mode 100644
index 0000000..e7909a9
--- /dev/null
+++ b/plugins/arm/v7/opdefs/B934_hvc.d
@@ -0,0 +1,73 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2017 Cyrille Bagard
+ *
+ *  This file is part of Chrysalide.
+ *
+ *  Chrysalide is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  Chrysalide is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Chrysalide.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title HVC
+
+@id 355
+
+@desc {
+
+	Hypervisor Call causes a Hypervisor Call exception. For more information see Hypervisor Call (HVC) exception on page B1-1211. Non-secure software executing at PL1 can use this instruction to call the hypervisor to request a service. The HVC instruction is: • UNDEFINED in Secure state, and in User mode in Non-secure state • when SCR.HCE is set to 0, UNDEFINED in Non-secure PL1 modes and UNPREDICTABLE in Hyp mode • UNPREDICTABLE in Debug state. On executing an HVC instruction, the HSR reports the exception as a Hypervisor Call exception, using the EC value 0x12, and captures the value of the immediate argument, see Use of the HSR on page B3-1424.
+
+}
+
+@encoding (T1) {
+
+	@word 1 1 1 1 0 1 1 1 1 1 1 0 imm4(4) 1 0 0 0 imm12(12)
+
+	@syntax {
+
+		@subid 1998
+
+		@conv {
+
+			imm16 = UInt(imm4:imm12)
+
+		}
+
+		@asm hvc imm16
+
+	}
+
+}
+
+@encoding (A1) {
+
+	@word cond(4) 0 0 0 1 0 1 0 0 imm12(12) 0 1 1 1 imm4(4)
+
+	@syntax {
+
+		@subid 1999
+
+		@conv {
+
+			imm16 = UInt(imm12:imm4)
+
+		}
+
+		@asm hvc imm16
+
+	}
+
+}
+
diff --git a/plugins/arm/v7/opdefs/B935_ldm.d b/plugins/arm/v7/opdefs/B935_ldm.d
new file mode 100644
index 0000000..9563920
--- /dev/null
+++ b/plugins/arm/v7/opdefs/B935_ldm.d
@@ -0,0 +1,155 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2017 Cyrille Bagard
+ *
+ *  This file is part of Chrysalide.
+ *
+ *  Chrysalide is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  Chrysalide is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Chrysalide.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title LDM (exception return)
+
+@id 356
+
+@desc {
+
+	Load Multiple (exception return) loads multiple registers from consecutive memory locations using an address from a base register. The SPSR of the current mode is copied to the CPSR. An address adjusted by the size of the data loaded can optionally be written back to the base register. The registers loaded include the PC. The word loaded for the PC is treated as an address and a branch occurs to that address. LDM (exception return) is: • UNDEFINED in Hyp mode • UNPREDICTABLE in: — the cases described in Restrictions on exception return instructions on page B9-1970 — Debug state.
+
+}
+
+@encoding (A1) {
+
+	@word cond(4) 1 0 0 P(1) U(1) 1 W(1) 1 Rn(4) 1 register_list(15)
+
+	@syntax {
+
+		@subid 2000
+
+		@assert {
+
+			P == 0
+			U == 0
+
+		}
+
+		@conv {
+
+			reg_N = Register(Rn)
+			wb_reg = WrittenBackReg(reg_N, W)
+			registers = RegListWithPC(register_list)
+
+		}
+
+		@asm ldmda wb_reg registers
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
+
+		}
+
+	}
+
+	@syntax {
+
+		@subid 2001
+
+		@assert {
+
+			P == 1
+			U == 0
+
+		}
+
+		@conv {
+
+			reg_N = Register(Rn)
+			wb_reg = WrittenBackReg(reg_N, W)
+			registers = RegListWithPC(register_list)
+
+		}
+
+		@asm ldmdb wb_reg registers
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
+
+		}
+
+	}
+
+	@syntax {
+
+		@subid 2002
+
+		@assert {
+
+			P == 0
+			U == 1
+
+		}
+
+		@conv {
+
+			reg_N = Register(Rn)
+			wb_reg = WrittenBackReg(reg_N, W)
+			registers = RegListWithPC(register_list)
+
+		}
+
+		@asm ldmia wb_reg registers
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
+
+		}
+
+	}
+
+	@syntax {
+
+		@subid 2003
+
+		@assert {
+
+			P == 1
+			U == 1
+
+		}
+
+		@conv {
+
+			reg_N = Register(Rn)
+			wb_reg = WrittenBackReg(reg_N, W)
+			registers = RegListWithPC(register_list)
+
+		}
+
+		@asm ldmib wb_reg registers
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
+
+		}
+
+	}
+
+}
+
diff --git a/plugins/arm/v7/opdefs/B936_ldm.d b/plugins/arm/v7/opdefs/B936_ldm.d
new file mode 100644
index 0000000..331febc
--- /dev/null
+++ b/plugins/arm/v7/opdefs/B936_ldm.d
@@ -0,0 +1,151 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2017 Cyrille Bagard
+ *
+ *  This file is part of Chrysalide.
+ *
+ *  Chrysalide is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  Chrysalide is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Chrysalide.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title LDM (User registers)
+
+@id 357
+
+@desc {
+
+	In a PL1 mode other than System mode, Load Multiple (User registers) loads multiple User mode registers from consecutive memory locations using an address from a base register. The registers loaded cannot include the PC. The processor reads the base register value normally, using the current mode to determine the correct Banked version of the register. This instruction cannot writeback to the base register. LDM (user registers) is UNDEFINED in Hyp mode, and UNPREDICTABLE in User and System modes.
+
+}
+
+@encoding (A1) {
+
+	@word cond(4) 1 0 0 P(1) U(1) 1 0 1 Rn(4) 0 register_list(15)
+
+	@syntax {
+
+		@subid 2004
+
+		@assert {
+
+			P == 0
+			U == 0
+
+		}
+
+		@conv {
+
+			reg_N = Register(Rn)
+			registers = RegListWithoutPC(register_list)
+
+		}
+
+		@asm ldmda reg_N registers
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
+
+		}
+
+	}
+
+	@syntax {
+
+		@subid 2005
+
+		@assert {
+
+			P == 1
+			U == 0
+
+		}
+
+		@conv {
+
+			reg_N = Register(Rn)
+			registers = RegListWithoutPC(register_list)
+
+		}
+
+		@asm ldmdb reg_N registers
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
+
+		}
+
+	}
+
+	@syntax {
+
+		@subid 2006
+
+		@assert {
+
+			P == 0
+			U == 1
+
+		}
+
+		@conv {
+
+			reg_N = Register(Rn)
+			registers = RegListWithoutPC(register_list)
+
+		}
+
+		@asm ldmia reg_N registers
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
+
+		}
+
+	}
+
+	@syntax {
+
+		@subid 2007
+
+		@assert {
+
+			P == 1
+			U == 1
+
+		}
+
+		@conv {
+
+			reg_N = Register(Rn)
+			registers = RegListWithoutPC(register_list)
+
+		}
+
+		@asm ldmib reg_N registers
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
+
+		}
+
+	}
+
+}
+
diff --git a/plugins/arm/v7/opdefs/B938_mrs.d b/plugins/arm/v7/opdefs/B938_mrs.d
new file mode 100644
index 0000000..259daae
--- /dev/null
+++ b/plugins/arm/v7/opdefs/B938_mrs.d
@@ -0,0 +1,81 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2017 Cyrille Bagard
+ *
+ *  This file is part of Chrysalide.
+ *
+ *  Chrysalide is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  Chrysalide is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Chrysalide.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title MRS
+
+@id 359
+
+@desc {
+
+	Move to Register from Special register moves the value from the CPSR or SPSR of the current mode into an ARM core register. An MRS that accesses the SPSR is UNPREDICTABLE if executed in User or System mode. An MRS that is executed in User mode and accesses the CPSR returns an UNKNOWN value for the CPSR.{E, A, I, F, M} fields. Note MRS on page A8-496 describes the valid application level uses of the MRS instruction.
+
+}
+
+@encoding (T1) {
+
+	@word 1 1 1 1 0 0 1 1 1 1 1 R(1) 1 1 1 1 1 0 0 0 Rd(4) 0 0 0 0 0 0 0 0
+
+	@syntax {
+
+		@subid 2008
+
+		@conv {
+
+			reg_D = Register(Rd)
+			spec_reg = SpecRegCSPSR(R)
+
+		}
+
+		@asm mrs reg_D spec_reg
+
+	}
+
+}
+
+@encoding (A1) {
+
+	@word cond(4) 0 0 0 1 0 R(1) 0 0 1 1 1 1 Rd(4) 0 0 0 0 0 0 0 0 0 0 0 0
+
+	@syntax {
+
+		@subid 2009
+
+		@conv {
+
+			reg_D = Register(Rd)
+			spec_reg = SpecRegCSPSR(R)
+
+		}
+
+		@asm mrs reg_D spec_reg
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
+
+		}
+
+	}
+
+}
+
diff --git a/plugins/arm/v7/opdefs/B939_mrs.d b/plugins/arm/v7/opdefs/B939_mrs.d
new file mode 100644
index 0000000..61db344
--- /dev/null
+++ b/plugins/arm/v7/opdefs/B939_mrs.d
@@ -0,0 +1,81 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2017 Cyrille Bagard
+ *
+ *  This file is part of Chrysalide.
+ *
+ *  Chrysalide is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  Chrysalide is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Chrysalide.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title MRS (Banked register)
+
+@id 360
+
+@desc {
+
+	Move to Register from Banked or Special register moves the value from the Banked ARM core register or SPSR of the specified mode, or the value of ELR_hyp, to an ARM core register. MRS (Banked register) is UNPREDICTABLE if executed in User mode. The effect of using an MRS (Banked register) instruction with a register argument that is not valid for the current mode is UNPREDICTABLE. For more information see Usage restrictions on the Banked register transfer instructions on page B9-1972.
+
+}
+
+@encoding (T1) {
+
+	@word 1 1 1 1 0 0 1 1 1 1 1 R(1) m1(4) 1 0 0 0 Rd(4) 0 0 1 m(1) 0 0 0 0
+
+	@syntax {
+
+		@subid 2010
+
+		@conv {
+
+			reg_D = Register(Rd)
+			banked_reg = BankedRegister(R, m:m1)
+
+		}
+
+		@asm mrs reg_D banked_reg
+
+	}
+
+}
+
+@encoding (A1) {
+
+	@word cond(4) 0 0 0 1 0 R(1) 0 0 m1(4) Rd(4) 0 0 1 m(1) 0 0 0 0 0 0 0 0
+
+	@syntax {
+
+		@subid 2011
+
+		@conv {
+
+			reg_D = Register(Rd)
+			banked_reg = BankedRegister(R, m:m1)
+
+		}
+
+		@asm mrs reg_D banked_reg
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
+
+		}
+
+	}
+
+}
+
diff --git a/plugins/arm/v7/opdefs/Makefile.am b/plugins/arm/v7/opdefs/Makefile.am
index 331ac98..68e6c6f 100644
--- a/plugins/arm/v7/opdefs/Makefile.am
+++ b/plugins/arm/v7/opdefs/Makefile.am
@@ -22,7 +22,7 @@ D2C_ENCODINGS =							\
 D2C_ID_PREFIX = AOP7
 D2C_ID_COUNT = 500
 
-D2C_SPECIFIC = 
+D2C_SPECIFIC = --filename-reuse=2
 
 
 FIXED_C_INCLUDES =						\
@@ -49,267 +49,289 @@ FIXED_H_HOOKS_INCLUDES =				\
 	\n\#include "../../link.h"
 
 
-# for i in $(seq 1 426); do test -f *A88$i.d && (ls *A88$i.d | sed 's/^/\t/' | sed 's/$/\t\t\t\t\t\t\\/') ; done
+# for i in $(seq 1 426); do file=A88${i}_*d ; test -f $file && ls $file ; done | sed 's/^/\t/' | sed 's/$/\t\t\t\t\t\t\\/'
+# for i in $(seq 1 22); do file=B93${i}_*d ; test -f $file && ls $file ; done | sed 's/^/\t/' | sed 's/$/\t\t\t\t\t\t\\/'
+
 ARMV7_DEFS = 							\
-	adc_A881.d							\
-	adc_A882.d							\
-	adc_A883.d							\
-	add_A884.d							\
-	add_A885.d							\
-	add_A886.d							\
-	add_A887.d							\
-	add_A888.d							\
-	add_A889.d							\
-	add_A8810.d							\
-	add_A8811.d							\
-	adr_A8812.d							\
-	and_A8813.d							\
-	and_A8814.d							\
-	and_A8815.d							\
-	asr_A8816.d							\
-	asr_A8817.d							\
-	b_A8818.d							\
-	bfc_A8819.d							\
-	bfi_A8820.d							\
-	bic_A8821.d							\
-	bic_A8822.d							\
-	bic_A8823.d							\
-	bkpt_A8824.d						\
-	bl_A8825.d							\
-	blx_A8826.d							\
-	bx_A8827.d							\
-	bxj_A8828.d							\
-	cb_A8829.d							\
-	cdp_A8830.d							\
-	clrex_A8832.d						\
-	clz_A8833.d							\
-	cmn_A8834.d							\
-	cmn_A8835.d							\
-	cmn_A8836.d							\
-	cmp_A8837.d							\
-	cmp_A8838.d							\
-	cmp_A8839.d							\
-	dbg_A8842.d							\
-	dmb_A8843.d							\
-	dsb_A8844.d							\
-	eor_A8846.d							\
-	eor_A8847.d							\
-	eor_A8848.d							\
-	it_A8854.d							\
-	ldc_A8855.d							\
-	ldc_A8856.d							\
-	ldm_A8857.d							\
-	ldm_A8858.d							\
-	ldmda_A8859.d						\
-	ldmdb_A8860.d						\
-	ldmib_A8861.d						\
-	ldr_A8862.d							\
-	ldr_A8863.d							\
-	ldr_A8864.d							\
-	ldr_A8865.d							\
-	ldr_A8866.d							\
-	ldrb_A8867.d						\
-	ldrb_A8868.d						\
-	ldrb_A8869.d						\
-	ldrb_A8870.d						\
-	ldrbt_A8871.d						\
-	ldrd_A8872.d						\
-	ldrd_A8873.d						\
-	ldrd_A8874.d						\
-	ldrex_A8875.d						\
-	ldrexb_A8876.d						\
-	ldrexd_A8877.d						\
-	ldrexh_A8878.d						\
-	ldrh_A8879.d						\
-	ldrh_A8880.d						\
-	ldrh_A8881.d						\
-	ldrh_A8882.d						\
-	ldrht_A8883.d						\
-	ldrsb_A8884.d						\
-	ldrsb_A8885.d						\
-	ldrsb_A8886.d						\
-	ldrsbt_A8887.d						\
-	ldrsh_A8888.d						\
-	ldrsh_A8889.d						\
-	ldrsh_A8890.d						\
-	ldrsht_A8891.d						\
-	ldrt_A8892.d						\
-	lsl_A8894.d							\
-	lsl_A8895.d							\
-	lsr_A8896.d							\
-	lsr_A8897.d							\
-	mcr_A8898.d							\
-	mcrr_A8899.d						\
-	mla_A88100.d						\
-	mls_A88101.d						\
-	mov_A88102.d						\
-	mov_A88103.d						\
-	mov_A88104.d						\
-	movt_A88106.d						\
-	mrc_A88107.d						\
-	mrrc_A88108.d						\
-	mrs_A88109.d						\
-	msr_A88111.d						\
-	msr_A88112.d						\
-	mul_A88114.d						\
-	mvn_A88115.d						\
-	mvn_A88116.d						\
-	mvn_A88117.d						\
-	nop_A88119.d						\
-	orn_A88120.d						\
-	orn_A88121.d						\
-	orr_A88122.d						\
-	orr_A88123.d						\
-	orr_A88124.d						\
-	pkh_A88125.d						\
-	pld_A88126.d						\
-	pld_A88127.d						\
-	pld_A88128.d						\
-	pli_A88130.d						\
-	pop_A88131.d						\
-	pop_A88132.d						\
-	push_A88133.d						\
-	qadd_A88134.d						\
-	qadd16_A88135.d						\
-	qadd8_A88136.d						\
-	qasx_A88137.d						\
-	qdadd_A88138.d						\
-	qdsub_A88139.d						\
-	qsax_A88140.d						\
-	qsub_A88141.d						\
-	qsub16_A88142.d						\
-	qsub8_A88143.d						\
-	rbit_A88144.d						\
-	rev_A88145.d						\
-	rev16_A88146.d						\
-	revsh_A88147.d						\
-	ror_A88149.d						\
-	ror_A88150.d						\
-	rrx_A88151.d						\
-	rsb_A88152.d						\
-	rsb_A88153.d						\
-	rsb_A88154.d						\
-	rsc_A88155.d						\
-	rsc_A88156.d						\
-	rsc_A88157.d						\
-	sadd16_A88158.d						\
-	sadd8_A88159.d						\
-	sasx_A88160.d						\
-	sbc_A88161.d						\
-	sbc_A88162.d						\
-	sbc_A88163.d						\
-	sbfx_A88164.d						\
-	sdiv_A88165.d						\
-	sel_A88166.d						\
-	setend_A88167.d						\
-	sev_A88168.d						\
-	shadd16_A88169.d					\
-	shadd8_A88170.d						\
-	shasx_A88171.d						\
-	shsax_A88172.d						\
-	shsub16_A88173.d					\
-	shsub8_A88174.d						\
-	smla_A88176.d						\
-	smlad_A88177.d						\
-	smlal_A88178.d						\
-	smlal_A88179.d						\
-	smlald_A88180.d						\
-	smlaw_A88181.d						\
-	smlsd_A88182.d						\
-	smlsld_A88183.d						\
-	smmla_A88184.d						\
-	smmls_A88185.d						\
-	smmul_A88186.d						\
-	smuad_A88187.d						\
-	smul_A88188.d						\
-	smull_A88189.d						\
-	smulw_A88190.d						\
-	smusd_A88191.d						\
-	ssat_A88193.d						\
-	ssat16_A88194.d						\
-	ssax_A88195.d						\
-	ssub16_A88196.d						\
-	ssub8_A88197.d						\
-	stc_A88198.d						\
-	stm_A88199.d						\
-	stmda_A88200.d						\
-	stmdb_A88201.d						\
-	stmib_A88202.d						\
-	str_A88203.d						\
-	str_A88204.d						\
-	str_A88205.d						\
-	strb_A88206.d						\
-	strb_A88207.d						\
-	strb_A88208.d						\
-	strbt_A88209.d						\
-	strd_A88210.d						\
-	strd_A88211.d						\
-	strex_A88212.d						\
-	strexb_A88213.d						\
-	strexd_A88214.d						\
-	strexh_A88215.d						\
-	strh_A88216.d						\
-	strh_A88217.d						\
-	strh_A88218.d						\
-	strht_A88219.d						\
-	strt_A88220.d						\
-	sub_A88221.d						\
-	sub_A88222.d						\
-	sub_A88223.d						\
-	sub_A88224.d						\
-	sub_A88225.d						\
-	sub_A88226.d						\
-	svc_A88228.d						\
-	swp_A88229.d						\
-	sxtab_A88230.d						\
-	sxtab16_A88231.d					\
-	sxtah_A88232.d						\
-	sxtb_A88233.d						\
-	sxtb16_A88234.d						\
-	sxth_A88235.d						\
-	teq_A88237.d						\
-	teq_A88238.d						\
-	teq_A88239.d						\
-	tst_A88240.d						\
-	tst_A88241.d						\
-	tst_A88242.d						\
-	uadd16_A88243.d						\
-	uadd8_A88244.d						\
-	uasx_A88245.d						\
-	ubfx_A88246.d						\
-	udf_A88247.d						\
-	udiv_A88248.d						\
-	uhadd16_A88249.d					\
-	uhadd8_A88250.d						\
-	uhasx_A88251.d						\
-	uhsax_A88252.d						\
-	uhsub16_A88253.d					\
-	uhsub8_A88254.d						\
-	umaal_A88255.d						\
-	umlal_A88256.d						\
-	umull_A88257.d						\
-	uqadd16_A88258.d					\
-	uqadd8_A88259.d						\
-	uqasx_A88260.d						\
-	uqsax_A88261.d						\
-	uqsub16_A88262.d					\
-	uqsub8_A88263.d						\
-	usad8_A88264.d						\
-	usada8_A88265.d						\
-	usat_A88266.d						\
-	usat16_A88267.d						\
-	usax_A88268.d						\
-	usub16_A88269.d						\
-	usub8_A88270.d						\
-	uxtab_A88271.d						\
-	uxtab16_A88272.d					\
-	uxtah_A88273.d						\
-	uxtb_A88274.d						\
-	uxtb16_A88275.d						\
-	uxth_A88276.d						\
-	wfe_A88424.d						\
-	wfi_A88425.d						\
-	yield_A88426.d
+	A881_adc.d							\
+	A882_adc.d							\
+	A883_adc.d							\
+	A884_add.d							\
+	A885_add.d							\
+	A886_add.d							\
+	A887_add.d							\
+	A888_add.d							\
+	A889_add.d							\
+	A8810_add.d							\
+	A8811_add.d							\
+	A8812_adr.d							\
+	A8813_and.d							\
+	A8814_and.d							\
+	A8815_and.d							\
+	A8816_asr.d							\
+	A8817_asr.d							\
+	A8818_b.d							\
+	A8819_bfc.d							\
+	A8820_bfi.d							\
+	A8821_bic.d							\
+	A8822_bic.d							\
+	A8823_bic.d							\
+	A8824_bkpt.d						\
+	A8825_bl.d							\
+	A8826_blx.d							\
+	A8827_bx.d							\
+	A8828_bxj.d							\
+	A8829_cb.d							\
+	A8830_cdp.d							\
+	A8832_clrex.d						\
+	A8833_clz.d							\
+	A8834_cmn.d							\
+	A8835_cmn.d							\
+	A8836_cmn.d							\
+	A8837_cmp.d							\
+	A8838_cmp.d							\
+	A8839_cmp.d							\
+	A8842_dbg.d							\
+	A8843_dmb.d							\
+	A8844_dsb.d							\
+	A8846_eor.d							\
+	A8847_eor.d							\
+	A8848_eor.d							\
+	A8854_it.d							\
+	A8855_ldc.d							\
+	A8856_ldc.d							\
+	A8857_ldm.d							\
+	A8858_ldm.d							\
+	A8859_ldmda.d						\
+	A8860_ldmdb.d						\
+	A8861_ldmib.d						\
+	A8862_ldr.d							\
+	A8863_ldr.d							\
+	A8864_ldr.d							\
+	A8865_ldr.d							\
+	A8866_ldr.d							\
+	A8867_ldrb.d						\
+	A8868_ldrb.d						\
+	A8869_ldrb.d						\
+	A8870_ldrb.d						\
+	A8871_ldrbt.d						\
+	A8872_ldrd.d						\
+	A8873_ldrd.d						\
+	A8874_ldrd.d						\
+	A8875_ldrex.d						\
+	A8876_ldrexb.d						\
+	A8877_ldrexd.d						\
+	A8878_ldrexh.d						\
+	A8879_ldrh.d						\
+	A8880_ldrh.d						\
+	A8881_ldrh.d						\
+	A8882_ldrh.d						\
+	A8883_ldrht.d						\
+	A8884_ldrsb.d						\
+	A8885_ldrsb.d						\
+	A8886_ldrsb.d						\
+	A8887_ldrsbt.d						\
+	A8888_ldrsh.d						\
+	A8889_ldrsh.d						\
+	A8890_ldrsh.d						\
+	A8891_ldrsht.d						\
+	A8892_ldrt.d						\
+	A8894_lsl.d							\
+	A8895_lsl.d							\
+	A8896_lsr.d							\
+	A8897_lsr.d							\
+	A8898_mcr.d							\
+	A8899_mcrr.d						\
+	A88100_mla.d						\
+	A88101_mls.d						\
+	A88102_mov.d						\
+	A88103_mov.d						\
+	A88104_mov.d						\
+	A88106_movt.d						\
+	A88107_mrc.d						\
+	A88108_mrrc.d						\
+	A88109_mrs.d						\
+	A88111_msr.d						\
+	A88112_msr.d						\
+	A88114_mul.d						\
+	A88115_mvn.d						\
+	A88116_mvn.d						\
+	A88117_mvn.d						\
+	A88119_nop.d						\
+	A88120_orn.d						\
+	A88121_orn.d						\
+	A88122_orr.d						\
+	A88123_orr.d						\
+	A88124_orr.d						\
+	A88125_pkh.d						\
+	A88126_pld.d						\
+	A88127_pld.d						\
+	A88128_pld.d						\
+	A88130_pli.d						\
+	A88131_pop.d						\
+	A88132_pop.d						\
+	A88133_push.d						\
+	A88134_qadd.d						\
+	A88135_qadd16.d						\
+	A88136_qadd8.d						\
+	A88137_qasx.d						\
+	A88138_qdadd.d						\
+	A88139_qdsub.d						\
+	A88140_qsax.d						\
+	A88141_qsub.d						\
+	A88142_qsub16.d						\
+	A88143_qsub8.d						\
+	A88144_rbit.d						\
+	A88145_rev.d						\
+	A88146_rev16.d						\
+	A88147_revsh.d						\
+	A88149_ror.d						\
+	A88150_ror.d						\
+	A88151_rrx.d						\
+	A88152_rsb.d						\
+	A88153_rsb.d						\
+	A88154_rsb.d						\
+	A88155_rsc.d						\
+	A88156_rsc.d						\
+	A88157_rsc.d						\
+	A88158_sadd16.d						\
+	A88159_sadd8.d						\
+	A88160_sasx.d						\
+	A88161_sbc.d						\
+	A88162_sbc.d						\
+	A88163_sbc.d						\
+	A88164_sbfx.d						\
+	A88165_sdiv.d						\
+	A88166_sel.d						\
+	A88167_setend.d						\
+	A88168_sev.d						\
+	A88169_shadd16.d					\
+	A88170_shadd8.d						\
+	A88171_shasx.d						\
+	A88172_shsax.d						\
+	A88173_shsub16.d					\
+	A88174_shsub8.d						\
+	A88176_smla.d						\
+	A88177_smlad.d						\
+	A88178_smlal.d						\
+	A88179_smlal.d						\
+	A88180_smlald.d						\
+	A88181_smlaw.d						\
+	A88182_smlsd.d						\
+	A88183_smlsld.d						\
+	A88184_smmla.d						\
+	A88185_smmls.d						\
+	A88186_smmul.d						\
+	A88187_smuad.d						\
+	A88188_smul.d						\
+	A88189_smull.d						\
+	A88190_smulw.d						\
+	A88191_smusd.d						\
+	A88193_ssat.d						\
+	A88194_ssat16.d						\
+	A88195_ssax.d						\
+	A88196_ssub16.d						\
+	A88197_ssub8.d						\
+	A88198_stc.d						\
+	A88199_stm.d						\
+	A88200_stmda.d						\
+	A88201_stmdb.d						\
+	A88202_stmib.d						\
+	A88203_str.d						\
+	A88204_str.d						\
+	A88205_str.d						\
+	A88206_strb.d						\
+	A88207_strb.d						\
+	A88208_strb.d						\
+	A88209_strbt.d						\
+	A88210_strd.d						\
+	A88211_strd.d						\
+	A88212_strex.d						\
+	A88213_strexb.d						\
+	A88214_strexd.d						\
+	A88215_strexh.d						\
+	A88216_strh.d						\
+	A88217_strh.d						\
+	A88218_strh.d						\
+	A88219_strht.d						\
+	A88220_strt.d						\
+	A88221_sub.d						\
+	A88222_sub.d						\
+	A88223_sub.d						\
+	A88224_sub.d						\
+	A88225_sub.d						\
+	A88226_sub.d						\
+	A88228_svc.d						\
+	A88229_swp.d						\
+	A88230_sxtab.d						\
+	A88231_sxtab16.d					\
+	A88232_sxtah.d						\
+	A88233_sxtb.d						\
+	A88234_sxtb16.d						\
+	A88235_sxth.d						\
+	A88237_teq.d						\
+	A88238_teq.d						\
+	A88239_teq.d						\
+	A88240_tst.d						\
+	A88241_tst.d						\
+	A88242_tst.d						\
+	A88243_uadd16.d						\
+	A88244_uadd8.d						\
+	A88245_uasx.d						\
+	A88246_ubfx.d						\
+	A88247_udf.d						\
+	A88248_udiv.d						\
+	A88249_uhadd16.d					\
+	A88250_uhadd8.d						\
+	A88251_uhasx.d						\
+	A88252_uhsax.d						\
+	A88253_uhsub16.d					\
+	A88254_uhsub8.d						\
+	A88255_umaal.d						\
+	A88256_umlal.d						\
+	A88257_umull.d						\
+	A88258_uqadd16.d					\
+	A88259_uqadd8.d						\
+	A88260_uqasx.d						\
+	A88261_uqsax.d						\
+	A88262_uqsub16.d					\
+	A88263_uqsub8.d						\
+	A88264_usad8.d						\
+	A88265_usada8.d						\
+	A88266_usat.d						\
+	A88267_usat16.d						\
+	A88268_usax.d						\
+	A88269_usub16.d						\
+	A88270_usub8.d						\
+	A88271_uxtab.d						\
+	A88272_uxtab16.d					\
+	A88273_uxtah.d						\
+	A88274_uxtb.d						\
+	A88275_uxtb16.d						\
+	A88276_uxth.d						\
+	A88424_wfe.d						\
+	A88425_wfi.d						\
+	A88426_yield.d						\
+	B931_cps.d							\
+	B932_cps.d							\
+	B933_eret.d							\
+	B934_hvc.d							\
+	B935_ldm.d							\
+	B936_ldm.d							\
+	B938_mrs.d							\
+	B939_mrs.d							\
+	B9310_msr.d							\
+	B9311_msr.d							\
+	B9312_msr.d							\
+	B9313_rfe.d							\
+	B9314_smc.d							\
+	B9315_srs.d							\
+	B9316_srs.d							\
+	B9317_stm.d							\
+	B9319_subs.d						\
+	B9320_subs.d						\
+	B9321_vmrs.d						\
+	B9322_vmsr.d
 
 
 # make dist procède répertoire par répertoire. Or le répertoire opcodes utilise