Included support for ARMv7 system instructions.

1 files changed, 0 insertions, 461 deletions

diff --git a/plugins/arm/v7/opdefs/ldc_A8855.d b/plugins/arm/v7/opdefs/ldc_A8855.d
deleted file mode 100644
index 96cf4a5..0000000
--- a/plugins/arm/v7/opdefs/ldc_A8855.d
+++ /dev/null
@@ -1,461 +0,0 @@
-
-/* Chrysalide - Outil d'analyse de fichiers binaires
- * ##FILE## - traduction d'instructions ARMv7
- *
- * Copyright (C) 2017 Cyrille Bagard
- *
- *  This file is part of Chrysalide.
- *
- *  Chrysalide is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 3 of the License, or
- *  (at your option) any later version.
- *
- *  Chrysalide is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with Chrysalide.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-
-@title LDC, LDC2 (immediate)
-
-@id 54
-
-@desc {
-
-	Load Coprocessor loads memory data from a sequence of consecutive memory addresses to a coprocessor. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the D bit, the CRd field, and in the Unindexed addressing mode only, the imm8 field. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid LDC and LDC2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. In an implementation that includes the Virtualization Extensions, the permitted LDC access to a system control register can be trapped to Hyp mode, meaning that an attempt to execute an LDC instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see Trapping general CP14 accesses to debug registers on page B1-1260. Note For simplicity, the LDC pseudocode does not show this possible trap to Hyp mode.
-
-}
-
-@encoding (T1) {
-
-	@word 1 1 1 0 1 1 0 P(1) U(1) D(1) W(1) 1 Rn(4) CRd(4) coproc(4) imm8(8)
-
-	@syntax {
-
-		@subid 139
-
-		@assert {
-
-			P == 1
-			W == 0
-
-		}
-
-		@conv {
-
-			cp = CoProcessor(coproc)
-			direct_CRd = UInt(CRd)
-			reg_N = Register(Rn)
-			imm32 = ZeroExtend(imm8:'00', 32)
-			maccess = MemAccessOffset(reg_N, imm32)
-
-		}
-
-		@asm ldc cp direct_CRd maccess
-
-	}
-
-	@syntax {
-
-		@subid 140
-
-		@assert {
-
-			P == 1
-			W == 1
-
-		}
-
-		@conv {
-
-			cp = CoProcessor(coproc)
-			direct_CRd = UInt(CRd)
-			reg_N = Register(Rn)
-			imm32 = ZeroExtend(imm8:'00', 32)
-			maccess = MemAccessPreIndexed(reg_N, imm32)
-
-		}
-
-		@asm ldc cp direct_CRd maccess
-
-	}
-
-	@syntax {
-
-		@subid 141
-
-		@assert {
-
-			P == 0
-			W == 1
-
-		}
-
-		@conv {
-
-			cp = CoProcessor(coproc)
-			direct_CRd = UInt(CRd)
-			reg_N = Register(Rn)
-			imm32 = ZeroExtend(imm8:'00', 32)
-			maccess = MemAccessPostIndexed(reg_N, imm32)
-
-		}
-
-		@asm ldc cp direct_CRd maccess
-
-	}
-
-	@syntax {
-
-		@subid 142
-
-		@assert {
-
-			P == 0
-			W == 0
-			U == 1
-
-		}
-
-		@conv {
-
-			cp = CoProcessor(coproc)
-			direct_CRd = UInt(CRd)
-			reg_N = Register(Rn)
-			maccess = MemAccessOffset(reg_N, NULL)
-			option = ZeroExtend(imm8:'00', 32)
-
-		}
-
-		@asm ldc cp direct_CRd maccess option
-
-	}
-
-}
-
-@encoding (T2) {
-
-	@word 1 1 1 1 1 1 0 P(1) U(1) D(1) W(1) 1 Rn(4) CRd(4) coproc(4) imm8(8)
-
-	@syntax {
-
-		@subid 143
-
-		@assert {
-
-			P == 1
-			W == 0
-
-		}
-
-		@conv {
-
-			cp = CoProcessor(coproc)
-			direct_CRd = UInt(CRd)
-			reg_N = Register(Rn)
-			imm32 = ZeroExtend(imm8:'00', 32)
-			maccess = MemAccessOffset(reg_N, imm32)
-
-		}
-
-		@asm ldc cp direct_CRd maccess
-
-	}
-
-	@syntax {
-
-		@subid 144
-
-		@assert {
-
-			P == 1
-			W == 1
-
-		}
-
-		@conv {
-
-			cp = CoProcessor(coproc)
-			direct_CRd = UInt(CRd)
-			reg_N = Register(Rn)
-			imm32 = ZeroExtend(imm8:'00', 32)
-			maccess = MemAccessPreIndexed(reg_N, imm32)
-
-		}
-
-		@asm ldc cp direct_CRd maccess
-
-	}
-
-	@syntax {
-
-		@subid 145
-
-		@assert {
-
-			P == 0
-			W == 1
-
-		}
-
-		@conv {
-
-			cp = CoProcessor(coproc)
-			direct_CRd = UInt(CRd)
-			reg_N = Register(Rn)
-			imm32 = ZeroExtend(imm8:'00', 32)
-			maccess = MemAccessPostIndexed(reg_N, imm32)
-
-		}
-
-		@asm ldc cp direct_CRd maccess
-
-	}
-
-	@syntax {
-
-		@subid 146
-
-		@assert {
-
-			P == 0
-			W == 0
-			U == 1
-
-		}
-
-		@conv {
-
-			cp = CoProcessor(coproc)
-			direct_CRd = UInt(CRd)
-			reg_N = Register(Rn)
-			maccess = MemAccessOffset(reg_N, NULL)
-			option = ZeroExtend(imm8:'00', 32)
-
-		}
-
-		@asm ldc cp direct_CRd maccess option
-
-	}
-
-}
-
-@encoding (A1) {
-
-	@word 1 1 1 0 1 1 0 P(1) U(1) D(1) W(1) 1 Rn(4) CRd(4) coproc(4) imm8(8)
-
-	@syntax {
-
-		@subid 147
-
-		@assert {
-
-			P == 1
-			W == 0
-
-		}
-
-		@conv {
-
-			cp = CoProcessor(coproc)
-			direct_CRd = UInt(CRd)
-			reg_N = Register(Rn)
-			imm32 = ZeroExtend(imm8:'00', 32)
-			maccess = MemAccessOffset(reg_N, imm32)
-
-		}
-
-		@asm ldc cp direct_CRd maccess
-
-	}
-
-	@syntax {
-
-		@subid 148
-
-		@assert {
-
-			P == 1
-			W == 1
-
-		}
-
-		@conv {
-
-			cp = CoProcessor(coproc)
-			direct_CRd = UInt(CRd)
-			reg_N = Register(Rn)
-			imm32 = ZeroExtend(imm8:'00', 32)
-			maccess = MemAccessPreIndexed(reg_N, imm32)
-
-		}
-
-		@asm ldc cp direct_CRd maccess
-
-	}
-
-	@syntax {
-
-		@subid 149
-
-		@assert {
-
-			P == 0
-			W == 1
-
-		}
-
-		@conv {
-
-			cp = CoProcessor(coproc)
-			direct_CRd = UInt(CRd)
-			reg_N = Register(Rn)
-			imm32 = ZeroExtend(imm8:'00', 32)
-			maccess = MemAccessPostIndexed(reg_N, imm32)
-
-		}
-
-		@asm ldc cp direct_CRd maccess
-
-	}
-
-	@syntax {
-
-		@subid 150
-
-		@assert {
-
-			P == 0
-			W == 0
-			U == 1
-
-		}
-
-		@conv {
-
-			cp = CoProcessor(coproc)
-			direct_CRd = UInt(CRd)
-			reg_N = Register(Rn)
-			maccess = MemAccessOffset(reg_N, NULL)
-			option = ZeroExtend(imm8:'00', 32)
-
-		}
-
-		@asm ldc cp direct_CRd maccess option
-
-	}
-
-}
-
-@encoding (A2) {
-
-	@word 1 1 1 1 1 1 0 P(1) U(1) D(1) W(1) 1 Rn(4) CRd(4) coproc(4) imm8(8)
-
-	@syntax {
-
-		@subid 151
-
-		@assert {
-
-			P == 1
-			W == 0
-
-		}
-
-		@conv {
-
-			cp = CoProcessor(coproc)
-			direct_CRd = UInt(CRd)
-			reg_N = Register(Rn)
-			imm32 = ZeroExtend(imm8:'00', 32)
-			maccess = MemAccessOffset(reg_N, imm32)
-
-		}
-
-		@asm ldc cp direct_CRd maccess
-
-	}
-
-	@syntax {
-
-		@subid 152
-
-		@assert {
-
-			P == 1
-			W == 1
-
-		}
-
-		@conv {
-
-			cp = CoProcessor(coproc)
-			direct_CRd = UInt(CRd)
-			reg_N = Register(Rn)
-			imm32 = ZeroExtend(imm8:'00', 32)
-			maccess = MemAccessPreIndexed(reg_N, imm32)
-
-		}
-
-		@asm ldc cp direct_CRd maccess
-
-	}
-
-	@syntax {
-
-		@subid 153
-
-		@assert {
-
-			P == 0
-			W == 1
-
-		}
-
-		@conv {
-
-			cp = CoProcessor(coproc)
-			direct_CRd = UInt(CRd)
-			reg_N = Register(Rn)
-			imm32 = ZeroExtend(imm8:'00', 32)
-			maccess = MemAccessPostIndexed(reg_N, imm32)
-
-		}
-
-		@asm ldc cp direct_CRd maccess
-
-	}
-
-	@syntax {
-
-		@subid 154
-
-		@assert {
-
-			P == 0
-			W == 0
-			U == 1
-
-		}
-
-		@conv {
-
-			cp = CoProcessor(coproc)
-			direct_CRd = UInt(CRd)
-			reg_N = Register(Rn)
-			maccess = MemAccessOffset(reg_N, NULL)
-			option = ZeroExtend(imm8:'00', 32)
-
-		}
-
-		@asm ldc cp direct_CRd maccess option
-
-	}
-
-}
-