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authorCyrille Bagard <nocbos@gmail.com>2018-05-28 20:34:24 (GMT)
committerCyrille Bagard <nocbos@gmail.com>2018-05-28 20:34:24 (GMT)
commit5311a943dffcc410739509b9215ca464f6d1e54c (patch)
tree9c34b5176606aa7bb3dcfb5970a20e3f9b27f1c3 /plugins/arm/v7/opdefs/rev16_A88146.d
parent9f5ed46de568d3db882c939c8ca9d0117bff3369 (diff)
Included support for ARMv7 system instructions.
Diffstat (limited to 'plugins/arm/v7/opdefs/rev16_A88146.d')
-rw-r--r--plugins/arm/v7/opdefs/rev16_A88146.d102
1 files changed, 0 insertions, 102 deletions
diff --git a/plugins/arm/v7/opdefs/rev16_A88146.d b/plugins/arm/v7/opdefs/rev16_A88146.d
deleted file mode 100644
index 49821e5..0000000
--- a/plugins/arm/v7/opdefs/rev16_A88146.d
+++ /dev/null
@@ -1,102 +0,0 @@
-
-/* Chrysalide - Outil d'analyse de fichiers binaires
- * ##FILE## - traduction d'instructions ARMv7
- *
- * Copyright (C) 2017 Cyrille Bagard
- *
- * This file is part of Chrysalide.
- *
- * Chrysalide is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 3 of the License, or
- * (at your option) any later version.
- *
- * Chrysalide is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>.
- */
-
-
-@title REV16
-
-@id 145
-
-@desc {
-
- Byte-Reverse Packed Halfword reverses the byte order in each16-bit halfword of a 32-bit register.
-
-}
-
-@encoding (t1) {
-
- @half 1 0 1 1 1 0 1 0 0 1 Rm(3) Rd(3)
-
- @syntax {
-
- @subid 424
-
- @conv {
-
- reg_D = Register(Rd)
- reg_M = Register(Rm)
-
- }
-
- @asm rev16 reg_D reg_M
-
- }
-
-}
-
-@encoding (T2) {
-
- @word 1 1 1 1 1 0 1 0 1 0 0 1 Rm(4) 1 1 1 1 Rd(4) 1 0 0 1 Rm(4)
-
- @syntax {
-
- @subid 425
-
- @conv {
-
- reg_D = Register(Rd)
- reg_M = Register(Rm)
-
- }
-
- @asm rev16.w reg_D reg_M
-
- }
-
-}
-
-@encoding (A1) {
-
- @word cond(4) 0 1 1 0 1 0 1 1 1 1 1 1 Rd(4) 1 1 1 1 1 0 1 1 Rm(4)
-
- @syntax {
-
- @subid 426
-
- @conv {
-
- reg_D = Register(Rd)
- reg_M = Register(Rm)
-
- }
-
- @asm rev16 reg_D reg_M
-
- @rules {
-
- check g_arm_instruction_set_cond(cond)
-
- }
-
- }
-
-}
-