diff options
| author | Cyrille Bagard <nocbos@gmail.com> | 2018-05-28 20:34:24 (GMT) |
|---|---|---|
| committer | Cyrille Bagard <nocbos@gmail.com> | 2018-05-28 20:34:24 (GMT) |
| commit | 5311a943dffcc410739509b9215ca464f6d1e54c (patch) | |
| tree | 9c34b5176606aa7bb3dcfb5970a20e3f9b27f1c3 /plugins/arm/v7/opdefs/sxtb16_A88234.d | |
| parent | 9f5ed46de568d3db882c939c8ca9d0117bff3369 (diff) | |
Included support for ARMv7 system instructions.
Diffstat (limited to 'plugins/arm/v7/opdefs/sxtb16_A88234.d')
| -rw-r--r-- | plugins/arm/v7/opdefs/sxtb16_A88234.d | 83 |
1 files changed, 0 insertions, 83 deletions
diff --git a/plugins/arm/v7/opdefs/sxtb16_A88234.d b/plugins/arm/v7/opdefs/sxtb16_A88234.d deleted file mode 100644 index fe9fb17..0000000 --- a/plugins/arm/v7/opdefs/sxtb16_A88234.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title SXTB16 - -@id 233 - -@desc { - - Signed Extend Byte 16 extracts two 8-bit values from a register, sign-extends them to 16 bits each, and writes the results to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit values. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 0 0 1 0 1 1 1 1 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) - - @syntax { - - @subid 710 - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') - - } - - @asm sxtb16 ?reg_D reg_M ?rotation - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 1 0 0 0 1 1 1 1 Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) - - @syntax { - - @subid 711 - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') - - } - - @asm sxtb16 ?reg_D reg_M ?rotation - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - |