diff options
| author | Cyrille Bagard <nocbos@gmail.com> | 2018-05-19 10:28:27 (GMT) |
|---|---|---|
| committer | Cyrille Bagard <nocbos@gmail.com> | 2018-05-19 10:28:27 (GMT) |
| commit | 5e6f3a42a2f57c563f34e5ea4d9c377d8618e871 (patch) | |
| tree | 9b245999585accb100a09df44a0f254ece4d9209 /plugins/arm | |
| parent | d52e16c97aa88ecf6a3643ef454e1aa857e0e7dd (diff) | |
Added support for a few extra ARMv7 instructions.
Diffstat (limited to 'plugins/arm')
230 files changed, 5135 insertions, 616 deletions
diff --git a/plugins/arm/v7/fetch.c b/plugins/arm/v7/fetch.c index 20918c5..bf60d9c 100644 --- a/plugins/arm/v7/fetch.c +++ b/plugins/arm/v7/fetch.c @@ -35,7 +35,11 @@ #include <format/preload.h> +#include "operands/it.h" #include "operands/offset.h" +#include "operands/register.h" +#include "operands/reglist.h" +#include "../instruction.h" #include "../register.h" @@ -532,3 +536,171 @@ void help_fetching_with_instruction_ldr_literal_with_orig(GArchInstruction *inst //exit(0); } + + +/****************************************************************************** +* * +* Paramètres : instr = instruction ARMv7 à traiter. * +* proc = représentation de l'architecture utilisée. * +* context = contexte associé à la phase de désassemblage. * +* format = acès aux données du binaire d'origine. * +* iset = type de jeu d'instructions courant. * +* * +* Description : Applique la mise à jour d'un registre après coup. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +void apply_write_back(GArchInstruction *instr, GArchProcessor *proc, GArmV7Context *context, GExeFormat *format, ArmV7InstrSet iset) +{ + GArchOperand *op; /* Opérande de registre */ + + g_arch_instruction_lock_operands(instr); + + op = _g_arch_instruction_get_operand(instr, 0); + assert(G_IS_ARMV7_REGISTER_OPERAND(op)); + + g_armv7_register_operand_write_back(G_ARMV7_REGISTER_OPERAND(op), true); + + g_object_unref(G_OBJECT(op)); + + g_arch_instruction_unlock_operands(instr); + +} + + +/****************************************************************************** +* * +* Paramètres : instr = instruction ARMv7 à traiter. * +* proc = représentation de l'architecture utilisée. * +* context = contexte associé à la phase de désassemblage. * +* format = acès aux données du binaire d'origine. * +* iset = type de jeu d'instructions courant. * +* * +* Description : Applique la mise à jour d'un registre après coup au besoin. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +void apply_write_back_from_registers(GArchInstruction *instr, GArchProcessor *proc, GArmV7Context *context, GExeFormat *format, ArmV7InstrSet iset) +{ + GArchOperand *op; /* Opérande à manipuler */ + GArmV7RegisterOperand *regop; /* Opérande de registre */ + GArchRegister *reg_ref; /* Registre de référence */ + GArmV7RegListOperand *reglist; /* Opérande de liste de reg. */ + size_t count; /* Taille de la liste */ + bool inside; /* Intersection de registres */ + size_t i; /* Boucle de parcours */ + GArmV7Register *reg; /* Registre à analyser */ + + g_arch_instruction_lock_operands(instr); + + op = _g_arch_instruction_get_operand(instr, 0); + assert(G_IS_ARMV7_REGISTER_OPERAND(op)); + + regop = G_ARMV7_REGISTER_OPERAND(op); + + reg_ref = G_ARCH_REGISTER(g_armv7_register_operand_get(regop)); + + op = _g_arch_instruction_get_operand(instr, 1); + assert(G_IS_ARMV7_REGLIST_OPERAND(op)); + + reglist = G_ARMV7_REGLIST_OPERAND(op); + + count = g_armv7_reglist_count_registers(reglist); + + inside = false; + + for (i = 0; i < count && !inside; i++) + { + reg = g_armv7_reglist_operand_get_register(reglist, i); + + inside = (g_arch_register_compare(reg_ref, G_ARCH_REGISTER(reg)) == 0); + + } + + if (!inside) + g_armv7_register_operand_write_back(regop, true); + + g_object_unref(G_OBJECT(regop)); + g_object_unref(G_OBJECT(reglist)); + + g_arch_instruction_unlock_operands(instr); + +} + + +/****************************************************************************** +* * +* Paramètres : instr = instruction ARMv7 à traiter. * +* proc = représentation de l'architecture utilisée. * +* context = contexte associé à la phase de désassemblage. * +* format = acès aux données du binaire d'origine. * +* iset = type de jeu d'instructions courant. * +* * +* Description : Construit un suffixe adapté à une instruction IT. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +void build_it_instruction_suffix(GArchInstruction *instr, GArchProcessor *proc, GArmV7Context *context, GExeFormat *format, ArmV7InstrSet iset) +{ + GArchOperand *op; /* Opérande à manipuler */ + GArmV7ITCondOperand *itcond; /* Opérande de l'instruction */ + uint8_t firstcond; /* Indication sur la condition */ + uint8_t mask; /* Masque d'application */ + char suffix[4]; /* Suffixe à attribuer */ + + g_arch_instruction_lock_operands(instr); + + op = _g_arch_instruction_get_operand(instr, 0); + assert(G_IS_ARMV7_ITCOND_OPERAND(op)); + + itcond = G_ARMV7_ITCOND_OPERAND(op); + + firstcond = g_armv7_itcond_operand_get_firstcond(itcond); + mask = g_armv7_itcond_operand_get_mask(itcond); + + firstcond &= 0x1; + + if ((mask & 0x7) == 0x4) + { + suffix[0] = ((mask & 0x8) >> 3) == firstcond ? 't' : 'e'; + suffix[1] = '\0'; + } + + else if ((mask & 0x3) == 0x2) + { + suffix[0] = ((mask & 0x8) >> 3) == firstcond ? 't' : 'e'; + suffix[1] = ((mask & 0x4) >> 2) == firstcond ? 't' : 'e'; + suffix[2] = '\0'; + } + + else if ((mask & 0x1) == 0x1) + { + suffix[0] = ((mask & 0x8) >> 3) == firstcond ? 't' : 'e'; + suffix[1] = ((mask & 0x4) >> 2) == firstcond ? 't' : 'e'; + suffix[2] = ((mask & 0x2) >> 1) == firstcond ? 't' : 'e'; + suffix[3] = '\0'; + } + + else + suffix[0] = '\0'; + + if (suffix[0] != '\0') + g_arm_instruction_extend_keyword(G_ARM_INSTRUCTION(instr), suffix); + + g_object_unref(G_OBJECT(itcond)); + + g_arch_instruction_unlock_operands(instr); + +} diff --git a/plugins/arm/v7/fetch.h b/plugins/arm/v7/fetch.h index 634879f..602fae5 100644 --- a/plugins/arm/v7/fetch.h +++ b/plugins/arm/v7/fetch.h @@ -110,5 +110,15 @@ static inline void help_fetching_with_instruction_ldr_literal_from_thumb(GArchIn } +/* Applique la mise à jour d'un registre après coup. */ +void apply_write_back(GArchInstruction *, GArchProcessor *, GArmV7Context *, GExeFormat *, ArmV7InstrSet); + +/* Applique la mise à jour d'un registre après coup au besoin. */ +void apply_write_back_from_registers(GArchInstruction *, GArchProcessor *, GArmV7Context *, GExeFormat *, ArmV7InstrSet); + +/* Construit un suffixe adapté à une instruction IT. */ +void build_it_instruction_suffix(GArchInstruction *, GArchProcessor *, GArmV7Context *, GExeFormat *, ArmV7InstrSet); + + #endif /* _PLUGINS_ARM_V7_FETCH_H */ diff --git a/plugins/arm/v7/helpers.h b/plugins/arm/v7/helpers.h index ae759b8..a863a2d 100644 --- a/plugins/arm/v7/helpers.h +++ b/plugins/arm/v7/helpers.h @@ -32,11 +32,13 @@ #include "register.h" #include "operands/coproc.h" #include "operands/estate.h" +#include "operands/it.h" #include "operands/maccess.h" #include "operands/register.h" #include "operands/reglist.h" #include "operands/rotation.h" #include "operands/shift.h" +#include "operands/specreg.h" @@ -146,6 +148,13 @@ }) +#define ITCond(firstcond, mask) \ + ({ \ + GArchOperand *__result; \ + __result = g_armv7_itcond_operand_new(firstcond, mask); \ + __result; \ + }) + #define MemAccessOffset(base, off) \ ({ \ GArchOperand *__result; \ @@ -272,6 +281,72 @@ }) +#define SpecRegAPSR() \ + ({ \ + GArchOperand *__result; \ + __result = g_armv7_specreg_operand_new(SRT_APSR); \ + __result; \ + }) + + +#define SpecRegFromMask(mask) \ + ({ \ + GArchOperand *__result; \ + switch (mask) \ + { \ + case b10: \ + __result = g_armv7_specreg_operand_new(SRT_APSR_NZCVQ); \ + break; \ + case b1: \ + __result = g_armv7_specreg_operand_new(SRT_APSR_G); \ + break; \ + case b11: \ + __result = g_armv7_specreg_operand_new(SRT_APSR_NZCVQG); \ + break; \ + default: \ + __result = NULL; \ + break; \ + } \ + __result; \ + }) + + +#define SpecRegFromReg(reg) \ + ({ \ + GArchOperand *__result; \ + switch (reg) \ + { \ + case b0: \ + __result = g_armv7_specreg_operand_new(SRT_FPSID); \ + break; \ + case b1: \ + __result = g_armv7_specreg_operand_new(SRT_FPSCR); \ + break; \ + case b110: \ + __result = g_armv7_specreg_operand_new(SRT_MVFR1); \ + break; \ + case b111: \ + __result = g_armv7_specreg_operand_new(SRT_MVFR0); \ + break; \ + case b1000: \ + __result = g_armv7_specreg_operand_new(SRT_FPEXC); \ + break; \ + default: \ + __result = NULL; \ + break; \ + } \ + __result; \ + }) + + +#define SpecRegCSPSR(r) \ + ({ \ + GArchOperand *__result; \ + __result = g_armv7_specreg_operand_new(r == 1 ? SRT_SPSR : SRT_CPSR); \ + __result; \ + }) + + #define ThumbExpandImm(imm12) \ ({ \ GArchOperand *__result; \ @@ -314,6 +389,36 @@ }) +#define UncheckedWrittenBackReg(reg) \ + ({ \ + GArchOperand *__result; \ + if (reg == NULL) \ + __result = NULL; \ + else \ + __result = g_armv7_register_operand_new(G_ARMV7_REGISTER(reg)); \ + __result; \ + }) + + +#define WrittenBackReg(reg, writeback) \ + ({ \ + GArchOperand *__result; \ + GArmV7RegisterOperand *__armv7_op; \ + if (reg == NULL) \ + __result = NULL; \ + else \ + { \ + __result = g_armv7_register_operand_new(G_ARMV7_REGISTER(reg)); \ + if (__result != NULL && writeback == 1) \ + { \ + __armv7_op = G_ARMV7_REGISTER_OPERAND(__result); \ + g_armv7_register_operand_write_back(__armv7_op, true); \ + } \ + } \ + __result; \ + }) + + #define Zeros(i) \ ({ \ GArchOperand *__result; \ diff --git a/plugins/arm/v7/opcodes/opcodes_tmp_arm.h b/plugins/arm/v7/opcodes/opcodes_tmp_arm.h index 0e686e1..a43474f 100644 --- a/plugins/arm/v7/opcodes/opcodes_tmp_arm.h +++ b/plugins/arm/v7/opcodes/opcodes_tmp_arm.h @@ -4,15 +4,8 @@ #define armv7_read_arm_instr_eret(r) NULL #define armv7_read_arm_instr_hvc(r) NULL #define armv7_read_arm_instr_isb(r) NULL -#define armv7_read_arm_instr_ldc_ldc2_immediate(r) NULL -#define armv7_read_arm_instr_ldc_ldc2_literal(r) NULL -#define armv7_read_arm_instr_ldmda_ldmfa(r) NULL -#define armv7_read_arm_instr_ldmdb_ldmea(r) NULL #define armv7_read_arm_instr_ldm_exception_return(r) NULL -#define armv7_read_arm_instr_ldmib_ldmed(r) NULL -#define armv7_read_arm_instr_ldm_ldmia_ldmfd_arm(r) NULL #define armv7_read_arm_instr_ldm_user_registers(r) NULL -#define armv7_read_arm_instr_mrs(r) NULL #define armv7_read_arm_instr_mrs_banked_register(r) NULL #define armv7_read_arm_instr_msr_banked_register(r) NULL #define armv7_read_arm_instr_msr_immediate_a8(r) NULL @@ -20,19 +13,8 @@ #define armv7_read_arm_instr_msr_register_a8(r) NULL #define armv7_read_arm_instr_msr_register_b9(r) NULL #define armv7_read_arm_instr_pli_immediate_literal(r) NULL -#define armv7_read_arm_instr_pli_register(r) NULL #define armv7_read_arm_instr_rfe(r) NULL #define armv7_read_arm_instr_smc_previously_smi(r) NULL -#define armv7_read_arm_instr_smlabb_smlabt_smlatb_smlatt(r) NULL -#define armv7_read_arm_instr_smlalbb_smlalbt_smlaltb_smlaltt(r) NULL -#define armv7_read_arm_instr_smlawb_smlawt(r) NULL -#define armv7_read_arm_instr_smulbb_smulbt_smultb_smultt(r) NULL -#define armv7_read_arm_instr_smulwb_smulwt(r) NULL #define armv7_read_arm_instr_srs_arm(r) NULL -#define armv7_read_arm_instr_stc_stc2(r) NULL -#define armv7_read_arm_instr_stmda_stmed(r) NULL -#define armv7_read_arm_instr_stmdb_stmfd(r) NULL -#define armv7_read_arm_instr_stmib_stmfa(r) NULL -#define armv7_read_arm_instr_stm_stmia_stmea(r) NULL #define armv7_read_arm_instr_stm_user_registers(r) NULL #endif diff --git a/plugins/arm/v7/opcodes/opcodes_tmp_thumb_16.h b/plugins/arm/v7/opcodes/opcodes_tmp_thumb_16.h index 62235ec..449ea09 100644 --- a/plugins/arm/v7/opcodes/opcodes_tmp_thumb_16.h +++ b/plugins/arm/v7/opcodes/opcodes_tmp_thumb_16.h @@ -1,7 +1,4 @@ #ifndef thumb_16_def_tmp_h #define thumb_16_def_tmp_h #define armv7_read_thumb_16_instr_cps_thumb(r) NULL -#define armv7_read_thumb_16_instr_it(r) NULL -#define armv7_read_thumb_16_instr_ldm_ldmia_ldmfd_thumb(r) NULL -#define armv7_read_thumb_16_instr_stm_stmia_stmea(r) NULL #endif diff --git a/plugins/arm/v7/opcodes/opcodes_tmp_thumb_32.h b/plugins/arm/v7/opcodes/opcodes_tmp_thumb_32.h index 4848c92..4ecba24 100644 --- a/plugins/arm/v7/opcodes/opcodes_tmp_thumb_32.h +++ b/plugins/arm/v7/opcodes/opcodes_tmp_thumb_32.h @@ -7,25 +7,13 @@ #define armv7_read_thumb_32_instr_eret(r) NULL #define armv7_read_thumb_32_instr_hvc(r) NULL #define armv7_read_thumb_32_instr_isb(r) NULL -#define armv7_read_thumb_32_instr_ldc_ldc2_immediate(r) NULL -#define armv7_read_thumb_32_instr_ldc_ldc2_literal(r) NULL -#define armv7_read_thumb_32_instr_ldmdb_ldmea(r) NULL -#define armv7_read_thumb_32_instr_ldm_ldmia_ldmfd_thumb(r) NULL -#define armv7_read_thumb_32_instr_mrs(r) NULL #define armv7_read_thumb_32_instr_mrs_banked_register(r) NULL #define armv7_read_thumb_32_instr_msr_banked_register(r) NULL -#define armv7_read_thumb_32_instr_msr_register(r) NULL #define armv7_read_thumb_32_instr_pld_immediate(r) NULL #define armv7_read_thumb_32_instr_pld_register(r) NULL #define armv7_read_thumb_32_instr_pli_immediate_literal(r) NULL -#define armv7_read_thumb_32_instr_pli_register(r) NULL #define armv7_read_thumb_32_instr_rfe(r) NULL #define armv7_read_thumb_32_instr_smc_previously_smi(r) NULL -#define armv7_read_thumb_32_instr_smlabb_smlabt_smlatb_smlatt(r) NULL -#define armv7_read_thumb_32_instr_smlalbb_smlalbt_smlaltb_smlaltt(r) NULL -#define armv7_read_thumb_32_instr_smlawb_smlawt(r) NULL -#define armv7_read_thumb_32_instr_smulbb_smulbt_smultb_smultt(r) NULL -#define armv7_read_thumb_32_instr_smulwb_smulwt(r) NULL #define armv7_read_thumb_32_instr_sqadd16(r) NULL #define armv7_read_thumb_32_instr_sqadd8(r) NULL #define armv7_read_thumb_32_instr_sqasx(r) NULL @@ -33,9 +21,6 @@ #define armv7_read_thumb_32_instr_sqsub16(r) NULL #define armv7_read_thumb_32_instr_sqsub8(r) NULL #define armv7_read_thumb_32_instr_srs_thumb(r) NULL -#define armv7_read_thumb_32_instr_stc_stc2(r) NULL -#define armv7_read_thumb_32_instr_stmdb_stmfd(r) NULL -#define armv7_read_thumb_32_instr_stm_stmia_stmea(r) NULL #define armv7_read_thumb_32_instr_sub_register_thumb(r) NULL #define armv7_read_thumb_32_instr_subs_pc_lr_thumb(r) NULL #define armv7_read_thumb_32_instr_tbb_tbh(r) NULL diff --git a/plugins/arm/v7/opdefs/Makefile.am b/plugins/arm/v7/opdefs/Makefile.am index 0ecabc4..331ac98 100644 --- a/plugins/arm/v7/opdefs/Makefile.am +++ b/plugins/arm/v7/opdefs/Makefile.am @@ -95,6 +95,14 @@ ARMV7_DEFS = \ eor_A8846.d \ eor_A8847.d \ eor_A8848.d \ + it_A8854.d \ + ldc_A8855.d \ + ldc_A8856.d \ + ldm_A8857.d \ + ldm_A8858.d \ + ldmda_A8859.d \ + ldmdb_A8860.d \ + ldmib_A8861.d \ ldr_A8862.d \ ldr_A8863.d \ ldr_A8864.d \ @@ -140,6 +148,9 @@ ARMV7_DEFS = \ movt_A88106.d \ mrc_A88107.d \ mrrc_A88108.d \ + mrs_A88109.d \ + msr_A88111.d \ + msr_A88112.d \ mul_A88114.d \ mvn_A88115.d \ mvn_A88116.d \ @@ -154,6 +165,7 @@ ARMV7_DEFS = \ pld_A88126.d \ pld_A88127.d \ pld_A88128.d \ + pli_A88130.d \ pop_A88131.d \ pop_A88132.d \ push_A88133.d \ @@ -197,22 +209,32 @@ ARMV7_DEFS = \ shsax_A88172.d \ shsub16_A88173.d \ shsub8_A88174.d \ + smla_A88176.d \ smlad_A88177.d \ smlal_A88178.d \ + smlal_A88179.d \ smlald_A88180.d \ + smlaw_A88181.d \ smlsd_A88182.d \ smlsld_A88183.d \ smmla_A88184.d \ smmls_A88185.d \ smmul_A88186.d \ smuad_A88187.d \ + smul_A88188.d \ smull_A88189.d \ + smulw_A88190.d \ smusd_A88191.d \ ssat_A88193.d \ ssat16_A88194.d \ ssax_A88195.d \ ssub16_A88196.d \ ssub8_A88197.d \ + stc_A88198.d \ + stm_A88199.d \ + stmda_A88200.d \ + stmdb_A88201.d \ + stmib_A88202.d \ str_A88203.d \ str_A88204.d \ str_A88205.d \ diff --git a/plugins/arm/v7/opdefs/it_A8854.d b/plugins/arm/v7/opdefs/it_A8854.d new file mode 100644 index 0000000..42ee4c9 --- /dev/null +++ b/plugins/arm/v7/opdefs/it_A8854.d @@ -0,0 +1,59 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title IT + +@id 53 + +@desc { + + If-Then makes up to four following instructions (the IT block) conditional. The conditions for the instructions in the IT block are the same as, or the inverse of, the condition the IT instruction specifies for the first instruction in the block. The IT instruction itself does not affect the condition flags, but the execution of the instructions in the IT block can change the condition flags. 16-bit instructions in the IT block, other than CMP, CMN and TST, do not set the condition flags. An IT instruction with the AL condition can be used to get this changed behavior without conditional execution. The architecture permits exception return to an instruction in the IT block only if the restoration of the CPSR restores ITSTATE to a state consistent with the conditions specified by the IT instruction. Any other exception return to an instruction in an IT block is UNPREDICTABLE. Any branch to a target instruction in an IT block is not permitted, and if such a branch is made it is UNPREDICTABLE what condition is used when executing that target instruction and any subsequent instruction in the IT block. See also Conditional instructions on page A4-162 and Conditional execution on page A8-288. + +} + +@encoding (t1) { + + @half 1 0 1 1 1 1 1 1 firstcond(4) mask(4) + + @syntax { + + @subid 138 + + @conv { + + it_cond = ITCond(firstcond, mask) + + } + + @asm it it_cond + + } + + @hooks { + + fetch = build_it_instruction_suffix + + } + +} + diff --git a/plugins/arm/v7/opdefs/ldc_A8855.d b/plugins/arm/v7/opdefs/ldc_A8855.d new file mode 100644 index 0000000..96cf4a5 --- /dev/null +++ b/plugins/arm/v7/opdefs/ldc_A8855.d @@ -0,0 +1,461 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title LDC, LDC2 (immediate) + +@id 54 + +@desc { + + Load Coprocessor loads memory data from a sequence of consecutive memory addresses to a coprocessor. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the D bit, the CRd field, and in the Unindexed addressing mode only, the imm8 field. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid LDC and LDC2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. In an implementation that includes the Virtualization Extensions, the permitted LDC access to a system control register can be trapped to Hyp mode, meaning that an attempt to execute an LDC instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see Trapping general CP14 accesses to debug registers on page B1-1260. Note For simplicity, the LDC pseudocode does not show this possible trap to Hyp mode. + +} + +@encoding (T1) { + + @word 1 1 1 0 1 1 0 P(1) U(1) D(1) W(1) 1 Rn(4) CRd(4) coproc(4) imm8(8) + + @syntax { + + @subid 139 + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldc cp direct_CRd maccess + + } + + @syntax { + + @subid 140 + + @assert { + + P == 1 + W == 1 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm ldc cp direct_CRd maccess + + } + + @syntax { + + @subid 141 + + @assert { + + P == 0 + W == 1 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm ldc cp direct_CRd maccess + + } + + @syntax { + + @subid 142 + + @assert { + + P == 0 + W == 0 + U == 1 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) + option = ZeroExtend(imm8:'00', 32) + + } + + @asm ldc cp direct_CRd maccess option + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 1 0 P(1) U(1) D(1) W(1) 1 Rn(4) CRd(4) coproc(4) imm8(8) + + @syntax { + + @subid 143 + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldc cp direct_CRd maccess + + } + + @syntax { + + @subid 144 + + @assert { + + P == 1 + W == 1 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm ldc cp direct_CRd maccess + + } + + @syntax { + + @subid 145 + + @assert { + + P == 0 + W == 1 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm ldc cp direct_CRd maccess + + } + + @syntax { + + @subid 146 + + @assert { + + P == 0 + W == 0 + U == 1 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) + option = ZeroExtend(imm8:'00', 32) + + } + + @asm ldc cp direct_CRd maccess option + + } + +} + +@encoding (A1) { + + @word 1 1 1 0 1 1 0 P(1) U(1) D(1) W(1) 1 Rn(4) CRd(4) coproc(4) imm8(8) + + @syntax { + + @subid 147 + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldc cp direct_CRd maccess + + } + + @syntax { + + @subid 148 + + @assert { + + P == 1 + W == 1 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm ldc cp direct_CRd maccess + + } + + @syntax { + + @subid 149 + + @assert { + + P == 0 + W == 1 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm ldc cp direct_CRd maccess + + } + + @syntax { + + @subid 150 + + @assert { + + P == 0 + W == 0 + U == 1 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) + option = ZeroExtend(imm8:'00', 32) + + } + + @asm ldc cp direct_CRd maccess option + + } + +} + +@encoding (A2) { + + @word 1 1 1 1 1 1 0 P(1) U(1) D(1) W(1) 1 Rn(4) CRd(4) coproc(4) imm8(8) + + @syntax { + + @subid 151 + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldc cp direct_CRd maccess + + } + + @syntax { + + @subid 152 + + @assert { + + P == 1 + W == 1 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm ldc cp direct_CRd maccess + + } + + @syntax { + + @subid 153 + + @assert { + + P == 0 + W == 1 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm ldc cp direct_CRd maccess + + } + + @syntax { + + @subid 154 + + @assert { + + P == 0 + W == 0 + U == 1 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) + option = ZeroExtend(imm8:'00', 32) + + } + + @asm ldc cp direct_CRd maccess option + + } + +} + diff --git a/plugins/arm/v7/opdefs/ldc_A8856.d b/plugins/arm/v7/opdefs/ldc_A8856.d new file mode 100644 index 0000000..4731ff0 --- /dev/null +++ b/plugins/arm/v7/opdefs/ldc_A8856.d @@ -0,0 +1,201 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title LDC, LDC2 (literal) + +@id 55 + +@desc { + + Load Coprocessor loads memory data from a sequence of consecutive memory addresses to a coprocessor. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the D bit, the CRd field, and in the Unindexed addressing mode only, the imm8 field. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid LDC and LDC2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. In an implementation that includes the Virtualization Extensions, the permitted LDC access to a system control register can be trapped to Hyp mode, meaning that an attempt to execute an LDC instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see Trapping general CP14 accesses to debug registers on page B1-1260. Note For simplicity, the LDC pseudocode does not show this possible trap to Hyp mode. + +} + +@encoding (T1) { + + @word 1 1 1 0 1 1 0 P(1) U(1) D(1) W(1) 1 1 1 1 1 CRd(4) coproc(4) imm8(8) + + @syntax { + + @subid 155 + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + imm32 = ZeroExtend(imm8:'00', 32) + + } + + @asm ldc cp direct_CRd imm32 + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 1 0 P(1) U(1) D(1) W(1) 1 1 1 1 1 CRd(4) coproc(4) imm8(8) + + @syntax { + + @subid 156 + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + imm32 = ZeroExtend(imm8:'00', 32) + + } + + @asm ldc cp direct_CRd imm32 + + } + +} + +@encoding (A1) { + + @word 1 1 1 0 1 1 0 P(1) U(1) D(1) W(1) 1 1 1 1 1 CRd(4) coproc(4) imm8(8) + + @syntax { + + @subid 157 + + @assert { + + P == 0 + U == 1 + W == 0 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_PC = Register(15) + maccess = MemAccessOffset(reg_PC, NULL) + option = ZeroExtend(imm8:'00', 32) + + } + + @asm ldc cp direct_CRd maccess option + + } + + @syntax { + + @subid 158 + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + imm32 = ZeroExtend(imm8:'00', 32) + + } + + @asm ldc cp direct_CRd imm32 + + } + +} + +@encoding (A2) { + + @word 1 1 1 1 1 1 0 P(1) U(1) D(1) W(1) 1 1 1 1 1 CRd(4) coproc(4) imm8(8) + + @syntax { + + @subid 159 + + @assert { + + P == 0 + U == 1 + W == 0 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_PC = Register(15) + maccess = MemAccessOffset(reg_PC, NULL) + option = ZeroExtend(imm8:'00', 32) + + } + + @asm ldc cp direct_CRd maccess option + + } + + @syntax { + + @subid 160 + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + imm32 = ZeroExtend(imm8:'00', 32) + + } + + @asm ldc cp direct_CRd imm32 + + } + +} + diff --git a/plugins/arm/v7/opdefs/ldm_A8857.d b/plugins/arm/v7/opdefs/ldm_A8857.d new file mode 100644 index 0000000..e7733e0 --- /dev/null +++ b/plugins/arm/v7/opdefs/ldm_A8857.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title LDM/LDMIA/LDMFD (Thumb) + +@id 56 + +@desc { + + Load Multiple Increment After (Load Multiple Full Descending) loads multiple registers from consecutive memory locations using an address from a base register. The consecutive memory locations start at this address, and the address just above the highest of those locations can optionally be written back to the base register. The registers loaded can include the PC, causing a branch to a loaded address. Related system instructions are LDM (User registers) on page B9-1986 and LDM (exception return) on page B9-1984. + +} + +@encoding (t1) { + + @half 1 1 0 0 1 Rn(3) register_list(8) + + @syntax { + + @subid 161 + + @conv { + + reg_N = Register(Rn) + wb_reg = UncheckedWrittenBackReg(reg_N) + registers = RegList('00000000':register_list) + + } + + @asm ldm wb_reg registers + + } + + @hooks { + + fetch = apply_write_back_from_registers + + } + +} + +@encoding (T2) { + + @word 1 1 1 0 1 0 0 0 1 0 W(1) 1 Rn(4) P(1) M(1) 0 register_list(13) + + @syntax { + + @subid 162 + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + registers = RegList(P:M:'0':register_list) + + } + + @asm ldm.w wb_reg registers + + } + +} + diff --git a/plugins/arm/v7/opdefs/ldm_A8858.d b/plugins/arm/v7/opdefs/ldm_A8858.d new file mode 100644 index 0000000..8b41183 --- /dev/null +++ b/plugins/arm/v7/opdefs/ldm_A8858.d @@ -0,0 +1,61 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title LDM/LDMIA/LDMFD (ARM) + +@id 57 + +@desc { + + Load Multiple Increment After (Load Multiple Full Descending) loads multiple registers from consecutive memory locations using an address from a base register. The consecutive memory locations start at this address, and the address just above the highest of those locations can optionally be written back to the base register. The registers loaded can include the PC, causing a branch to a loaded address. Related system instructions are LDM (User registers) on page B9-1986 and LDM (exception return) on page B9-1984. + +} + +@encoding (A1) { + + @word cond(4) 1 0 0 0 1 0 W(1) 1 Rn(4) register_list(16) + + @syntax { + + @subid 163 + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + registers = RegList(register_list) + + } + + @asm ldm wb_reg registers + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/ldmda_A8859.d b/plugins/arm/v7/opdefs/ldmda_A8859.d new file mode 100644 index 0000000..6eb27d1 --- /dev/null +++ b/plugins/arm/v7/opdefs/ldmda_A8859.d @@ -0,0 +1,61 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title LDMDA/LDMFA + +@id 58 + +@desc { + + Load Multiple Decrement After (Load Multiple Full Ascending) loads multiple registers from consecutive memory locations using an address from a base register. The consecutive memory locations end at this address, and the address just below the lowest of those locations can optionally be written back to the base register. The registers loaded can include the PC, causing a branch to a loaded address. Related system instructions are LDM (User registers) on page B9-1986 and LDM (exception return) on page B9-1984. + +} + +@encoding (A1) { + + @word cond(4) 1 0 0 0 0 0 W(1) 1 Rn(4) register_list(16) + + @syntax { + + @subid 164 + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + registers = RegList(register_list) + + } + + @asm ldmda wb_reg registers + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/ldmdb_A8860.d b/plugins/arm/v7/opdefs/ldmdb_A8860.d new file mode 100644 index 0000000..a66d2a4 --- /dev/null +++ b/plugins/arm/v7/opdefs/ldmdb_A8860.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title LDMDB/LDMEA + +@id 59 + +@desc { + + Load Multiple Decrement Before (Load Multiple Empty Ascending) loads multiple registers from consecutive memory locations using an address from a base register. The consecutive memory locations end just below this address, and the address of the lowest of those locations can optionally be written back to the base register. The registers loaded can include the PC, causing a branch to a loaded address. Related system instructions are LDM (User registers) on page B9-1986 and LDM (exception return) on page B9-1984. + +} + +@encoding (T1) { + + @word 1 1 1 0 1 0 0 1 0 0 W(1) 1 Rn(4) P(1) M(1) 0 register_list(13) + + @syntax { + + @subid 165 + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + registers = RegList(P:M:'0':register_list) + + } + + @asm ldmdb wb_reg registers + + } + +} + +@encoding (A1) { + + @word cond(4) 1 0 0 1 0 0 W(1) 1 Rn(4) register_list(16) + + @syntax { + + @subid 166 + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + registers = RegList(register_list) + + } + + @asm ldmdb wb_reg registers + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/ldmib_A8861.d b/plugins/arm/v7/opdefs/ldmib_A8861.d new file mode 100644 index 0000000..fa12e8a --- /dev/null +++ b/plugins/arm/v7/opdefs/ldmib_A8861.d @@ -0,0 +1,61 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title LDMIB/LDMED + +@id 60 + +@desc { + + Load Multiple Increment Before (Load Multiple Empty Descending) loads multiple registers from consecutive memory locations using an address from a base register. The consecutive memory locations start just above this address, and the address of the last of those locations can optionally be written back to the base register. The registers loaded can include the PC, causing a branch to a loaded address. Related system instructions are LDM (User registers) on page B9-1986 and LDM (exception return) on page B9-1984. + +} + +@encoding (A1) { + + @word cond(4) 1 0 0 1 1 0 W(1) 1 Rn(4) register_list(16) + + @syntax { + + @subid 167 + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + registers = RegList(register_list) + + } + + @asm ldmib wb_reg registers + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/ldr_A8862.d b/plugins/arm/v7/opdefs/ldr_A8862.d index 8f61aa3..9771bae 100644 --- a/plugins/arm/v7/opdefs/ldr_A8862.d +++ b/plugins/arm/v7/opdefs/ldr_A8862.d @@ -37,7 +37,7 @@ @syntax { - @subid 138 + @subid 168 @conv { @@ -60,7 +60,7 @@ @syntax { - @subid 139 + @subid 169 @conv { @@ -83,7 +83,7 @@ @syntax { - @subid 140 + @subid 170 @conv { @@ -106,7 +106,7 @@ @syntax { - @subid 141 + @subid 171 @assert { @@ -130,7 +130,7 @@ @syntax { - @subid 142 + @subid 172 @assert { @@ -154,7 +154,7 @@ @syntax { - @subid 143 + @subid 173 @assert { diff --git a/plugins/arm/v7/opdefs/ldr_A8863.d b/plugins/arm/v7/opdefs/ldr_A8863.d index c3b423f..e2a443c 100644 --- a/plugins/arm/v7/opdefs/ldr_A8863.d +++ b/plugins/arm/v7/opdefs/ldr_A8863.d @@ -37,7 +37,7 @@ @syntax { - @subid 144 + @subid 174 @assert { @@ -67,7 +67,7 @@ @syntax { - @subid 145 + @subid 175 @assert { @@ -97,7 +97,7 @@ @syntax { - @subid 146 + @subid 176 @assert { diff --git a/plugins/arm/v7/opdefs/ldr_A8864.d b/plugins/arm/v7/opdefs/ldr_A8864.d index c56fa4a..fc19f13 100644 --- a/plugins/arm/v7/opdefs/ldr_A8864.d +++ b/plugins/arm/v7/opdefs/ldr_A8864.d @@ -37,7 +37,7 @@ @syntax { - @subid 147 + @subid 177 @conv { @@ -65,7 +65,7 @@ @syntax { - @subid 148 + @subid 178 @conv { @@ -93,7 +93,7 @@ @syntax { - @subid 149 + @subid 179 @conv { diff --git a/plugins/arm/v7/opdefs/ldr_A8865.d b/plugins/arm/v7/opdefs/ldr_A8865.d index f314cd4..8851ea2 100644 --- a/plugins/arm/v7/opdefs/ldr_A8865.d +++ b/plugins/arm/v7/opdefs/ldr_A8865.d @@ -37,7 +37,7 @@ @syntax { - @subid 150 + @subid 180 @conv { @@ -60,7 +60,7 @@ @syntax { - @subid 151 + @subid 181 @conv { diff --git a/plugins/arm/v7/opdefs/ldr_A8866.d b/plugins/arm/v7/opdefs/ldr_A8866.d index 9640894..e676fec 100644 --- a/plugins/arm/v7/opdefs/ldr_A8866.d +++ b/plugins/arm/v7/opdefs/ldr_A8866.d @@ -37,7 +37,7 @@ @syntax { - @subid 152 + @subid 182 @assert { @@ -68,7 +68,7 @@ @syntax { - @subid 153 + @subid 183 @assert { @@ -99,7 +99,7 @@ @syntax { - @subid 154 + @subid 184 @assert { diff --git a/plugins/arm/v7/opdefs/ldrb_A8867.d b/plugins/arm/v7/opdefs/ldrb_A8867.d index d42f086..a5c1a35 100644 --- a/plugins/arm/v7/opdefs/ldrb_A8867.d +++ b/plugins/arm/v7/opdefs/ldrb_A8867.d @@ -37,7 +37,7 @@ @syntax { - @subid 155 + @subid 185 @conv { @@ -60,7 +60,7 @@ @syntax { - @subid 156 + @subid 186 @conv { @@ -83,7 +83,7 @@ @syntax { - @subid 157 + @subid 187 @assert { @@ -107,7 +107,7 @@ @syntax { - @subid 158 + @subid 188 @assert { @@ -131,7 +131,7 @@ @syntax { - @subid 159 + @subid 189 @assert { diff --git a/plugins/arm/v7/opdefs/ldrb_A8868.d b/plugins/arm/v7/opdefs/ldrb_A8868.d index 4a7ef24..67f122c 100644 --- a/plugins/arm/v7/opdefs/ldrb_A8868.d +++ b/plugins/arm/v7/opdefs/ldrb_A8868.d @@ -37,7 +37,7 @@ @syntax { - @subid 160 + @subid 190 @assert { @@ -67,7 +67,7 @@ @syntax { - @subid 161 + @subid 191 @assert { @@ -97,7 +97,7 @@ @syntax { - @subid 162 + @subid 192 @assert { diff --git a/plugins/arm/v7/opdefs/ldrb_A8869.d b/plugins/arm/v7/opdefs/ldrb_A8869.d index ae6a83c..defb999 100644 --- a/plugins/arm/v7/opdefs/ldrb_A8869.d +++ b/plugins/arm/v7/opdefs/ldrb_A8869.d @@ -37,7 +37,7 @@ @syntax { - @subid 163 + @subid 193 @conv { @@ -58,7 +58,7 @@ @syntax { - @subid 164 + @subid 194 @conv { diff --git a/plugins/arm/v7/opdefs/ldrb_A8870.d b/plugins/arm/v7/opdefs/ldrb_A8870.d index 3a730e0..b99d19b 100644 --- a/plugins/arm/v7/opdefs/ldrb_A8870.d +++ b/plugins/arm/v7/opdefs/ldrb_A8870.d @@ -37,7 +37,7 @@ @syntax { - @subid 165 + @subid 195 @conv { @@ -60,7 +60,7 @@ @syntax { - @subid 166 + @subid 196 @conv { @@ -84,7 +84,7 @@ @syntax { - @subid 167 + @subid 197 @assert { @@ -115,7 +115,7 @@ @syntax { - @subid 168 + @subid 198 @assert { @@ -146,7 +146,7 @@ @syntax { - @subid 169 + @subid 199 @assert { diff --git a/plugins/arm/v7/opdefs/ldrbt_A8871.d b/plugins/arm/v7/opdefs/ldrbt_A8871.d index 6403ef4..fdd9176 100644 --- a/plugins/arm/v7/opdefs/ldrbt_A8871.d +++ b/plugins/arm/v7/opdefs/ldrbt_A8871.d @@ -37,7 +37,7 @@ @syntax { - @subid 170 + @subid 200 @conv { @@ -60,7 +60,7 @@ @syntax { - @subid 171 + @subid 201 @conv { @@ -89,7 +89,7 @@ @syntax { - @subid 172 + @subid 202 @conv { diff --git a/plugins/arm/v7/opdefs/ldrd_A8872.d b/plugins/arm/v7/opdefs/ldrd_A8872.d index 547bec4..752f956 100644 --- a/plugins/arm/v7/opdefs/ldrd_A8872.d +++ b/plugins/arm/v7/opdefs/ldrd_A8872.d @@ -37,7 +37,7 @@ @syntax { - @subid 173 + @subid 203 @assert { @@ -62,7 +62,7 @@ @syntax { - @subid 174 + @subid 204 @assert { @@ -87,7 +87,7 @@ @syntax { - @subid 175 + @subid 205 @assert { @@ -118,7 +118,7 @@ @syntax { - @subid 176 + @subid 206 @assert { @@ -149,7 +149,7 @@ @syntax { - @subid 177 + @subid 207 @assert { @@ -180,7 +180,7 @@ @syntax { - @subid 178 + @subid 208 @assert { diff --git a/plugins/arm/v7/opdefs/ldrd_A8873.d b/plugins/arm/v7/opdefs/ldrd_A8873.d index 9b15a15..031fb31 100644 --- a/plugins/arm/v7/opdefs/ldrd_A8873.d +++ b/plugins/arm/v7/opdefs/ldrd_A8873.d @@ -37,7 +37,7 @@ @syntax { - @subid 179 + @subid 209 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 180 + @subid 210 @conv { diff --git a/plugins/arm/v7/opdefs/ldrd_A8874.d b/plugins/arm/v7/opdefs/ldrd_A8874.d index 1d57312..c35f2cc 100644 --- a/plugins/arm/v7/opdefs/ldrd_A8874.d +++ b/plugins/arm/v7/opdefs/ldrd_A8874.d @@ -37,7 +37,7 @@ @syntax { - @subid 181 + @subid 211 @assert { @@ -68,7 +68,7 @@ @syntax { - @subid 182 + @subid 212 @assert { @@ -99,7 +99,7 @@ @syntax { - @subid 183 + @subid 213 @assert { diff --git a/plugins/arm/v7/opdefs/ldrex_A8875.d b/plugins/arm/v7/opdefs/ldrex_A8875.d index c5d85cc..af19077 100644 --- a/plugins/arm/v7/opdefs/ldrex_A8875.d +++ b/plugins/arm/v7/opdefs/ldrex_A8875.d @@ -37,7 +37,7 @@ @syntax { - @subid 184 + @subid 214 @conv { @@ -60,7 +60,7 @@ @syntax { - @subid 185 + @subid 215 @conv { diff --git a/plugins/arm/v7/opdefs/ldrexb_A8876.d b/plugins/arm/v7/opdefs/ldrexb_A8876.d index c90f3fe..39b07b3 100644 --- a/plugins/arm/v7/opdefs/ldrexb_A8876.d +++ b/plugins/arm/v7/opdefs/ldrexb_A8876.d @@ -37,7 +37,7 @@ @syntax { - @subid 186 + @subid 216 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 187 + @subid 217 @conv { diff --git a/plugins/arm/v7/opdefs/ldrexd_A8877.d b/plugins/arm/v7/opdefs/ldrexd_A8877.d index 16b59dc..232f4fa 100644 --- a/plugins/arm/v7/opdefs/ldrexd_A8877.d +++ b/plugins/arm/v7/opdefs/ldrexd_A8877.d @@ -37,7 +37,7 @@ @syntax { - @subid 188 + @subid 218 @conv { @@ -60,7 +60,7 @@ @syntax { - @subid 189 + @subid 219 @conv { diff --git a/plugins/arm/v7/opdefs/ldrexh_A8878.d b/plugins/arm/v7/opdefs/ldrexh_A8878.d index fb08874..ac124f5 100644 --- a/plugins/arm/v7/opdefs/ldrexh_A8878.d +++ b/plugins/arm/v7/opdefs/ldrexh_A8878.d @@ -37,7 +37,7 @@ @syntax { - @subid 190 + @subid 220 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 191 + @subid 221 @conv { diff --git a/plugins/arm/v7/opdefs/ldrh_A8879.d b/plugins/arm/v7/opdefs/ldrh_A8879.d index 75177f0..674a7d4 100644 --- a/plugins/arm/v7/opdefs/ldrh_A8879.d +++ b/plugins/arm/v7/opdefs/ldrh_A8879.d @@ -37,7 +37,7 @@ @syntax { - @subid 192 + @subid 222 @conv { @@ -60,7 +60,7 @@ @syntax { - @subid 193 + @subid 223 @conv { @@ -83,7 +83,7 @@ @syntax { - @subid 194 + @subid 224 @assert { @@ -107,7 +107,7 @@ @syntax { - @subid 195 + @subid 225 @assert { @@ -131,7 +131,7 @@ @syntax { - @subid 196 + @subid 226 @assert { diff --git a/plugins/arm/v7/opdefs/ldrh_A8880.d b/plugins/arm/v7/opdefs/ldrh_A8880.d index f63e805..7f7f1f7 100644 --- a/plugins/arm/v7/opdefs/ldrh_A8880.d +++ b/plugins/arm/v7/opdefs/ldrh_A8880.d @@ -37,7 +37,7 @@ @syntax { - @subid 197 + @subid 227 @assert { @@ -67,7 +67,7 @@ @syntax { - @subid 198 + @subid 228 @assert { @@ -97,7 +97,7 @@ @syntax { - @subid 199 + @subid 229 @assert { diff --git a/plugins/arm/v7/opdefs/ldrh_A8881.d b/plugins/arm/v7/opdefs/ldrh_A8881.d index 83baf79..43346e9 100644 --- a/plugins/arm/v7/opdefs/ldrh_A8881.d +++ b/plugins/arm/v7/opdefs/ldrh_A8881.d @@ -37,7 +37,7 @@ @syntax { - @subid 200 + @subid 230 @conv { @@ -58,7 +58,7 @@ @syntax { - @subid 201 + @subid 231 @conv { diff --git a/plugins/arm/v7/opdefs/ldrh_A8882.d b/plugins/arm/v7/opdefs/ldrh_A8882.d index 31f20cf..6f9fb73 100644 --- a/plugins/arm/v7/opdefs/ldrh_A8882.d +++ b/plugins/arm/v7/opdefs/ldrh_A8882.d @@ -37,7 +37,7 @@ @syntax { - @subid 202 + @subid 232 @conv { @@ -60,7 +60,7 @@ @syntax { - @subid 203 + @subid 233 @conv { @@ -84,7 +84,7 @@ @syntax { - @subid 204 + @subid 234 @assert { @@ -114,7 +114,7 @@ @syntax { - @subid 205 + @subid 235 @assert { @@ -144,7 +144,7 @@ @syntax { - @subid 206 + @subid 236 @assert { diff --git a/plugins/arm/v7/opdefs/ldrht_A8883.d b/plugins/arm/v7/opdefs/ldrht_A8883.d index 851d06b..46bd025 100644 --- a/plugins/arm/v7/opdefs/ldrht_A8883.d +++ b/plugins/arm/v7/opdefs/ldrht_A8883.d @@ -37,7 +37,7 @@ @syntax { - @subid 207 + @subid 237 @conv { @@ -60,7 +60,7 @@ @syntax { - @subid 208 + @subid 238 @conv { @@ -89,7 +89,7 @@ @syntax { - @subid 209 + @subid 239 @conv { diff --git a/plugins/arm/v7/opdefs/ldrsb_A8884.d b/plugins/arm/v7/opdefs/ldrsb_A8884.d index 327ffd3..828918f 100644 --- a/plugins/arm/v7/opdefs/ldrsb_A8884.d +++ b/plugins/arm/v7/opdefs/ldrsb_A8884.d @@ -37,7 +37,7 @@ @syntax { - @subid 210 + @subid 240 @conv { @@ -60,7 +60,7 @@ @syntax { - @subid 211 + @subid 241 @assert { @@ -84,7 +84,7 @@ @syntax { - @subid 212 + @subid 242 @assert { @@ -108,7 +108,7 @@ @syntax { - @subid 213 + @subid 243 @assert { @@ -138,7 +138,7 @@ @syntax { - @subid 214 + @subid 244 @assert { @@ -168,7 +168,7 @@ @syntax { - @subid 215 + @subid 245 @assert { @@ -198,7 +198,7 @@ @syntax { - @subid 216 + @subid 246 @assert { diff --git a/plugins/arm/v7/opdefs/ldrsb_A8885.d b/plugins/arm/v7/opdefs/ldrsb_A8885.d index 5c1447d..5d5c1c4 100644 --- a/plugins/arm/v7/opdefs/ldrsb_A8885.d +++ b/plugins/arm/v7/opdefs/ldrsb_A8885.d @@ -37,7 +37,7 @@ @syntax { - @subid 217 + @subid 247 @conv { @@ -58,7 +58,7 @@ @syntax { - @subid 218 + @subid 248 @conv { diff --git a/plugins/arm/v7/opdefs/ldrsb_A8886.d b/plugins/arm/v7/opdefs/ldrsb_A8886.d index 50b611d..9ce942b 100644 --- a/plugins/arm/v7/opdefs/ldrsb_A8886.d +++ b/plugins/arm/v7/opdefs/ldrsb_A8886.d @@ -37,7 +37,7 @@ @syntax { - @subid 219 + @subid 249 @conv { @@ -60,7 +60,7 @@ @syntax { - @subid 220 + @subid 250 @conv { @@ -84,7 +84,7 @@ @syntax { - @subid 221 + @subid 251 @assert { @@ -114,7 +114,7 @@ @syntax { - @subid 222 + @subid 252 @assert { @@ -144,7 +144,7 @@ @syntax { - @subid 223 + @subid 253 @assert { diff --git a/plugins/arm/v7/opdefs/ldrsbt_A8887.d b/plugins/arm/v7/opdefs/ldrsbt_A8887.d index f90d8b7..181739c 100644 --- a/plugins/arm/v7/opdefs/ldrsbt_A8887.d +++ b/plugins/arm/v7/opdefs/ldrsbt_A8887.d @@ -37,7 +37,7 @@ @syntax { - @subid 224 + @subid 254 @conv { @@ -60,7 +60,7 @@ @syntax { - @subid 225 + @subid 255 @conv { @@ -89,7 +89,7 @@ @syntax { - @subid 226 + @subid 256 @conv { diff --git a/plugins/arm/v7/opdefs/ldrsh_A8888.d b/plugins/arm/v7/opdefs/ldrsh_A8888.d index a5ae458..3d9c2a3 100644 --- a/plugins/arm/v7/opdefs/ldrsh_A8888.d +++ b/plugins/arm/v7/opdefs/ldrsh_A8888.d @@ -37,7 +37,7 @@ @syntax { - @subid 227 + @subid 257 @conv { @@ -60,7 +60,7 @@ @syntax { - @subid 228 + @subid 258 @assert { @@ -84,7 +84,7 @@ @syntax { - @subid 229 + @subid 259 @assert { @@ -108,7 +108,7 @@ @syntax { - @subid 230 + @subid 260 @assert { @@ -138,7 +138,7 @@ @syntax { - @subid 231 + @subid 261 @assert { @@ -168,7 +168,7 @@ @syntax { - @subid 232 + @subid 262 @assert { @@ -198,7 +198,7 @@ @syntax { - @subid 233 + @subid 263 @assert { diff --git a/plugins/arm/v7/opdefs/ldrsh_A8889.d b/plugins/arm/v7/opdefs/ldrsh_A8889.d index 8ea8d24..d6a6197 100644 --- a/plugins/arm/v7/opdefs/ldrsh_A8889.d +++ b/plugins/arm/v7/opdefs/ldrsh_A8889.d @@ -37,7 +37,7 @@ @syntax { - @subid 234 + @subid 264 @conv { @@ -58,7 +58,7 @@ @syntax { - @subid 235 + @subid 265 @conv { diff --git a/plugins/arm/v7/opdefs/ldrsh_A8890.d b/plugins/arm/v7/opdefs/ldrsh_A8890.d index 9f0fb46..9269ca0 100644 --- a/plugins/arm/v7/opdefs/ldrsh_A8890.d +++ b/plugins/arm/v7/opdefs/ldrsh_A8890.d @@ -37,7 +37,7 @@ @syntax { - @subid 236 + @subid 266 @conv { @@ -60,7 +60,7 @@ @syntax { - @subid 237 + @subid 267 @conv { @@ -84,7 +84,7 @@ @syntax { - @subid 238 + @subid 268 @assert { @@ -114,7 +114,7 @@ @syntax { - @subid 239 + @subid 269 @assert { @@ -144,7 +144,7 @@ @syntax { - @subid 240 + @subid 270 @assert { diff --git a/plugins/arm/v7/opdefs/ldrsht_A8891.d b/plugins/arm/v7/opdefs/ldrsht_A8891.d index 759a6d8..b1402f7 100644 --- a/plugins/arm/v7/opdefs/ldrsht_A8891.d +++ b/plugins/arm/v7/opdefs/ldrsht_A8891.d @@ -37,7 +37,7 @@ @syntax { - @subid 241 + @subid 271 @conv { @@ -60,7 +60,7 @@ @syntax { - @subid 242 + @subid 272 @conv { @@ -89,7 +89,7 @@ @syntax { - @subid 243 + @subid 273 @conv { diff --git a/plugins/arm/v7/opdefs/ldrt_A8892.d b/plugins/arm/v7/opdefs/ldrt_A8892.d index be38438..23d1d6f 100644 --- a/plugins/arm/v7/opdefs/ldrt_A8892.d +++ b/plugins/arm/v7/opdefs/ldrt_A8892.d @@ -37,7 +37,7 @@ @syntax { - @subid 244 + @subid 274 @conv { @@ -60,7 +60,7 @@ @syntax { - @subid 245 + @subid 275 @conv { @@ -89,7 +89,7 @@ @syntax { - @subid 246 + @subid 276 @conv { diff --git a/plugins/arm/v7/opdefs/lsl_A8894.d b/plugins/arm/v7/opdefs/lsl_A8894.d index 617991f..b4689bb 100644 --- a/plugins/arm/v7/opdefs/lsl_A8894.d +++ b/plugins/arm/v7/opdefs/lsl_A8894.d @@ -37,7 +37,7 @@ @syntax { - @subid 247 + @subid 277 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 248 + @subid 278 @assert { @@ -81,7 +81,7 @@ @syntax { - @subid 249 + @subid 279 @assert { @@ -109,7 +109,7 @@ @syntax { - @subid 250 + @subid 280 @assert { @@ -137,7 +137,7 @@ @syntax { - @subid 251 + @subid 281 @assert { diff --git a/plugins/arm/v7/opdefs/lsl_A8895.d b/plugins/arm/v7/opdefs/lsl_A8895.d index 761e2dc..59bbb91 100644 --- a/plugins/arm/v7/opdefs/lsl_A8895.d +++ b/plugins/arm/v7/opdefs/lsl_A8895.d @@ -37,7 +37,7 @@ @syntax { - @subid 252 + @subid 282 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 253 + @subid 283 @assert { @@ -81,7 +81,7 @@ @syntax { - @subid 254 + @subid 284 @assert { @@ -109,7 +109,7 @@ @syntax { - @subid 255 + @subid 285 @assert { @@ -137,7 +137,7 @@ @syntax { - @subid 256 + @subid 286 @assert { diff --git a/plugins/arm/v7/opdefs/lsr_A8896.d b/plugins/arm/v7/opdefs/lsr_A8896.d index 07e1e21..07f12da 100644 --- a/plugins/arm/v7/opdefs/lsr_A8896.d +++ b/plugins/arm/v7/opdefs/lsr_A8896.d @@ -37,7 +37,7 @@ @syntax { - @subid 257 + @subid 287 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 258 + @subid 288 @assert { @@ -81,7 +81,7 @@ @syntax { - @subid 259 + @subid 289 @assert { @@ -109,7 +109,7 @@ @syntax { - @subid 260 + @subid 290 @assert { @@ -137,7 +137,7 @@ @syntax { - @subid 261 + @subid 291 @assert { diff --git a/plugins/arm/v7/opdefs/lsr_A8897.d b/plugins/arm/v7/opdefs/lsr_A8897.d index d0fd071..fa0b70f 100644 --- a/plugins/arm/v7/opdefs/lsr_A8897.d +++ b/plugins/arm/v7/opdefs/lsr_A8897.d @@ -37,7 +37,7 @@ @syntax { - @subid 262 + @subid 292 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 263 + @subid 293 @assert { @@ -81,7 +81,7 @@ @syntax { - @subid 264 + @subid 294 @assert { @@ -109,7 +109,7 @@ @syntax { - @subid 265 + @subid 295 @assert { @@ -137,7 +137,7 @@ @syntax { - @subid 266 + @subid 296 @assert { diff --git a/plugins/arm/v7/opdefs/mcr_A8898.d b/plugins/arm/v7/opdefs/mcr_A8898.d index c18639e..8a2252b 100644 --- a/plugins/arm/v7/opdefs/mcr_A8898.d +++ b/plugins/arm/v7/opdefs/mcr_A8898.d @@ -37,7 +37,7 @@ @syntax { - @subid 267 + @subid 297 @conv { @@ -62,7 +62,7 @@ @syntax { - @subid 268 + @subid 298 @conv { @@ -87,7 +87,7 @@ @syntax { - @subid 269 + @subid 299 @conv { @@ -112,7 +112,7 @@ @syntax { - @subid 270 + @subid 300 @conv { diff --git a/plugins/arm/v7/opdefs/mcrr_A8899.d b/plugins/arm/v7/opdefs/mcrr_A8899.d index a7aa837..b500446 100644 --- a/plugins/arm/v7/opdefs/mcrr_A8899.d +++ b/plugins/arm/v7/opdefs/mcrr_A8899.d @@ -37,7 +37,7 @@ @syntax { - @subid 271 + @subid 301 @conv { @@ -61,7 +61,7 @@ @syntax { - @subid 272 + @subid 302 @conv { @@ -85,7 +85,7 @@ @syntax { - @subid 273 + @subid 303 @conv { @@ -109,7 +109,7 @@ @syntax { - @subid 274 + @subid 304 @conv { diff --git a/plugins/arm/v7/opdefs/mla_A88100.d b/plugins/arm/v7/opdefs/mla_A88100.d index c1d5c73..ec8b92b 100644 --- a/plugins/arm/v7/opdefs/mla_A88100.d +++ b/plugins/arm/v7/opdefs/mla_A88100.d @@ -37,7 +37,7 @@ @syntax { - @subid 275 + @subid 305 @conv { @@ -60,7 +60,7 @@ @syntax { - @subid 276 + @subid 306 @assert { @@ -89,7 +89,7 @@ @syntax { - @subid 277 + @subid 307 @assert { diff --git a/plugins/arm/v7/opdefs/mls_A88101.d b/plugins/arm/v7/opdefs/mls_A88101.d index 54dfe42..083e4e1 100644 --- a/plugins/arm/v7/opdefs/mls_A88101.d +++ b/plugins/arm/v7/opdefs/mls_A88101.d @@ -37,7 +37,7 @@ @syntax { - @subid 278 + @subid 308 @conv { @@ -60,7 +60,7 @@ @syntax { - @subid 279 + @subid 309 @conv { diff --git a/plugins/arm/v7/opdefs/mov_A88102.d b/plugins/arm/v7/opdefs/mov_A88102.d index f68fed6..805bc16 100644 --- a/plugins/arm/v7/opdefs/mov_A88102.d +++ b/plugins/arm/v7/opdefs/mov_A88102.d @@ -37,7 +37,7 @@ @syntax { - @subid 280 + @subid 310 @conv { @@ -58,7 +58,7 @@ @syntax { - @subid 281 + @subid 311 @assert { @@ -79,7 +79,7 @@ @syntax { - @subid 282 + @subid 312 @assert { @@ -106,7 +106,7 @@ @syntax { - @subid 283 + @subid 313 @conv { @@ -127,7 +127,7 @@ @syntax { - @subid 284 + @subid 314 @assert { @@ -154,7 +154,7 @@ @syntax { - @subid 285 + @subid 315 @assert { @@ -187,7 +187,7 @@ @syntax { - @subid 286 + @subid 316 @conv { diff --git a/plugins/arm/v7/opdefs/mov_A88103.d b/plugins/arm/v7/opdefs/mov_A88103.d index c4a9f97..9497800 100644 --- a/plugins/arm/v7/opdefs/mov_A88103.d +++ b/plugins/arm/v7/opdefs/mov_A88103.d @@ -37,7 +37,7 @@ @syntax { - @subid 287 + @subid 317 @conv { @@ -58,7 +58,7 @@ @syntax { - @subid 288 + @subid 318 @conv { @@ -79,7 +79,7 @@ @syntax { - @subid 289 + @subid 319 @assert { @@ -100,7 +100,7 @@ @syntax { - @subid 290 + @subid 320 @assert { diff --git a/plugins/arm/v7/opdefs/mov_A88104.d b/plugins/arm/v7/opdefs/mov_A88104.d index c619baa..3d7eb99 100644 --- a/plugins/arm/v7/opdefs/mov_A88104.d +++ b/plugins/arm/v7/opdefs/mov_A88104.d @@ -37,7 +37,7 @@ @syntax { - @subid 291 + @subid 321 @assert { @@ -64,7 +64,7 @@ @syntax { - @subid 292 + @subid 322 @assert { diff --git a/plugins/arm/v7/opdefs/movt_A88106.d b/plugins/arm/v7/opdefs/movt_A88106.d index 852b745..dc024df 100644 --- a/plugins/arm/v7/opdefs/movt_A88106.d +++ b/plugins/arm/v7/opdefs/movt_A88106.d @@ -37,7 +37,7 @@ @syntax { - @subid 293 + @subid 323 @conv { @@ -58,7 +58,7 @@ @syntax { - @subid 294 + @subid 324 @conv { diff --git a/plugins/arm/v7/opdefs/mrc_A88107.d b/plugins/arm/v7/opdefs/mrc_A88107.d index 04591e7..ab3f0a1 100644 --- a/plugins/arm/v7/opdefs/mrc_A88107.d +++ b/plugins/arm/v7/opdefs/mrc_A88107.d @@ -37,7 +37,7 @@ @syntax { - @subid 295 + @subid 325 @conv { @@ -62,7 +62,7 @@ @syntax { - @subid 296 + @subid 326 @conv { @@ -87,7 +87,7 @@ @syntax { - @subid 297 + @subid 327 @conv { @@ -112,7 +112,7 @@ @syntax { - @subid 298 + @subid 328 @conv { diff --git a/plugins/arm/v7/opdefs/mrrc_A88108.d b/plugins/arm/v7/opdefs/mrrc_A88108.d index 0e33e6c..ea25147 100644 --- a/plugins/arm/v7/opdefs/mrrc_A88108.d +++ b/plugins/arm/v7/opdefs/mrrc_A88108.d @@ -37,7 +37,7 @@ @syntax { - @subid 299 + @subid 329 @conv { @@ -61,7 +61,7 @@ @syntax { - @subid 300 + @subid 330 @conv { @@ -85,7 +85,7 @@ @syntax { - @subid 301 + @subid 331 @conv { @@ -109,7 +109,7 @@ @syntax { - @subid 302 + @subid 332 @conv { diff --git a/plugins/arm/v7/opdefs/mrs_A88109.d b/plugins/arm/v7/opdefs/mrs_A88109.d new file mode 100644 index 0000000..6ea0208 --- /dev/null +++ b/plugins/arm/v7/opdefs/mrs_A88109.d @@ -0,0 +1,81 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title MRS + +@id 108 + +@desc { + + Move to Register from Special register moves the value from the APSR into an ARM core register. For details of system level use of this instruction, see MRS on page B9-1988. + +} + +@encoding (T1) { + + @word 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 1 1 0 0 0 Rd(4) 0 0 0 0 0 0 0 0 + + @syntax { + + @subid 333 + + @conv { + + reg_D = Register(Rd) + spec_reg = SpecRegAPSR() + + } + + @asm mrs reg_D spec_reg + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 0 0 0 1 1 1 1 Rd(4) 0 0 0 0 0 0 0 0 0 0 0 0 + + @syntax { + + @subid 334 + + @conv { + + reg_D = Register(Rd) + spec_reg = SpecRegAPSR() + + } + + @asm mrs reg_D spec_reg + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/msr_A88111.d b/plugins/arm/v7/opdefs/msr_A88111.d new file mode 100644 index 0000000..ccf86df --- /dev/null +++ b/plugins/arm/v7/opdefs/msr_A88111.d @@ -0,0 +1,60 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title MSR (immediate) + +@id 110 + +@desc { + + Move immediate value to Special register moves selected bits of an immediate value to the corresponding bits in the APSR. For details of system level use of this instruction, see MSR (immediate) on page B9-1994. + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 1 0 0 1 0 mask(2) 0 0 1 1 1 1 imm12(12) + + @syntax { + + @subid 335 + + @conv { + + spec_reg = SpecRegFromMask(mask) + imm32 = ARMExpandImm(imm12) + + } + + @asm msr spec_reg imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/msr_A88112.d b/plugins/arm/v7/opdefs/msr_A88112.d new file mode 100644 index 0000000..89aedc3 --- /dev/null +++ b/plugins/arm/v7/opdefs/msr_A88112.d @@ -0,0 +1,81 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title MSR (register) + +@id 111 + +@desc { + + Move to Special register from ARM core register moves selected bits of an ARM core register to the APSR. For details of system level use of this instruction, see MSR (register) on page B9-1996. + +} + +@encoding (T1) { + + @word 1 1 1 1 0 0 1 1 1 0 0 0 Rn(4) 1 0 0 0 mask(2) 0 0 0 0 0 0 0 0 0 0 + + @syntax { + + @subid 336 + + @conv { + + spec_reg = SpecRegFromMask(mask) + reg_N = Register(Rn) + + } + + @asm msr spec_reg reg_N + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 0 1 0 mask(2) 0 0 1 1 1 1 0 0 0 0 0 0 0 0 Rn(4) + + @syntax { + + @subid 337 + + @conv { + + spec_reg = SpecRegFromMask(mask) + reg_N = Register(Rn) + + } + + @asm msr spec_reg reg_N + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/mul_A88114.d b/plugins/arm/v7/opdefs/mul_A88114.d index a246a56..9eb245f 100644 --- a/plugins/arm/v7/opdefs/mul_A88114.d +++ b/plugins/arm/v7/opdefs/mul_A88114.d @@ -37,7 +37,7 @@ @syntax { - @subid 303 + @subid 338 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 304 + @subid 339 @conv { @@ -81,7 +81,7 @@ @syntax { - @subid 305 + @subid 340 @assert { @@ -109,7 +109,7 @@ @syntax { - @subid 306 + @subid 341 @assert { diff --git a/plugins/arm/v7/opdefs/mvn_A88115.d b/plugins/arm/v7/opdefs/mvn_A88115.d index 5c23abb..23d9525 100644 --- a/plugins/arm/v7/opdefs/mvn_A88115.d +++ b/plugins/arm/v7/opdefs/mvn_A88115.d @@ -37,7 +37,7 @@ @syntax { - @subid 307 + @subid 342 @assert { @@ -58,7 +58,7 @@ @syntax { - @subid 308 + @subid 343 @assert { @@ -85,7 +85,7 @@ @syntax { - @subid 309 + @subid 344 @assert { @@ -112,7 +112,7 @@ @syntax { - @subid 310 + @subid 345 @assert { diff --git a/plugins/arm/v7/opdefs/mvn_A88116.d b/plugins/arm/v7/opdefs/mvn_A88116.d index 25185c9..db9e070 100644 --- a/plugins/arm/v7/opdefs/mvn_A88116.d +++ b/plugins/arm/v7/opdefs/mvn_A88116.d @@ -37,7 +37,7 @@ @syntax { - @subid 311 + @subid 346 @conv { @@ -58,7 +58,7 @@ @syntax { - @subid 312 + @subid 347 @assert { @@ -80,7 +80,7 @@ @syntax { - @subid 313 + @subid 348 @assert { @@ -108,7 +108,7 @@ @syntax { - @subid 314 + @subid 349 @assert { @@ -136,7 +136,7 @@ @syntax { - @subid 315 + @subid 350 @assert { diff --git a/plugins/arm/v7/opdefs/mvn_A88117.d b/plugins/arm/v7/opdefs/mvn_A88117.d index 813d735..8e88096 100644 --- a/plugins/arm/v7/opdefs/mvn_A88117.d +++ b/plugins/arm/v7/opdefs/mvn_A88117.d @@ -37,7 +37,7 @@ @syntax { - @subid 316 + @subid 351 @assert { @@ -67,7 +67,7 @@ @syntax { - @subid 317 + @subid 352 @assert { diff --git a/plugins/arm/v7/opdefs/nop_A88119.d b/plugins/arm/v7/opdefs/nop_A88119.d index 1ea0e96..8efcb03 100644 --- a/plugins/arm/v7/opdefs/nop_A88119.d +++ b/plugins/arm/v7/opdefs/nop_A88119.d @@ -37,7 +37,7 @@ @syntax { - @subid 318 + @subid 353 @asm nop @@ -51,7 +51,7 @@ @syntax { - @subid 319 + @subid 354 @asm nop.w @@ -65,7 +65,7 @@ @syntax { - @subid 320 + @subid 355 @asm nop diff --git a/plugins/arm/v7/opdefs/orn_A88120.d b/plugins/arm/v7/opdefs/orn_A88120.d index 4f3091c..b90857d 100644 --- a/plugins/arm/v7/opdefs/orn_A88120.d +++ b/plugins/arm/v7/opdefs/orn_A88120.d @@ -37,7 +37,7 @@ @syntax { - @subid 321 + @subid 356 @assert { @@ -59,7 +59,7 @@ @syntax { - @subid 322 + @subid 357 @assert { diff --git a/plugins/arm/v7/opdefs/orn_A88121.d b/plugins/arm/v7/opdefs/orn_A88121.d index fcc9898..4e98abe 100644 --- a/plugins/arm/v7/opdefs/orn_A88121.d +++ b/plugins/arm/v7/opdefs/orn_A88121.d @@ -37,7 +37,7 @@ @syntax { - @subid 323 + @subid 358 @assert { @@ -60,7 +60,7 @@ @syntax { - @subid 324 + @subid 359 @assert { diff --git a/plugins/arm/v7/opdefs/orr_A88122.d b/plugins/arm/v7/opdefs/orr_A88122.d index be54518..9855ad2 100644 --- a/plugins/arm/v7/opdefs/orr_A88122.d +++ b/plugins/arm/v7/opdefs/orr_A88122.d @@ -37,7 +37,7 @@ @syntax { - @subid 325 + @subid 360 @assert { @@ -59,7 +59,7 @@ @syntax { - @subid 326 + @subid 361 @assert { @@ -87,7 +87,7 @@ @syntax { - @subid 327 + @subid 362 @assert { @@ -115,7 +115,7 @@ @syntax { - @subid 328 + @subid 363 @assert { diff --git a/plugins/arm/v7/opdefs/orr_A88123.d b/plugins/arm/v7/opdefs/orr_A88123.d index 923b766..0a28002 100644 --- a/plugins/arm/v7/opdefs/orr_A88123.d +++ b/plugins/arm/v7/opdefs/orr_A88123.d @@ -37,7 +37,7 @@ @syntax { - @subid 329 + @subid 364 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 330 + @subid 365 @assert { @@ -82,7 +82,7 @@ @syntax { - @subid 331 + @subid 366 @assert { @@ -111,7 +111,7 @@ @syntax { - @subid 332 + @subid 367 @assert { @@ -140,7 +140,7 @@ @syntax { - @subid 333 + @subid 368 @assert { diff --git a/plugins/arm/v7/opdefs/orr_A88124.d b/plugins/arm/v7/opdefs/orr_A88124.d index 85ddeba..adc1d42 100644 --- a/plugins/arm/v7/opdefs/orr_A88124.d +++ b/plugins/arm/v7/opdefs/orr_A88124.d @@ -37,7 +37,7 @@ @syntax { - @subid 334 + @subid 369 @assert { @@ -68,7 +68,7 @@ @syntax { - @subid 335 + @subid 370 @assert { diff --git a/plugins/arm/v7/opdefs/pkh_A88125.d b/plugins/arm/v7/opdefs/pkh_A88125.d index 76c185c..1ca6a30 100644 --- a/plugins/arm/v7/opdefs/pkh_A88125.d +++ b/plugins/arm/v7/opdefs/pkh_A88125.d @@ -37,7 +37,7 @@ @syntax { - @subid 336 + @subid 371 @assert { @@ -60,7 +60,7 @@ @syntax { - @subid 337 + @subid 372 @assert { @@ -89,7 +89,7 @@ @syntax { - @subid 338 + @subid 373 @assert { @@ -118,7 +118,7 @@ @syntax { - @subid 339 + @subid 374 @assert { diff --git a/plugins/arm/v7/opdefs/pld_A88126.d b/plugins/arm/v7/opdefs/pld_A88126.d index 7e4994f..3a82fe4 100644 --- a/plugins/arm/v7/opdefs/pld_A88126.d +++ b/plugins/arm/v7/opdefs/pld_A88126.d @@ -37,7 +37,7 @@ @syntax { - @subid 340 + @subid 375 @assert { @@ -59,7 +59,7 @@ @syntax { - @subid 341 + @subid 376 @assert { @@ -87,7 +87,7 @@ @syntax { - @subid 342 + @subid 377 @assert { @@ -109,7 +109,7 @@ @syntax { - @subid 343 + @subid 378 @assert { @@ -137,7 +137,7 @@ @syntax { - @subid 344 + @subid 379 @assert { @@ -159,7 +159,7 @@ @syntax { - @subid 345 + @subid 380 @assert { diff --git a/plugins/arm/v7/opdefs/pld_A88127.d b/plugins/arm/v7/opdefs/pld_A88127.d index 49f27c8..e753579 100644 --- a/plugins/arm/v7/opdefs/pld_A88127.d +++ b/plugins/arm/v7/opdefs/pld_A88127.d @@ -37,7 +37,7 @@ @syntax { - @subid 346 + @subid 381 @conv { @@ -57,7 +57,7 @@ @syntax { - @subid 347 + @subid 382 @conv { diff --git a/plugins/arm/v7/opdefs/pld_A88128.d b/plugins/arm/v7/opdefs/pld_A88128.d index 50c9bc8..5c7eb2d 100644 --- a/plugins/arm/v7/opdefs/pld_A88128.d +++ b/plugins/arm/v7/opdefs/pld_A88128.d @@ -37,7 +37,7 @@ @syntax { - @subid 348 + @subid 383 @assert { @@ -60,7 +60,7 @@ @syntax { - @subid 349 + @subid 384 @assert { @@ -89,7 +89,7 @@ @syntax { - @subid 350 + @subid 385 @assert { @@ -112,7 +112,7 @@ @syntax { - @subid 351 + @subid 386 @assert { diff --git a/plugins/arm/v7/opdefs/pli_A88130.d b/plugins/arm/v7/opdefs/pli_A88130.d new file mode 100644 index 0000000..e669ff8 --- /dev/null +++ b/plugins/arm/v7/opdefs/pli_A88130.d @@ -0,0 +1,79 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title PLI (register) + +@id 129 + +@desc { + + Preload Instruction signals the memory system that instruction memory accesses from a specified address are likely in the near future. The memory system can respond by taking actions that are expected to speed up the memory accesses when they do occur, such as pre-loading the cache line containing the specified address into the instruction cache. For more information, see Behavior of Preload Data (PLD, PLDW) and Preload Instruction (PLI) with caches on page B2-1269. The effect of a PLI instruction is IMPLEMENTATION DEFINED. For more information, see Preloading caches on page A3-157 and Behavior of Preload Data (PLD, PLDW) and Preload Instruction (PLI) with caches on page B2-1269. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 1 0 0 0 1 Rn(4) 1 1 1 1 0 0 0 0 0 0 imm2(2) Rm(4) + + @syntax { + + @subid 387 + + @conv { + + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = FixedShift(SRType_LSL, imm2) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) + + } + + @asm pli maccess + + } + +} + +@encoding (A1) { + + @word 1 1 1 1 0 1 1 0 U(1) 1 0 1 Rn(4) 1 1 1 1 imm5(5) type(2) 0 Rm(4) + + @syntax { + + @subid 388 + + @conv { + + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) + + } + + @asm pli maccess + + } + +} + diff --git a/plugins/arm/v7/opdefs/pop_A88131.d b/plugins/arm/v7/opdefs/pop_A88131.d index 2881669..12f1254 100644 --- a/plugins/arm/v7/opdefs/pop_A88131.d +++ b/plugins/arm/v7/opdefs/pop_A88131.d @@ -37,7 +37,7 @@ @syntax { - @subid 352 + @subid 389 @conv { @@ -63,7 +63,7 @@ @syntax { - @subid 353 + @subid 390 @conv { @@ -89,7 +89,7 @@ @syntax { - @subid 354 + @subid 391 @conv { diff --git a/plugins/arm/v7/opdefs/pop_A88132.d b/plugins/arm/v7/opdefs/pop_A88132.d index 2cdfdfe..f4e681e 100644 --- a/plugins/arm/v7/opdefs/pop_A88132.d +++ b/plugins/arm/v7/opdefs/pop_A88132.d @@ -37,7 +37,7 @@ @syntax { - @subid 355 + @subid 392 @conv { @@ -69,7 +69,7 @@ @syntax { - @subid 356 + @subid 393 @conv { diff --git a/plugins/arm/v7/opdefs/push_A88133.d b/plugins/arm/v7/opdefs/push_A88133.d index 91be90b..6240e66 100644 --- a/plugins/arm/v7/opdefs/push_A88133.d +++ b/plugins/arm/v7/opdefs/push_A88133.d @@ -37,7 +37,7 @@ @syntax { - @subid 357 + @subid 394 @conv { @@ -57,7 +57,7 @@ @syntax { - @subid 358 + @subid 395 @conv { @@ -77,7 +77,7 @@ @syntax { - @subid 359 + @subid 396 @conv { @@ -97,7 +97,7 @@ @syntax { - @subid 360 + @subid 397 @conv { @@ -123,7 +123,7 @@ @syntax { - @subid 361 + @subid 398 @conv { diff --git a/plugins/arm/v7/opdefs/qadd16_A88135.d b/plugins/arm/v7/opdefs/qadd16_A88135.d index 175ffe4..4bcaff9 100644 --- a/plugins/arm/v7/opdefs/qadd16_A88135.d +++ b/plugins/arm/v7/opdefs/qadd16_A88135.d @@ -37,7 +37,7 @@ @syntax { - @subid 364 + @subid 401 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 365 + @subid 402 @conv { diff --git a/plugins/arm/v7/opdefs/qadd8_A88136.d b/plugins/arm/v7/opdefs/qadd8_A88136.d index 6a6fd13..7ceda6a 100644 --- a/plugins/arm/v7/opdefs/qadd8_A88136.d +++ b/plugins/arm/v7/opdefs/qadd8_A88136.d @@ -37,7 +37,7 @@ @syntax { - @subid 366 + @subid 403 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 367 + @subid 404 @conv { diff --git a/plugins/arm/v7/opdefs/qadd_A88134.d b/plugins/arm/v7/opdefs/qadd_A88134.d index ab57530..11d86b1 100644 --- a/plugins/arm/v7/opdefs/qadd_A88134.d +++ b/plugins/arm/v7/opdefs/qadd_A88134.d @@ -37,7 +37,7 @@ @syntax { - @subid 362 + @subid 399 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 363 + @subid 400 @conv { diff --git a/plugins/arm/v7/opdefs/qasx_A88137.d b/plugins/arm/v7/opdefs/qasx_A88137.d index ed856ae..4c62bca 100644 --- a/plugins/arm/v7/opdefs/qasx_A88137.d +++ b/plugins/arm/v7/opdefs/qasx_A88137.d @@ -37,7 +37,7 @@ @syntax { - @subid 368 + @subid 405 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 369 + @subid 406 @conv { diff --git a/plugins/arm/v7/opdefs/qdadd_A88138.d b/plugins/arm/v7/opdefs/qdadd_A88138.d index cb32dab..8f49b67 100644 --- a/plugins/arm/v7/opdefs/qdadd_A88138.d +++ b/plugins/arm/v7/opdefs/qdadd_A88138.d @@ -37,7 +37,7 @@ @syntax { - @subid 370 + @subid 407 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 371 + @subid 408 @conv { diff --git a/plugins/arm/v7/opdefs/qdsub_A88139.d b/plugins/arm/v7/opdefs/qdsub_A88139.d index b510e45..2747f27 100644 --- a/plugins/arm/v7/opdefs/qdsub_A88139.d +++ b/plugins/arm/v7/opdefs/qdsub_A88139.d @@ -37,7 +37,7 @@ @syntax { - @subid 372 + @subid 409 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 373 + @subid 410 @conv { diff --git a/plugins/arm/v7/opdefs/qsax_A88140.d b/plugins/arm/v7/opdefs/qsax_A88140.d index 4953c88..f8217b2 100644 --- a/plugins/arm/v7/opdefs/qsax_A88140.d +++ b/plugins/arm/v7/opdefs/qsax_A88140.d @@ -37,7 +37,7 @@ @syntax { - @subid 374 + @subid 411 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 375 + @subid 412 @conv { diff --git a/plugins/arm/v7/opdefs/qsub16_A88142.d b/plugins/arm/v7/opdefs/qsub16_A88142.d index 5a9c950..b971c85 100644 --- a/plugins/arm/v7/opdefs/qsub16_A88142.d +++ b/plugins/arm/v7/opdefs/qsub16_A88142.d @@ -37,7 +37,7 @@ @syntax { - @subid 378 + @subid 415 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 379 + @subid 416 @conv { diff --git a/plugins/arm/v7/opdefs/qsub8_A88143.d b/plugins/arm/v7/opdefs/qsub8_A88143.d index 518cde9..d7f96c7 100644 --- a/plugins/arm/v7/opdefs/qsub8_A88143.d +++ b/plugins/arm/v7/opdefs/qsub8_A88143.d @@ -37,7 +37,7 @@ @syntax { - @subid 380 + @subid 417 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 381 + @subid 418 @conv { diff --git a/plugins/arm/v7/opdefs/qsub_A88141.d b/plugins/arm/v7/opdefs/qsub_A88141.d index 9fc14da..89d034b 100644 --- a/plugins/arm/v7/opdefs/qsub_A88141.d +++ b/plugins/arm/v7/opdefs/qsub_A88141.d @@ -37,7 +37,7 @@ @syntax { - @subid 376 + @subid 413 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 377 + @subid 414 @conv { diff --git a/plugins/arm/v7/opdefs/rbit_A88144.d b/plugins/arm/v7/opdefs/rbit_A88144.d index b868310..b5c610c 100644 --- a/plugins/arm/v7/opdefs/rbit_A88144.d +++ b/plugins/arm/v7/opdefs/rbit_A88144.d @@ -37,7 +37,7 @@ @syntax { - @subid 382 + @subid 419 @conv { @@ -58,7 +58,7 @@ @syntax { - @subid 383 + @subid 420 @conv { diff --git a/plugins/arm/v7/opdefs/rev16_A88146.d b/plugins/arm/v7/opdefs/rev16_A88146.d index adb8f0b..49821e5 100644 --- a/plugins/arm/v7/opdefs/rev16_A88146.d +++ b/plugins/arm/v7/opdefs/rev16_A88146.d @@ -37,7 +37,7 @@ @syntax { - @subid 387 + @subid 424 @conv { @@ -58,7 +58,7 @@ @syntax { - @subid 388 + @subid 425 @conv { @@ -79,7 +79,7 @@ @syntax { - @subid 389 + @subid 426 @conv { diff --git a/plugins/arm/v7/opdefs/rev_A88145.d b/plugins/arm/v7/opdefs/rev_A88145.d index 392e90c..cb81837 100644 --- a/plugins/arm/v7/opdefs/rev_A88145.d +++ b/plugins/arm/v7/opdefs/rev_A88145.d @@ -37,7 +37,7 @@ @syntax { - @subid 384 + @subid 421 @conv { @@ -58,7 +58,7 @@ @syntax { - @subid 385 + @subid 422 @conv { @@ -79,7 +79,7 @@ @syntax { - @subid 386 + @subid 423 @conv { diff --git a/plugins/arm/v7/opdefs/revsh_A88147.d b/plugins/arm/v7/opdefs/revsh_A88147.d index 37df8b8..bf04a89 100644 --- a/plugins/arm/v7/opdefs/revsh_A88147.d +++ b/plugins/arm/v7/opdefs/revsh_A88147.d @@ -37,7 +37,7 @@ @syntax { - @subid 390 + @subid 427 @conv { @@ -58,7 +58,7 @@ @syntax { - @subid 391 + @subid 428 @conv { @@ -79,7 +79,7 @@ @syntax { - @subid 392 + @subid 429 @conv { diff --git a/plugins/arm/v7/opdefs/ror_A88149.d b/plugins/arm/v7/opdefs/ror_A88149.d index 5cb9893..98735fd 100644 --- a/plugins/arm/v7/opdefs/ror_A88149.d +++ b/plugins/arm/v7/opdefs/ror_A88149.d @@ -37,7 +37,7 @@ @syntax { - @subid 393 + @subid 430 @assert { @@ -59,7 +59,7 @@ @syntax { - @subid 394 + @subid 431 @assert { @@ -87,7 +87,7 @@ @syntax { - @subid 395 + @subid 432 @assert { @@ -115,7 +115,7 @@ @syntax { - @subid 396 + @subid 433 @assert { diff --git a/plugins/arm/v7/opdefs/ror_A88150.d b/plugins/arm/v7/opdefs/ror_A88150.d index 5c62d28..031f56e 100644 --- a/plugins/arm/v7/opdefs/ror_A88150.d +++ b/plugins/arm/v7/opdefs/ror_A88150.d @@ -37,7 +37,7 @@ @syntax { - @subid 397 + @subid 434 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 398 + @subid 435 @assert { @@ -81,7 +81,7 @@ @syntax { - @subid 399 + @subid 436 @assert { @@ -109,7 +109,7 @@ @syntax { - @subid 400 + @subid 437 @assert { @@ -137,7 +137,7 @@ @syntax { - @subid 401 + @subid 438 @assert { diff --git a/plugins/arm/v7/opdefs/rrx_A88151.d b/plugins/arm/v7/opdefs/rrx_A88151.d index 1e26aa3..445a5d3 100644 --- a/plugins/arm/v7/opdefs/rrx_A88151.d +++ b/plugins/arm/v7/opdefs/rrx_A88151.d @@ -37,7 +37,7 @@ @syntax { - @subid 402 + @subid 439 @assert { @@ -58,7 +58,7 @@ @syntax { - @subid 403 + @subid 440 @assert { @@ -85,7 +85,7 @@ @syntax { - @subid 404 + @subid 441 @assert { @@ -112,7 +112,7 @@ @syntax { - @subid 405 + @subid 442 @assert { diff --git a/plugins/arm/v7/opdefs/rsb_A88152.d b/plugins/arm/v7/opdefs/rsb_A88152.d index 6eb7139..9b5e13e 100644 --- a/plugins/arm/v7/opdefs/rsb_A88152.d +++ b/plugins/arm/v7/opdefs/rsb_A88152.d @@ -37,7 +37,7 @@ @syntax { - @subid 406 + @subid 443 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 407 + @subid 444 @assert { @@ -81,7 +81,7 @@ @syntax { - @subid 408 + @subid 445 @assert { @@ -109,7 +109,7 @@ @syntax { - @subid 409 + @subid 446 @assert { @@ -137,7 +137,7 @@ @syntax { - @subid 410 + @subid 447 @assert { diff --git a/plugins/arm/v7/opdefs/rsb_A88153.d b/plugins/arm/v7/opdefs/rsb_A88153.d index a1fc0cc..cb8ad6d 100644 --- a/plugins/arm/v7/opdefs/rsb_A88153.d +++ b/plugins/arm/v7/opdefs/rsb_A88153.d @@ -37,7 +37,7 @@ @syntax { - @subid 411 + @subid 448 @assert { @@ -60,7 +60,7 @@ @syntax { - @subid 412 + @subid 449 @assert { @@ -89,7 +89,7 @@ @syntax { - @subid 413 + @subid 450 @assert { @@ -118,7 +118,7 @@ @syntax { - @subid 414 + @subid 451 @assert { diff --git a/plugins/arm/v7/opdefs/rsb_A88154.d b/plugins/arm/v7/opdefs/rsb_A88154.d index c35f396..cfc0a11 100644 --- a/plugins/arm/v7/opdefs/rsb_A88154.d +++ b/plugins/arm/v7/opdefs/rsb_A88154.d @@ -37,7 +37,7 @@ @syntax { - @subid 415 + @subid 452 @assert { @@ -68,7 +68,7 @@ @syntax { - @subid 416 + @subid 453 @assert { diff --git a/plugins/arm/v7/opdefs/rsc_A88155.d b/plugins/arm/v7/opdefs/rsc_A88155.d index e9eb02d..e30a4a1 100644 --- a/plugins/arm/v7/opdefs/rsc_A88155.d +++ b/plugins/arm/v7/opdefs/rsc_A88155.d @@ -37,7 +37,7 @@ @syntax { - @subid 417 + @subid 454 @assert { @@ -65,7 +65,7 @@ @syntax { - @subid 418 + @subid 455 @assert { diff --git a/plugins/arm/v7/opdefs/rsc_A88156.d b/plugins/arm/v7/opdefs/rsc_A88156.d index e97f13e..63d39fb 100644 --- a/plugins/arm/v7/opdefs/rsc_A88156.d +++ b/plugins/arm/v7/opdefs/rsc_A88156.d @@ -37,7 +37,7 @@ @syntax { - @subid 419 + @subid 456 @assert { @@ -66,7 +66,7 @@ @syntax { - @subid 420 + @subid 457 @assert { diff --git a/plugins/arm/v7/opdefs/rsc_A88157.d b/plugins/arm/v7/opdefs/rsc_A88157.d index 1280b3f..25d1ea2 100644 --- a/plugins/arm/v7/opdefs/rsc_A88157.d +++ b/plugins/arm/v7/opdefs/rsc_A88157.d @@ -37,7 +37,7 @@ @syntax { - @subid 421 + @subid 458 @assert { @@ -68,7 +68,7 @@ @syntax { - @subid 422 + @subid 459 @assert { diff --git a/plugins/arm/v7/opdefs/sadd16_A88158.d b/plugins/arm/v7/opdefs/sadd16_A88158.d index 9fa7760..b181221 100644 --- a/plugins/arm/v7/opdefs/sadd16_A88158.d +++ b/plugins/arm/v7/opdefs/sadd16_A88158.d @@ -37,7 +37,7 @@ @syntax { - @subid 423 + @subid 460 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 424 + @subid 461 @conv { diff --git a/plugins/arm/v7/opdefs/sadd8_A88159.d b/plugins/arm/v7/opdefs/sadd8_A88159.d index 3420e45..94a91d7 100644 --- a/plugins/arm/v7/opdefs/sadd8_A88159.d +++ b/plugins/arm/v7/opdefs/sadd8_A88159.d @@ -37,7 +37,7 @@ @syntax { - @subid 425 + @subid 462 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 426 + @subid 463 @conv { diff --git a/plugins/arm/v7/opdefs/sasx_A88160.d b/plugins/arm/v7/opdefs/sasx_A88160.d index 1056630..30c86be 100644 --- a/plugins/arm/v7/opdefs/sasx_A88160.d +++ b/plugins/arm/v7/opdefs/sasx_A88160.d @@ -37,7 +37,7 @@ @syntax { - @subid 427 + @subid 464 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 428 + @subid 465 @conv { diff --git a/plugins/arm/v7/opdefs/sbc_A88161.d b/plugins/arm/v7/opdefs/sbc_A88161.d index 8243825..8d307fa 100644 --- a/plugins/arm/v7/opdefs/sbc_A88161.d +++ b/plugins/arm/v7/opdefs/sbc_A88161.d @@ -37,7 +37,7 @@ @syntax { - @subid 429 + @subid 466 @assert { @@ -59,7 +59,7 @@ @syntax { - @subid 430 + @subid 467 @assert { @@ -87,7 +87,7 @@ @syntax { - @subid 431 + @subid 468 @assert { @@ -115,7 +115,7 @@ @syntax { - @subid 432 + @subid 469 @assert { diff --git a/plugins/arm/v7/opdefs/sbc_A88162.d b/plugins/arm/v7/opdefs/sbc_A88162.d index 4504b1a..27f97fc 100644 --- a/plugins/arm/v7/opdefs/sbc_A88162.d +++ b/plugins/arm/v7/opdefs/sbc_A88162.d @@ -37,7 +37,7 @@ @syntax { - @subid 433 + @subid 470 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 434 + @subid 471 @assert { @@ -82,7 +82,7 @@ @syntax { - @subid 435 + @subid 472 @assert { @@ -111,7 +111,7 @@ @syntax { - @subid 436 + @subid 473 @assert { @@ -140,7 +140,7 @@ @syntax { - @subid 437 + @subid 474 @assert { diff --git a/plugins/arm/v7/opdefs/sbc_A88163.d b/plugins/arm/v7/opdefs/sbc_A88163.d index 5d54b34..a7e7c27 100644 --- a/plugins/arm/v7/opdefs/sbc_A88163.d +++ b/plugins/arm/v7/opdefs/sbc_A88163.d @@ -37,7 +37,7 @@ @syntax { - @subid 438 + @subid 475 @assert { @@ -68,7 +68,7 @@ @syntax { - @subid 439 + @subid 476 @assert { diff --git a/plugins/arm/v7/opdefs/sbfx_A88164.d b/plugins/arm/v7/opdefs/sbfx_A88164.d index c28c39c..8a3f4de 100644 --- a/plugins/arm/v7/opdefs/sbfx_A88164.d +++ b/plugins/arm/v7/opdefs/sbfx_A88164.d @@ -37,7 +37,7 @@ @syntax { - @subid 440 + @subid 477 @conv { @@ -61,7 +61,7 @@ @syntax { - @subid 441 + @subid 478 @conv { diff --git a/plugins/arm/v7/opdefs/sdiv_A88165.d b/plugins/arm/v7/opdefs/sdiv_A88165.d index 2852046..0e74d6c 100644 --- a/plugins/arm/v7/opdefs/sdiv_A88165.d +++ b/plugins/arm/v7/opdefs/sdiv_A88165.d @@ -37,7 +37,7 @@ @syntax { - @subid 442 + @subid 479 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 443 + @subid 480 @conv { diff --git a/plugins/arm/v7/opdefs/sel_A88166.d b/plugins/arm/v7/opdefs/sel_A88166.d index 5b5e332..660dd46 100644 --- a/plugins/arm/v7/opdefs/sel_A88166.d +++ b/plugins/arm/v7/opdefs/sel_A88166.d @@ -37,7 +37,7 @@ @syntax { - @subid 444 + @subid 481 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 445 + @subid 482 @conv { diff --git a/plugins/arm/v7/opdefs/setend_A88167.d b/plugins/arm/v7/opdefs/setend_A88167.d index 1e6de01..ac6d59b 100644 --- a/plugins/arm/v7/opdefs/setend_A88167.d +++ b/plugins/arm/v7/opdefs/setend_A88167.d @@ -37,7 +37,7 @@ @syntax { - @subid 446 + @subid 483 @conv { @@ -57,7 +57,7 @@ @syntax { - @subid 447 + @subid 484 @conv { diff --git a/plugins/arm/v7/opdefs/sev_A88168.d b/plugins/arm/v7/opdefs/sev_A88168.d index 90f6056..8695ace 100644 --- a/plugins/arm/v7/opdefs/sev_A88168.d +++ b/plugins/arm/v7/opdefs/sev_A88168.d @@ -37,7 +37,7 @@ @syntax { - @subid 448 + @subid 485 @asm sev @@ -51,7 +51,7 @@ @syntax { - @subid 449 + @subid 486 @asm sev.w @@ -65,7 +65,7 @@ @syntax { - @subid 450 + @subid 487 @asm sev diff --git a/plugins/arm/v7/opdefs/shadd16_A88169.d b/plugins/arm/v7/opdefs/shadd16_A88169.d index 98c6768..0ecbd43 100644 --- a/plugins/arm/v7/opdefs/shadd16_A88169.d +++ b/plugins/arm/v7/opdefs/shadd16_A88169.d @@ -37,7 +37,7 @@ @syntax { - @subid 451 + @subid 488 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 452 + @subid 489 @conv { diff --git a/plugins/arm/v7/opdefs/shadd8_A88170.d b/plugins/arm/v7/opdefs/shadd8_A88170.d index 71cc9cf..c1d358a 100644 --- a/plugins/arm/v7/opdefs/shadd8_A88170.d +++ b/plugins/arm/v7/opdefs/shadd8_A88170.d @@ -37,7 +37,7 @@ @syntax { - @subid 453 + @subid 490 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 454 + @subid 491 @conv { diff --git a/plugins/arm/v7/opdefs/shasx_A88171.d b/plugins/arm/v7/opdefs/shasx_A88171.d index d808b25..b48ef07 100644 --- a/plugins/arm/v7/opdefs/shasx_A88171.d +++ b/plugins/arm/v7/opdefs/shasx_A88171.d @@ -37,7 +37,7 @@ @syntax { - @subid 455 + @subid 492 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 456 + @subid 493 @conv { diff --git a/plugins/arm/v7/opdefs/shsax_A88172.d b/plugins/arm/v7/opdefs/shsax_A88172.d index 59641e3..f9d0742 100644 --- a/plugins/arm/v7/opdefs/shsax_A88172.d +++ b/plugins/arm/v7/opdefs/shsax_A88172.d @@ -37,7 +37,7 @@ @syntax { - @subid 457 + @subid 494 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 458 + @subid 495 @conv { diff --git a/plugins/arm/v7/opdefs/shsub16_A88173.d b/plugins/arm/v7/opdefs/shsub16_A88173.d index 03bbbe8..802def4 100644 --- a/plugins/arm/v7/opdefs/shsub16_A88173.d +++ b/plugins/arm/v7/opdefs/shsub16_A88173.d @@ -37,7 +37,7 @@ @syntax { - @subid 459 + @subid 496 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 460 + @subid 497 @conv { diff --git a/plugins/arm/v7/opdefs/shsub8_A88174.d b/plugins/arm/v7/opdefs/shsub8_A88174.d index e0df718..a4113db 100644 --- a/plugins/arm/v7/opdefs/shsub8_A88174.d +++ b/plugins/arm/v7/opdefs/shsub8_A88174.d @@ -37,7 +37,7 @@ @syntax { - @subid 461 + @subid 498 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 462 + @subid 499 @conv { diff --git a/plugins/arm/v7/opdefs/smla_A88176.d b/plugins/arm/v7/opdefs/smla_A88176.d new file mode 100644 index 0000000..b167f82 --- /dev/null +++ b/plugins/arm/v7/opdefs/smla_A88176.d @@ -0,0 +1,261 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SMLABB, SMLABT, SMLATB, SMLATT + +@id 175 + +@desc { + + Signed Multiply Accumulate (halfwords) performs a signed multiply accumulate operation. The multiply acts on two signed 16-bit quantities, taken from either the bottom or the top half of their respective source registers. The other halves of these source registers are ignored. The 32-bit product is added to a 32-bit accumulate value and the result is written to the destination register. If overflow occurs during the addition of the accumulate value, the instruction sets the Q flag in the APSR. It is not possible for overflow to occur during the multiplication. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 0 0 0 1 Rn(4) Ra(4) Rd(4) 0 0 N(1) M(1) Rm(4) + + @syntax { + + @subid 500 + + @assert { + + N == 1 + M == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smlatt reg_D reg_N reg_M reg_A + + } + + @syntax { + + @subid 501 + + @assert { + + N == 1 + M == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smlatb reg_D reg_N reg_M reg_A + + } + + @syntax { + + @subid 502 + + @assert { + + N == 0 + M == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smlabt reg_D reg_N reg_M reg_A + + } + + @syntax { + + @subid 503 + + @assert { + + N == 0 + M == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smlabb reg_D reg_N reg_M reg_A + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 0 0 0 Rd(4) Ra(4) Rm(4) 1 M(1) N(1) 0 Rn(4) + + @syntax { + + @subid 504 + + @assert { + + N == 1 + M == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smlatt reg_D reg_N reg_M reg_A + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 505 + + @assert { + + N == 1 + M == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smlatb reg_D reg_N reg_M reg_A + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 506 + + @assert { + + N == 0 + M == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smlabt reg_D reg_N reg_M reg_A + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 507 + + @assert { + + N == 0 + M == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smlabb reg_D reg_N reg_M reg_A + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/smlad_A88177.d b/plugins/arm/v7/opdefs/smlad_A88177.d index 9f56ebb..ff62a60 100644 --- a/plugins/arm/v7/opdefs/smlad_A88177.d +++ b/plugins/arm/v7/opdefs/smlad_A88177.d @@ -37,7 +37,7 @@ @syntax { - @subid 463 + @subid 508 @assert { @@ -60,7 +60,7 @@ @syntax { - @subid 464 + @subid 509 @assert { @@ -89,7 +89,7 @@ @syntax { - @subid 465 + @subid 510 @assert { @@ -118,7 +118,7 @@ @syntax { - @subid 466 + @subid 511 @assert { diff --git a/plugins/arm/v7/opdefs/smlal_A88178.d b/plugins/arm/v7/opdefs/smlal_A88178.d index e6fcaf8..311ae7d 100644 --- a/plugins/arm/v7/opdefs/smlal_A88178.d +++ b/plugins/arm/v7/opdefs/smlal_A88178.d @@ -37,7 +37,7 @@ @syntax { - @subid 467 + @subid 512 @conv { @@ -60,7 +60,7 @@ @syntax { - @subid 468 + @subid 513 @assert { @@ -89,7 +89,7 @@ @syntax { - @subid 469 + @subid 514 @assert { diff --git a/plugins/arm/v7/opdefs/smlal_A88179.d b/plugins/arm/v7/opdefs/smlal_A88179.d new file mode 100644 index 0000000..f7ce190 --- /dev/null +++ b/plugins/arm/v7/opdefs/smlal_A88179.d @@ -0,0 +1,261 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SMLALBB, SMLALBT, SMLALTB, SMLALTT + +@id 178 + +@desc { + + Signed Multiply Accumulate Long (halfwords) multiplies two signed 16-bit values to produce a 32-bit value, and accumulates this with a 64-bit value. The multiply acts on two signed 16-bit quantities, taken from either the bottom or the top half of their respective source registers. The other halves of these source registers are ignored. The 32-bit product is sign-extended and accumulated with a 64-bit accumulate value. Overflow is possible during this instruction, but only as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo 264. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 1 1 0 0 Rn(4) RdLo(4) RdHi(4) 1 0 N(1) M(1) Rm(4) + + @syntax { + + @subid 515 + + @assert { + + N == 1 + M == 1 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smlaltt reg_DLO reg_DHI reg_N reg_M + + } + + @syntax { + + @subid 516 + + @assert { + + N == 1 + M == 0 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smlaltb reg_DLO reg_DHI reg_N reg_M + + } + + @syntax { + + @subid 517 + + @assert { + + N == 0 + M == 1 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smlalbt reg_DLO reg_DHI reg_N reg_M + + } + + @syntax { + + @subid 518 + + @assert { + + N == 0 + M == 0 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smlalbb reg_DLO reg_DHI reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 1 0 0 RdHi(4) RdLo(4) Rm(4) 1 M(1) N(1) 0 Rn(4) + + @syntax { + + @subid 519 + + @assert { + + N == 1 + M == 1 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smlaltt reg_DLO reg_DHI reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 520 + + @assert { + + N == 1 + M == 0 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smlaltb reg_DLO reg_DHI reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 521 + + @assert { + + N == 0 + M == 1 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smlalbt reg_DLO reg_DHI reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 522 + + @assert { + + N == 0 + M == 0 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smlalbb reg_DLO reg_DHI reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/smlald_A88180.d b/plugins/arm/v7/opdefs/smlald_A88180.d index 54e0634..ed8e718 100644 --- a/plugins/arm/v7/opdefs/smlald_A88180.d +++ b/plugins/arm/v7/opdefs/smlald_A88180.d @@ -37,7 +37,7 @@ @syntax { - @subid 470 + @subid 523 @assert { @@ -60,7 +60,7 @@ @syntax { - @subid 471 + @subid 524 @assert { @@ -89,7 +89,7 @@ @syntax { - @subid 472 + @subid 525 @assert { @@ -118,7 +118,7 @@ @syntax { - @subid 473 + @subid 526 @assert { diff --git a/plugins/arm/v7/opdefs/smlaw_A88181.d b/plugins/arm/v7/opdefs/smlaw_A88181.d new file mode 100644 index 0000000..d9b8918 --- /dev/null +++ b/plugins/arm/v7/opdefs/smlaw_A88181.d @@ -0,0 +1,149 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SMLAWB, SMLAWT + +@id 180 + +@desc { + + Signed Multiply Accumulate (word by halfword) performs a signed multiply accumulate operation. The multiply acts on a signed 32-bit quantity and a signed 16-bit quantity. The signed 16-bit quantity is taken from either the bottom or the top half of its source register. The other half of the second source register is ignored. The top 32 bits of the 48-bit product are added to a 32-bit accumulate value and the result is written to the destination register. The bottom 16 bits of the 48-bit product are ignored. If overflow occurs during the addition of the accumulate value, the instruction sets the Q flag in the APSR. No overflow can occur during the multiplication. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 0 0 1 1 Rn(4) Ra(4) Rd(4) 0 0 0 M(1) Rm(4) + + @syntax { + + @subid 527 + + @assert { + + M == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smlawt reg_D reg_N reg_M reg_A + + } + + @syntax { + + @subid 528 + + @assert { + + M == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smlawb reg_D reg_N reg_M reg_A + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 0 1 0 Rd(4) Ra(4) Rm(4) 1 M(1) 0 0 Rn(4) + + @syntax { + + @subid 529 + + @assert { + + M == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smlawt reg_D reg_N reg_M reg_A + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 530 + + @assert { + + M == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smlawb reg_D reg_N reg_M reg_A + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/smlsd_A88182.d b/plugins/arm/v7/opdefs/smlsd_A88182.d index cace235..e24eb18 100644 --- a/plugins/arm/v7/opdefs/smlsd_A88182.d +++ b/plugins/arm/v7/opdefs/smlsd_A88182.d @@ -37,7 +37,7 @@ @syntax { - @subid 474 + @subid 531 @assert { @@ -60,7 +60,7 @@ @syntax { - @subid 475 + @subid 532 @assert { @@ -89,7 +89,7 @@ @syntax { - @subid 476 + @subid 533 @assert { @@ -118,7 +118,7 @@ @syntax { - @subid 477 + @subid 534 @assert { diff --git a/plugins/arm/v7/opdefs/smlsld_A88183.d b/plugins/arm/v7/opdefs/smlsld_A88183.d index 67545f6..2b82705 100644 --- a/plugins/arm/v7/opdefs/smlsld_A88183.d +++ b/plugins/arm/v7/opdefs/smlsld_A88183.d @@ -37,7 +37,7 @@ @syntax { - @subid 478 + @subid 535 @assert { @@ -60,7 +60,7 @@ @syntax { - @subid 479 + @subid 536 @assert { @@ -89,7 +89,7 @@ @syntax { - @subid 480 + @subid 537 @assert { @@ -118,7 +118,7 @@ @syntax { - @subid 481 + @subid 538 @assert { diff --git a/plugins/arm/v7/opdefs/smmla_A88184.d b/plugins/arm/v7/opdefs/smmla_A88184.d index 9ac5778..a025895 100644 --- a/plugins/arm/v7/opdefs/smmla_A88184.d +++ b/plugins/arm/v7/opdefs/smmla_A88184.d @@ -37,7 +37,7 @@ @syntax { - @subid 482 + @subid 539 @assert { @@ -60,7 +60,7 @@ @syntax { - @subid 483 + @subid 540 @assert { @@ -89,7 +89,7 @@ @syntax { - @subid 484 + @subid 541 @assert { @@ -118,7 +118,7 @@ @syntax { - @subid 485 + @subid 542 @assert { diff --git a/plugins/arm/v7/opdefs/smmls_A88185.d b/plugins/arm/v7/opdefs/smmls_A88185.d index ea32b1a..18bd82c 100644 --- a/plugins/arm/v7/opdefs/smmls_A88185.d +++ b/plugins/arm/v7/opdefs/smmls_A88185.d @@ -37,7 +37,7 @@ @syntax { - @subid 486 + @subid 543 @assert { @@ -60,7 +60,7 @@ @syntax { - @subid 487 + @subid 544 @assert { @@ -89,7 +89,7 @@ @syntax { - @subid 488 + @subid 545 @assert { @@ -118,7 +118,7 @@ @syntax { - @subid 489 + @subid 546 @assert { diff --git a/plugins/arm/v7/opdefs/smmul_A88186.d b/plugins/arm/v7/opdefs/smmul_A88186.d index b3d053f..f1b2579 100644 --- a/plugins/arm/v7/opdefs/smmul_A88186.d +++ b/plugins/arm/v7/opdefs/smmul_A88186.d @@ -37,7 +37,7 @@ @syntax { - @subid 490 + @subid 547 @assert { @@ -59,7 +59,7 @@ @syntax { - @subid 491 + @subid 548 @assert { @@ -87,7 +87,7 @@ @syntax { - @subid 492 + @subid 549 @assert { @@ -115,7 +115,7 @@ @syntax { - @subid 493 + @subid 550 @assert { diff --git a/plugins/arm/v7/opdefs/smuad_A88187.d b/plugins/arm/v7/opdefs/smuad_A88187.d index bfdcd43..c5fc1e8 100644 --- a/plugins/arm/v7/opdefs/smuad_A88187.d +++ b/plugins/arm/v7/opdefs/smuad_A88187.d @@ -37,7 +37,7 @@ @syntax { - @subid 494 + @subid 551 @assert { @@ -59,7 +59,7 @@ @syntax { - @subid 495 + @subid 552 @assert { @@ -87,7 +87,7 @@ @syntax { - @subid 496 + @subid 553 @assert { @@ -115,7 +115,7 @@ @syntax { - @subid 497 + @subid 554 @assert { diff --git a/plugins/arm/v7/opdefs/smul_A88188.d b/plugins/arm/v7/opdefs/smul_A88188.d new file mode 100644 index 0000000..18d8631 --- /dev/null +++ b/plugins/arm/v7/opdefs/smul_A88188.d @@ -0,0 +1,253 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SMULBB, SMULBT, SMULTB, SMULTT + +@id 187 + +@desc { + + Signed Multiply (halfwords) multiplies two signed 16-bit quantities, taken from either the bottom or the top half of their respective source registers. The other halves of these source registers are ignored. The 32-bit product is written to the destination register. No overflow is possible during this instruction. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 0 0 0 1 Rn(4) 1 1 1 1 Rd(4) 0 0 N(1) M(1) Rm(4) + + @syntax { + + @subid 555 + + @assert { + + N == 1 + M == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smultt ?reg_D reg_N reg_M + + } + + @syntax { + + @subid 556 + + @assert { + + N == 1 + M == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smultb ?reg_D reg_N reg_M + + } + + @syntax { + + @subid 557 + + @assert { + + N == 0 + M == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smulbt ?reg_D reg_N reg_M + + } + + @syntax { + + @subid 558 + + @assert { + + N == 0 + M == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smulbb ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 1 1 0 Rd(4) 0 0 0 0 Rm(4) 1 M(1) N(1) 0 Rn(4) + + @syntax { + + @subid 559 + + @assert { + + N == 1 + M == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smultt ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 560 + + @assert { + + N == 1 + M == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smultb ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 561 + + @assert { + + N == 0 + M == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smulbt ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 562 + + @assert { + + N == 0 + M == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smulbb ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/smull_A88189.d b/plugins/arm/v7/opdefs/smull_A88189.d index 0ecc51b..1903894 100644 --- a/plugins/arm/v7/opdefs/smull_A88189.d +++ b/plugins/arm/v7/opdefs/smull_A88189.d @@ -37,7 +37,7 @@ @syntax { - @subid 498 + @subid 563 @conv { @@ -60,7 +60,7 @@ @syntax { - @subid 499 + @subid 564 @assert { @@ -89,7 +89,7 @@ @syntax { - @subid 500 + @subid 565 @assert { diff --git a/plugins/arm/v7/opdefs/smulw_A88190.d b/plugins/arm/v7/opdefs/smulw_A88190.d new file mode 100644 index 0000000..5b5d5d3 --- /dev/null +++ b/plugins/arm/v7/opdefs/smulw_A88190.d @@ -0,0 +1,145 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SMULWB, SMULWT + +@id 189 + +@desc { + + Signed Multiply (word by halfword) multiplies a signed 32-bit quantity and a signed 16-bit quantity. The signed 16-bit quantity is taken from either the bottom or the top half of its source register. The other half of the second source register is ignored. The top 32 bits of the 48-bit product are written to the destination register. The bottom 16 bits of the 48-bit product are ignored. No overflow is possible during this instruction. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 0 0 1 1 Rn(4) 1 1 1 1 Rd(4) 0 0 0 M(1) Rm(4) + + @syntax { + + @subid 566 + + @assert { + + M == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smulwt ?reg_D reg_N reg_M + + } + + @syntax { + + @subid 567 + + @assert { + + M == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smulwb ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 0 1 0 Rd(4) 0 0 0 0 Rm(4) 1 M(1) 1 0 Rn(4) + + @syntax { + + @subid 568 + + @assert { + + M == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smulwt ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 569 + + @assert { + + M == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smulwb ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/smusd_A88191.d b/plugins/arm/v7/opdefs/smusd_A88191.d index 768d616..7ab2e6d 100644 --- a/plugins/arm/v7/opdefs/smusd_A88191.d +++ b/plugins/arm/v7/opdefs/smusd_A88191.d @@ -37,7 +37,7 @@ @syntax { - @subid 501 + @subid 570 @assert { @@ -59,7 +59,7 @@ @syntax { - @subid 502 + @subid 571 @assert { @@ -87,7 +87,7 @@ @syntax { - @subid 503 + @subid 572 @assert { @@ -115,7 +115,7 @@ @syntax { - @subid 504 + @subid 573 @assert { diff --git a/plugins/arm/v7/opdefs/ssat16_A88194.d b/plugins/arm/v7/opdefs/ssat16_A88194.d index 30515d0..6cae060 100644 --- a/plugins/arm/v7/opdefs/ssat16_A88194.d +++ b/plugins/arm/v7/opdefs/ssat16_A88194.d @@ -37,7 +37,7 @@ @syntax { - @subid 507 + @subid 576 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 508 + @subid 577 @conv { diff --git a/plugins/arm/v7/opdefs/ssat_A88193.d b/plugins/arm/v7/opdefs/ssat_A88193.d index 7f323b7..835b80f 100644 --- a/plugins/arm/v7/opdefs/ssat_A88193.d +++ b/plugins/arm/v7/opdefs/ssat_A88193.d @@ -37,7 +37,7 @@ @syntax { - @subid 505 + @subid 574 @conv { @@ -60,7 +60,7 @@ @syntax { - @subid 506 + @subid 575 @conv { diff --git a/plugins/arm/v7/opdefs/ssax_A88195.d b/plugins/arm/v7/opdefs/ssax_A88195.d index f7ac18a..be5e94a 100644 --- a/plugins/arm/v7/opdefs/ssax_A88195.d +++ b/plugins/arm/v7/opdefs/ssax_A88195.d @@ -37,7 +37,7 @@ @syntax { - @subid 509 + @subid 578 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 510 + @subid 579 @conv { diff --git a/plugins/arm/v7/opdefs/ssub16_A88196.d b/plugins/arm/v7/opdefs/ssub16_A88196.d index 78a9a4a..b3a1935 100644 --- a/plugins/arm/v7/opdefs/ssub16_A88196.d +++ b/plugins/arm/v7/opdefs/ssub16_A88196.d @@ -37,7 +37,7 @@ @syntax { - @subid 511 + @subid 580 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 512 + @subid 581 @conv { diff --git a/plugins/arm/v7/opdefs/ssub8_A88197.d b/plugins/arm/v7/opdefs/ssub8_A88197.d index 38045ce..b7b9d9c 100644 --- a/plugins/arm/v7/opdefs/ssub8_A88197.d +++ b/plugins/arm/v7/opdefs/ssub8_A88197.d @@ -37,7 +37,7 @@ @syntax { - @subid 513 + @subid 582 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 514 + @subid 583 @conv { diff --git a/plugins/arm/v7/opdefs/stc_A88198.d b/plugins/arm/v7/opdefs/stc_A88198.d new file mode 100644 index 0000000..88b68ac --- /dev/null +++ b/plugins/arm/v7/opdefs/stc_A88198.d @@ -0,0 +1,461 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title STC, STC2 + +@id 197 + +@desc { + + Store Coprocessor stores data from a coprocessor to a sequence of consecutive memory addresses. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the D bit, the CRd field, and in the Unindexed addressing mode only, the imm8 field. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid STC and STC2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. In an implementation that includes the Virtualization Extensions, the permitted STC access to a system control register can be trapped to Hyp mode, meaning that an attempt to execute an STC instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see Trapping general CP14 accesses to debug registers on page B1-1260. Note For simplicity, the STC pseudocode does not show this possible trap to Hyp mode. + +} + +@encoding (T1) { + + @word 1 1 1 0 1 1 0 P(1) U(1) D(1) W(1) 0 Rn(4) CRd(4) coproc(4) imm8(8) + + @syntax { + + @subid 584 + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm stc cp direct_CRd maccess + + } + + @syntax { + + @subid 585 + + @assert { + + P == 1 + W == 1 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm stc cp direct_CRd maccess + + } + + @syntax { + + @subid 586 + + @assert { + + P == 0 + W == 1 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm stc cp direct_CRd maccess + + } + + @syntax { + + @subid 587 + + @assert { + + P == 0 + W == 0 + U == 1 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) + option = ZeroExtend(imm8:'00', 32) + + } + + @asm stc cp direct_CRd maccess option + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 1 0 P(1) U(1) D(1) W(1) 0 Rn(4) CRd(4) coproc(4) imm8(8) + + @syntax { + + @subid 588 + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm stc cp direct_CRd maccess + + } + + @syntax { + + @subid 589 + + @assert { + + P == 1 + W == 1 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm stc cp direct_CRd maccess + + } + + @syntax { + + @subid 590 + + @assert { + + P == 0 + W == 1 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm stc cp direct_CRd maccess + + } + + @syntax { + + @subid 591 + + @assert { + + P == 0 + W == 0 + U == 1 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) + option = ZeroExtend(imm8:'00', 32) + + } + + @asm stc cp direct_CRd maccess option + + } + +} + +@encoding (A1) { + + @word 1 1 1 0 1 1 0 P(1) U(1) D(1) W(1) 0 Rn(4) CRd(4) coproc(4) imm8(8) + + @syntax { + + @subid 592 + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm stc cp direct_CRd maccess + + } + + @syntax { + + @subid 593 + + @assert { + + P == 1 + W == 1 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm stc cp direct_CRd maccess + + } + + @syntax { + + @subid 594 + + @assert { + + P == 0 + W == 1 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm stc cp direct_CRd maccess + + } + + @syntax { + + @subid 595 + + @assert { + + P == 0 + W == 0 + U == 1 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) + option = ZeroExtend(imm8:'00', 32) + + } + + @asm stc cp direct_CRd maccess option + + } + +} + +@encoding (A2) { + + @word 1 1 1 1 1 1 0 P(1) U(1) D(1) W(1) 0 Rn(4) CRd(4) coproc(4) imm8(8) + + @syntax { + + @subid 596 + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm stc cp direct_CRd maccess + + } + + @syntax { + + @subid 597 + + @assert { + + P == 1 + W == 1 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm stc cp direct_CRd maccess + + } + + @syntax { + + @subid 598 + + @assert { + + P == 0 + W == 1 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm stc cp direct_CRd maccess + + } + + @syntax { + + @subid 599 + + @assert { + + P == 0 + W == 0 + U == 1 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) + option = ZeroExtend(imm8:'00', 32) + + } + + @asm stc cp direct_CRd maccess option + + } + +} + diff --git a/plugins/arm/v7/opdefs/stm_A88199.d b/plugins/arm/v7/opdefs/stm_A88199.d new file mode 100644 index 0000000..0b519e6 --- /dev/null +++ b/plugins/arm/v7/opdefs/stm_A88199.d @@ -0,0 +1,111 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title STM (STMIA, STMEA) + +@id 198 + +@desc { + + Store Multiple Increment After (Store Multiple Empty Ascending) stores multiple registers to consecutive memory locations using an address from a base register. The consecutive memory locations start at this address, and the address just above the last of those locations can optionally be written back to the base register. For details of related system instructions see STM (User registers) on page B9-2006. + +} + +@encoding (t1) { + + @half 1 1 0 0 0 Rn(3) register_list(8) + + @syntax { + + @subid 600 + + @conv { + + reg_N = Register(Rn) + wb_reg = UncheckedWrittenBackReg(reg_N) + registers = RegList('00000000':register_list) + + } + + @asm stm wb_reg registers + + } + + @hooks { + + fetch = apply_write_back + + } + +} + +@encoding (T2) { + + @word 1 1 1 0 1 0 0 0 1 0 W(1) 0 Rn(4) 0 M(1) 0 register_list(13) + + @syntax { + + @subid 601 + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + registers = RegList('0':M:'0':register_list) + + } + + @asm stm.w wb_reg registers + + } + +} + +@encoding (A1) { + + @word cond(4) 1 0 0 0 1 0 W(1) 0 Rn(4) register_list(16) + + @syntax { + + @subid 602 + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + registers = RegList(register_list) + + } + + @asm stm wb_reg registers + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/stmda_A88200.d b/plugins/arm/v7/opdefs/stmda_A88200.d new file mode 100644 index 0000000..8515c74 --- /dev/null +++ b/plugins/arm/v7/opdefs/stmda_A88200.d @@ -0,0 +1,61 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title STMDA (STMED) + +@id 199 + +@desc { + + Store Multiple Decrement After (Store Multiple Empty Descending) stores multiple registers to consecutive memory locations using an address from a base register. The consecutive memory locations end at this address, and the address just below the lowest of those locations can optionally be written back to the base register. For details of related system instructions see STM (User registers) on page B9-2006. + +} + +@encoding (A1) { + + @word cond(4) 1 0 0 0 0 0 W(1) 0 Rn(4) register_list(16) + + @syntax { + + @subid 603 + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + registers = RegList(register_list) + + } + + @asm stmda wb_reg registers + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/stmdb_A88201.d b/plugins/arm/v7/opdefs/stmdb_A88201.d new file mode 100644 index 0000000..52d7bfb --- /dev/null +++ b/plugins/arm/v7/opdefs/stmdb_A88201.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title STMDB (STMFD) + +@id 200 + +@desc { + + Store Multiple Decrement Before (Store Multiple Full Descending) stores multiple registers to consecutive memory locations using an address from a base register. The consecutive memory locations end just below this address, and the address of the first of those locations can optionally be written back to the base register. For details of related system instructions see STM (User registers) on page B9-2006. + +} + +@encoding (T1) { + + @word 1 1 1 0 1 0 0 1 0 0 W(1) 0 Rn(4) 0 M(1) 0 register_list(13) + + @syntax { + + @subid 604 + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + registers = RegList('0':M:'0':register_list) + + } + + @asm stmdb wb_reg registers + + } + +} + +@encoding (A1) { + + @word cond(4) 1 0 0 1 0 0 W(1) 0 Rn(4) register_list(16) + + @syntax { + + @subid 605 + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + registers = RegList(register_list) + + } + + @asm stmdb wb_reg registers + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/stmib_A88202.d b/plugins/arm/v7/opdefs/stmib_A88202.d new file mode 100644 index 0000000..9ce1840 --- /dev/null +++ b/plugins/arm/v7/opdefs/stmib_A88202.d @@ -0,0 +1,61 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title STMIB (STMFA) + +@id 201 + +@desc { + + Store Multiple Increment Before (Store Multiple Full Ascending) stores multiple registers to consecutive memory locations using an address from a base register. The consecutive memory locations start just above this address, and the address of the last of those locations can optionally be written back to the base register. For details of related system instructions see STM (User registers) on page B9-2006. + +} + +@encoding (A1) { + + @word cond(4) 1 0 0 1 1 0 W(1) 0 Rn(4) register_list(16) + + @syntax { + + @subid 606 + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + registers = RegList(register_list) + + } + + @asm stmib wb_reg registers + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/str_A88203.d b/plugins/arm/v7/opdefs/str_A88203.d index d5c5744..591641b 100644 --- a/plugins/arm/v7/opdefs/str_A88203.d +++ b/plugins/arm/v7/opdefs/str_A88203.d @@ -37,7 +37,7 @@ @syntax { - @subid 515 + @subid 607 @conv { @@ -60,7 +60,7 @@ @syntax { - @subid 516 + @subid 608 @conv { @@ -83,7 +83,7 @@ @syntax { - @subid 517 + @subid 609 @conv { @@ -106,7 +106,7 @@ @syntax { - @subid 518 + @subid 610 @assert { @@ -130,7 +130,7 @@ @syntax { - @subid 519 + @subid 611 @assert { @@ -154,7 +154,7 @@ @syntax { - @subid 520 + @subid 612 @assert { diff --git a/plugins/arm/v7/opdefs/str_A88204.d b/plugins/arm/v7/opdefs/str_A88204.d index cee5ff5..6182de8 100644 --- a/plugins/arm/v7/opdefs/str_A88204.d +++ b/plugins/arm/v7/opdefs/str_A88204.d @@ -37,7 +37,7 @@ @syntax { - @subid 521 + @subid 613 @assert { @@ -67,7 +67,7 @@ @syntax { - @subid 522 + @subid 614 @assert { @@ -97,7 +97,7 @@ @syntax { - @subid 523 + @subid 615 @assert { diff --git a/plugins/arm/v7/opdefs/str_A88205.d b/plugins/arm/v7/opdefs/str_A88205.d index 59c43a7..cbc9f78 100644 --- a/plugins/arm/v7/opdefs/str_A88205.d +++ b/plugins/arm/v7/opdefs/str_A88205.d @@ -37,7 +37,7 @@ @syntax { - @subid 524 + @subid 616 @conv { @@ -60,7 +60,7 @@ @syntax { - @subid 525 + @subid 617 @conv { @@ -84,7 +84,7 @@ @syntax { - @subid 526 + @subid 618 @assert { @@ -115,7 +115,7 @@ @syntax { - @subid 527 + @subid 619 @assert { @@ -146,7 +146,7 @@ @syntax { - @subid 528 + @subid 620 @assert { diff --git a/plugins/arm/v7/opdefs/strb_A88206.d b/plugins/arm/v7/opdefs/strb_A88206.d index 7cbf681..cb7b74a 100644 --- a/plugins/arm/v7/opdefs/strb_A88206.d +++ b/plugins/arm/v7/opdefs/strb_A88206.d @@ -37,7 +37,7 @@ @syntax { - @subid 529 + @subid 621 @conv { @@ -60,7 +60,7 @@ @syntax { - @subid 530 + @subid 622 @conv { @@ -83,7 +83,7 @@ @syntax { - @subid 531 + @subid 623 @assert { @@ -107,7 +107,7 @@ @syntax { - @subid 532 + @subid 624 @assert { @@ -131,7 +131,7 @@ @syntax { - @subid 533 + @subid 625 @assert { diff --git a/plugins/arm/v7/opdefs/strb_A88207.d b/plugins/arm/v7/opdefs/strb_A88207.d index 2c6a13f..3ee78b9 100644 --- a/plugins/arm/v7/opdefs/strb_A88207.d +++ b/plugins/arm/v7/opdefs/strb_A88207.d @@ -37,7 +37,7 @@ @syntax { - @subid 534 + @subid 626 @assert { @@ -67,7 +67,7 @@ @syntax { - @subid 535 + @subid 627 @assert { @@ -97,7 +97,7 @@ @syntax { - @subid 536 + @subid 628 @assert { diff --git a/plugins/arm/v7/opdefs/strb_A88208.d b/plugins/arm/v7/opdefs/strb_A88208.d index 64ce4d0..8ecc962 100644 --- a/plugins/arm/v7/opdefs/strb_A88208.d +++ b/plugins/arm/v7/opdefs/strb_A88208.d @@ -37,7 +37,7 @@ @syntax { - @subid 537 + @subid 629 @conv { @@ -60,7 +60,7 @@ @syntax { - @subid 538 + @subid 630 @conv { @@ -84,7 +84,7 @@ @syntax { - @subid 539 + @subid 631 @assert { @@ -115,7 +115,7 @@ @syntax { - @subid 540 + @subid 632 @assert { @@ -146,7 +146,7 @@ @syntax { - @subid 541 + @subid 633 @assert { diff --git a/plugins/arm/v7/opdefs/strbt_A88209.d b/plugins/arm/v7/opdefs/strbt_A88209.d index 8608763..ac91408 100644 --- a/plugins/arm/v7/opdefs/strbt_A88209.d +++ b/plugins/arm/v7/opdefs/strbt_A88209.d @@ -37,7 +37,7 @@ @syntax { - @subid 542 + @subid 634 @conv { @@ -60,7 +60,7 @@ @syntax { - @subid 543 + @subid 635 @conv { @@ -89,7 +89,7 @@ @syntax { - @subid 544 + @subid 636 @conv { diff --git a/plugins/arm/v7/opdefs/strd_A88210.d b/plugins/arm/v7/opdefs/strd_A88210.d index feb36a7..83e7af7 100644 --- a/plugins/arm/v7/opdefs/strd_A88210.d +++ b/plugins/arm/v7/opdefs/strd_A88210.d @@ -37,7 +37,7 @@ @syntax { - @subid 545 + @subid 637 @assert { @@ -62,7 +62,7 @@ @syntax { - @subid 546 + @subid 638 @assert { @@ -87,7 +87,7 @@ @syntax { - @subid 547 + @subid 639 @assert { @@ -118,7 +118,7 @@ @syntax { - @subid 548 + @subid 640 @assert { @@ -149,7 +149,7 @@ @syntax { - @subid 549 + @subid 641 @assert { @@ -180,7 +180,7 @@ @syntax { - @subid 550 + @subid 642 @assert { diff --git a/plugins/arm/v7/opdefs/strd_A88211.d b/plugins/arm/v7/opdefs/strd_A88211.d index 9ca5cce..817d2f1 100644 --- a/plugins/arm/v7/opdefs/strd_A88211.d +++ b/plugins/arm/v7/opdefs/strd_A88211.d @@ -37,7 +37,7 @@ @syntax { - @subid 551 + @subid 643 @assert { @@ -68,7 +68,7 @@ @syntax { - @subid 552 + @subid 644 @assert { @@ -99,7 +99,7 @@ @syntax { - @subid 553 + @subid 645 @assert { diff --git a/plugins/arm/v7/opdefs/strex_A88212.d b/plugins/arm/v7/opdefs/strex_A88212.d index 1984524..8a3ab87 100644 --- a/plugins/arm/v7/opdefs/strex_A88212.d +++ b/plugins/arm/v7/opdefs/strex_A88212.d @@ -37,7 +37,7 @@ @syntax { - @subid 554 + @subid 646 @conv { @@ -61,7 +61,7 @@ @syntax { - @subid 555 + @subid 647 @conv { diff --git a/plugins/arm/v7/opdefs/strexb_A88213.d b/plugins/arm/v7/opdefs/strexb_A88213.d index 309fdf2..45ec2f2 100644 --- a/plugins/arm/v7/opdefs/strexb_A88213.d +++ b/plugins/arm/v7/opdefs/strexb_A88213.d @@ -37,7 +37,7 @@ @syntax { - @subid 556 + @subid 648 @conv { @@ -60,7 +60,7 @@ @syntax { - @subid 557 + @subid 649 @conv { diff --git a/plugins/arm/v7/opdefs/strexd_A88214.d b/plugins/arm/v7/opdefs/strexd_A88214.d index 7223d8c..ec1f4f6 100644 --- a/plugins/arm/v7/opdefs/strexd_A88214.d +++ b/plugins/arm/v7/opdefs/strexd_A88214.d @@ -37,7 +37,7 @@ @syntax { - @subid 558 + @subid 650 @conv { @@ -61,7 +61,7 @@ @syntax { - @subid 559 + @subid 651 @conv { diff --git a/plugins/arm/v7/opdefs/strexh_A88215.d b/plugins/arm/v7/opdefs/strexh_A88215.d index d999c68..6ca68ce 100644 --- a/plugins/arm/v7/opdefs/strexh_A88215.d +++ b/plugins/arm/v7/opdefs/strexh_A88215.d @@ -37,7 +37,7 @@ @syntax { - @subid 560 + @subid 652 @conv { @@ -60,7 +60,7 @@ @syntax { - @subid 561 + @subid 653 @conv { diff --git a/plugins/arm/v7/opdefs/strh_A88216.d b/plugins/arm/v7/opdefs/strh_A88216.d index 8e54122..fadbcbe 100644 --- a/plugins/arm/v7/opdefs/strh_A88216.d +++ b/plugins/arm/v7/opdefs/strh_A88216.d @@ -37,7 +37,7 @@ @syntax { - @subid 562 + @subid 654 @conv { @@ -60,7 +60,7 @@ @syntax { - @subid 563 + @subid 655 @conv { @@ -83,7 +83,7 @@ @syntax { - @subid 564 + @subid 656 @assert { @@ -107,7 +107,7 @@ @syntax { - @subid 565 + @subid 657 @assert { @@ -131,7 +131,7 @@ @syntax { - @subid 566 + @subid 658 @assert { diff --git a/plugins/arm/v7/opdefs/strh_A88217.d b/plugins/arm/v7/opdefs/strh_A88217.d index ed44ec0..76fc365 100644 --- a/plugins/arm/v7/opdefs/strh_A88217.d +++ b/plugins/arm/v7/opdefs/strh_A88217.d @@ -37,7 +37,7 @@ @syntax { - @subid 567 + @subid 659 @assert { @@ -67,7 +67,7 @@ @syntax { - @subid 568 + @subid 660 @assert { @@ -97,7 +97,7 @@ @syntax { - @subid 569 + @subid 661 @assert { diff --git a/plugins/arm/v7/opdefs/strh_A88218.d b/plugins/arm/v7/opdefs/strh_A88218.d index ae46b75..0d222a8 100644 --- a/plugins/arm/v7/opdefs/strh_A88218.d +++ b/plugins/arm/v7/opdefs/strh_A88218.d @@ -37,7 +37,7 @@ @syntax { - @subid 570 + @subid 662 @conv { @@ -60,7 +60,7 @@ @syntax { - @subid 571 + @subid 663 @conv { @@ -84,7 +84,7 @@ @syntax { - @subid 572 + @subid 664 @assert { @@ -114,7 +114,7 @@ @syntax { - @subid 573 + @subid 665 @assert { @@ -144,7 +144,7 @@ @syntax { - @subid 574 + @subid 666 @assert { diff --git a/plugins/arm/v7/opdefs/strht_A88219.d b/plugins/arm/v7/opdefs/strht_A88219.d index a750b63..a15db3a 100644 --- a/plugins/arm/v7/opdefs/strht_A88219.d +++ b/plugins/arm/v7/opdefs/strht_A88219.d @@ -37,7 +37,7 @@ @syntax { - @subid 575 + @subid 667 @conv { @@ -60,7 +60,7 @@ @syntax { - @subid 576 + @subid 668 @conv { @@ -89,7 +89,7 @@ @syntax { - @subid 577 + @subid 669 @conv { diff --git a/plugins/arm/v7/opdefs/strt_A88220.d b/plugins/arm/v7/opdefs/strt_A88220.d index cc113b3..0750a0d 100644 --- a/plugins/arm/v7/opdefs/strt_A88220.d +++ b/plugins/arm/v7/opdefs/strt_A88220.d @@ -37,7 +37,7 @@ @syntax { - @subid 578 + @subid 670 @conv { @@ -60,7 +60,7 @@ @syntax { - @subid 579 + @subid 671 @conv { @@ -89,7 +89,7 @@ @syntax { - @subid 580 + @subid 672 @conv { diff --git a/plugins/arm/v7/opdefs/sub_A88221.d b/plugins/arm/v7/opdefs/sub_A88221.d index 71eb2fe..30ccb68 100644 --- a/plugins/arm/v7/opdefs/sub_A88221.d +++ b/plugins/arm/v7/opdefs/sub_A88221.d @@ -37,7 +37,7 @@ @syntax { - @subid 581 + @subid 673 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 582 + @subid 674 @conv { @@ -81,7 +81,7 @@ @syntax { - @subid 583 + @subid 675 @assert { @@ -103,7 +103,7 @@ @syntax { - @subid 584 + @subid 676 @assert { @@ -131,7 +131,7 @@ @syntax { - @subid 585 + @subid 677 @conv { diff --git a/plugins/arm/v7/opdefs/sub_A88222.d b/plugins/arm/v7/opdefs/sub_A88222.d index 9dcc50b..74bb4e0 100644 --- a/plugins/arm/v7/opdefs/sub_A88222.d +++ b/plugins/arm/v7/opdefs/sub_A88222.d @@ -37,7 +37,7 @@ @syntax { - @subid 586 + @subid 678 @assert { @@ -65,7 +65,7 @@ @syntax { - @subid 587 + @subid 679 @assert { diff --git a/plugins/arm/v7/opdefs/sub_A88223.d b/plugins/arm/v7/opdefs/sub_A88223.d index b993951..1498889 100644 --- a/plugins/arm/v7/opdefs/sub_A88223.d +++ b/plugins/arm/v7/opdefs/sub_A88223.d @@ -37,7 +37,7 @@ @syntax { - @subid 588 + @subid 680 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 589 + @subid 681 @assert { @@ -82,7 +82,7 @@ @syntax { - @subid 590 + @subid 682 @assert { @@ -111,7 +111,7 @@ @syntax { - @subid 591 + @subid 683 @assert { @@ -140,7 +140,7 @@ @syntax { - @subid 592 + @subid 684 @assert { diff --git a/plugins/arm/v7/opdefs/sub_A88224.d b/plugins/arm/v7/opdefs/sub_A88224.d index 817d1a4..e52e818 100644 --- a/plugins/arm/v7/opdefs/sub_A88224.d +++ b/plugins/arm/v7/opdefs/sub_A88224.d @@ -37,7 +37,7 @@ @syntax { - @subid 593 + @subid 685 @assert { @@ -68,7 +68,7 @@ @syntax { - @subid 594 + @subid 686 @assert { diff --git a/plugins/arm/v7/opdefs/sub_A88225.d b/plugins/arm/v7/opdefs/sub_A88225.d index bb44a8e..3248f19 100644 --- a/plugins/arm/v7/opdefs/sub_A88225.d +++ b/plugins/arm/v7/opdefs/sub_A88225.d @@ -37,7 +37,7 @@ @syntax { - @subid 595 + @subid 687 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 596 + @subid 688 @assert { @@ -81,7 +81,7 @@ @syntax { - @subid 597 + @subid 689 @assert { @@ -109,7 +109,7 @@ @syntax { - @subid 598 + @subid 690 @conv { @@ -131,7 +131,7 @@ @syntax { - @subid 599 + @subid 691 @assert { @@ -159,7 +159,7 @@ @syntax { - @subid 600 + @subid 692 @assert { diff --git a/plugins/arm/v7/opdefs/sub_A88226.d b/plugins/arm/v7/opdefs/sub_A88226.d index d4e4eff..cdbd277 100644 --- a/plugins/arm/v7/opdefs/sub_A88226.d +++ b/plugins/arm/v7/opdefs/sub_A88226.d @@ -37,7 +37,7 @@ @syntax { - @subid 601 + @subid 693 @assert { @@ -60,7 +60,7 @@ @syntax { - @subid 602 + @subid 694 @assert { @@ -89,7 +89,7 @@ @syntax { - @subid 603 + @subid 695 @assert { @@ -118,7 +118,7 @@ @syntax { - @subid 604 + @subid 696 @assert { diff --git a/plugins/arm/v7/opdefs/svc_A88228.d b/plugins/arm/v7/opdefs/svc_A88228.d index 4df804f..d9f709e 100644 --- a/plugins/arm/v7/opdefs/svc_A88228.d +++ b/plugins/arm/v7/opdefs/svc_A88228.d @@ -37,7 +37,7 @@ @syntax { - @subid 605 + @subid 697 @conv { @@ -57,7 +57,7 @@ @syntax { - @subid 606 + @subid 698 @conv { diff --git a/plugins/arm/v7/opdefs/swp_A88229.d b/plugins/arm/v7/opdefs/swp_A88229.d index cae58ca..09a8110 100644 --- a/plugins/arm/v7/opdefs/swp_A88229.d +++ b/plugins/arm/v7/opdefs/swp_A88229.d @@ -37,7 +37,7 @@ @syntax { - @subid 607 + @subid 699 @assert { @@ -66,7 +66,7 @@ @syntax { - @subid 608 + @subid 700 @assert { diff --git a/plugins/arm/v7/opdefs/sxtab16_A88231.d b/plugins/arm/v7/opdefs/sxtab16_A88231.d index a690a1e..f60a624 100644 --- a/plugins/arm/v7/opdefs/sxtab16_A88231.d +++ b/plugins/arm/v7/opdefs/sxtab16_A88231.d @@ -37,7 +37,7 @@ @syntax { - @subid 611 + @subid 703 @conv { @@ -60,7 +60,7 @@ @syntax { - @subid 612 + @subid 704 @conv { diff --git a/plugins/arm/v7/opdefs/sxtab_A88230.d b/plugins/arm/v7/opdefs/sxtab_A88230.d index b897af5..ccd1859 100644 --- a/plugins/arm/v7/opdefs/sxtab_A88230.d +++ b/plugins/arm/v7/opdefs/sxtab_A88230.d @@ -37,7 +37,7 @@ @syntax { - @subid 609 + @subid 701 @conv { @@ -60,7 +60,7 @@ @syntax { - @subid 610 + @subid 702 @conv { diff --git a/plugins/arm/v7/opdefs/sxtah_A88232.d b/plugins/arm/v7/opdefs/sxtah_A88232.d index b3b77d0..e1d4135 100644 --- a/plugins/arm/v7/opdefs/sxtah_A88232.d +++ b/plugins/arm/v7/opdefs/sxtah_A88232.d @@ -37,7 +37,7 @@ @syntax { - @subid 613 + @subid 705 @conv { @@ -60,7 +60,7 @@ @syntax { - @subid 614 + @subid 706 @conv { diff --git a/plugins/arm/v7/opdefs/sxtb16_A88234.d b/plugins/arm/v7/opdefs/sxtb16_A88234.d index a1aa0dd..fe9fb17 100644 --- a/plugins/arm/v7/opdefs/sxtb16_A88234.d +++ b/plugins/arm/v7/opdefs/sxtb16_A88234.d @@ -37,7 +37,7 @@ @syntax { - @subid 618 + @subid 710 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 619 + @subid 711 @conv { diff --git a/plugins/arm/v7/opdefs/sxtb_A88233.d b/plugins/arm/v7/opdefs/sxtb_A88233.d index fb07b8a..99b43c0 100644 --- a/plugins/arm/v7/opdefs/sxtb_A88233.d +++ b/plugins/arm/v7/opdefs/sxtb_A88233.d @@ -37,7 +37,7 @@ @syntax { - @subid 615 + @subid 707 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 616 + @subid 708 @conv { @@ -81,7 +81,7 @@ @syntax { - @subid 617 + @subid 709 @conv { diff --git a/plugins/arm/v7/opdefs/sxth_A88235.d b/plugins/arm/v7/opdefs/sxth_A88235.d index a5e4b59..76e09d2 100644 --- a/plugins/arm/v7/opdefs/sxth_A88235.d +++ b/plugins/arm/v7/opdefs/sxth_A88235.d @@ -37,7 +37,7 @@ @syntax { - @subid 620 + @subid 712 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 621 + @subid 713 @conv { @@ -81,7 +81,7 @@ @syntax { - @subid 622 + @subid 714 @conv { diff --git a/plugins/arm/v7/opdefs/teq_A88237.d b/plugins/arm/v7/opdefs/teq_A88237.d index f729083..9972918 100644 --- a/plugins/arm/v7/opdefs/teq_A88237.d +++ b/plugins/arm/v7/opdefs/teq_A88237.d @@ -37,7 +37,7 @@ @syntax { - @subid 623 + @subid 715 @conv { @@ -58,7 +58,7 @@ @syntax { - @subid 624 + @subid 716 @conv { diff --git a/plugins/arm/v7/opdefs/teq_A88238.d b/plugins/arm/v7/opdefs/teq_A88238.d index 4710ad7..def4bc4 100644 --- a/plugins/arm/v7/opdefs/teq_A88238.d +++ b/plugins/arm/v7/opdefs/teq_A88238.d @@ -37,7 +37,7 @@ @syntax { - @subid 625 + @subid 717 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 626 + @subid 718 @conv { diff --git a/plugins/arm/v7/opdefs/teq_A88239.d b/plugins/arm/v7/opdefs/teq_A88239.d index ea2cd68..3c6ab33 100644 --- a/plugins/arm/v7/opdefs/teq_A88239.d +++ b/plugins/arm/v7/opdefs/teq_A88239.d @@ -37,7 +37,7 @@ @syntax { - @subid 627 + @subid 719 @conv { diff --git a/plugins/arm/v7/opdefs/tst_A88240.d b/plugins/arm/v7/opdefs/tst_A88240.d index c390262..125febc 100644 --- a/plugins/arm/v7/opdefs/tst_A88240.d +++ b/plugins/arm/v7/opdefs/tst_A88240.d @@ -37,7 +37,7 @@ @syntax { - @subid 628 + @subid 720 @conv { @@ -58,7 +58,7 @@ @syntax { - @subid 629 + @subid 721 @conv { diff --git a/plugins/arm/v7/opdefs/tst_A88241.d b/plugins/arm/v7/opdefs/tst_A88241.d index e65fea9..1be33f8 100644 --- a/plugins/arm/v7/opdefs/tst_A88241.d +++ b/plugins/arm/v7/opdefs/tst_A88241.d @@ -37,7 +37,7 @@ @syntax { - @subid 630 + @subid 722 @conv { @@ -58,7 +58,7 @@ @syntax { - @subid 631 + @subid 723 @conv { @@ -80,7 +80,7 @@ @syntax { - @subid 632 + @subid 724 @conv { diff --git a/plugins/arm/v7/opdefs/tst_A88242.d b/plugins/arm/v7/opdefs/tst_A88242.d index 279c92e..04bfdd2 100644 --- a/plugins/arm/v7/opdefs/tst_A88242.d +++ b/plugins/arm/v7/opdefs/tst_A88242.d @@ -37,7 +37,7 @@ @syntax { - @subid 633 + @subid 725 @conv { diff --git a/plugins/arm/v7/opdefs/uadd16_A88243.d b/plugins/arm/v7/opdefs/uadd16_A88243.d index d99ee90..ba9ad7a 100644 --- a/plugins/arm/v7/opdefs/uadd16_A88243.d +++ b/plugins/arm/v7/opdefs/uadd16_A88243.d @@ -37,7 +37,7 @@ @syntax { - @subid 634 + @subid 726 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 635 + @subid 727 @conv { diff --git a/plugins/arm/v7/opdefs/uadd8_A88244.d b/plugins/arm/v7/opdefs/uadd8_A88244.d index 799c831..bf8e18d 100644 --- a/plugins/arm/v7/opdefs/uadd8_A88244.d +++ b/plugins/arm/v7/opdefs/uadd8_A88244.d @@ -37,7 +37,7 @@ @syntax { - @subid 636 + @subid 728 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 637 + @subid 729 @conv { diff --git a/plugins/arm/v7/opdefs/uasx_A88245.d b/plugins/arm/v7/opdefs/uasx_A88245.d index 14ca465..b802f43 100644 --- a/plugins/arm/v7/opdefs/uasx_A88245.d +++ b/plugins/arm/v7/opdefs/uasx_A88245.d @@ -37,7 +37,7 @@ @syntax { - @subid 638 + @subid 730 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 639 + @subid 731 @conv { diff --git a/plugins/arm/v7/opdefs/ubfx_A88246.d b/plugins/arm/v7/opdefs/ubfx_A88246.d index 732f594..3fe25c7 100644 --- a/plugins/arm/v7/opdefs/ubfx_A88246.d +++ b/plugins/arm/v7/opdefs/ubfx_A88246.d @@ -37,7 +37,7 @@ @syntax { - @subid 640 + @subid 732 @conv { @@ -61,7 +61,7 @@ @syntax { - @subid 641 + @subid 733 @conv { diff --git a/plugins/arm/v7/opdefs/udf_A88247.d b/plugins/arm/v7/opdefs/udf_A88247.d index db26083..500e714 100644 --- a/plugins/arm/v7/opdefs/udf_A88247.d +++ b/plugins/arm/v7/opdefs/udf_A88247.d @@ -37,7 +37,7 @@ @syntax { - @subid 642 + @subid 734 @conv { @@ -57,7 +57,7 @@ @syntax { - @subid 643 + @subid 735 @conv { @@ -77,7 +77,7 @@ @syntax { - @subid 644 + @subid 736 @conv { diff --git a/plugins/arm/v7/opdefs/udiv_A88248.d b/plugins/arm/v7/opdefs/udiv_A88248.d index 4504985..27ef02b 100644 --- a/plugins/arm/v7/opdefs/udiv_A88248.d +++ b/plugins/arm/v7/opdefs/udiv_A88248.d @@ -37,7 +37,7 @@ @syntax { - @subid 645 + @subid 737 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 646 + @subid 738 @conv { diff --git a/plugins/arm/v7/opdefs/uhadd16_A88249.d b/plugins/arm/v7/opdefs/uhadd16_A88249.d index 65f7bd8..379b0e9 100644 --- a/plugins/arm/v7/opdefs/uhadd16_A88249.d +++ b/plugins/arm/v7/opdefs/uhadd16_A88249.d @@ -37,7 +37,7 @@ @syntax { - @subid 647 + @subid 739 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 648 + @subid 740 @conv { diff --git a/plugins/arm/v7/opdefs/uhadd8_A88250.d b/plugins/arm/v7/opdefs/uhadd8_A88250.d index 0964304..1f4a626 100644 --- a/plugins/arm/v7/opdefs/uhadd8_A88250.d +++ b/plugins/arm/v7/opdefs/uhadd8_A88250.d @@ -37,7 +37,7 @@ @syntax { - @subid 649 + @subid 741 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 650 + @subid 742 @conv { diff --git a/plugins/arm/v7/opdefs/uhasx_A88251.d b/plugins/arm/v7/opdefs/uhasx_A88251.d index 2a624bc..148d120 100644 --- a/plugins/arm/v7/opdefs/uhasx_A88251.d +++ b/plugins/arm/v7/opdefs/uhasx_A88251.d @@ -37,7 +37,7 @@ @syntax { - @subid 651 + @subid 743 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 652 + @subid 744 @conv { diff --git a/plugins/arm/v7/opdefs/uhsax_A88252.d b/plugins/arm/v7/opdefs/uhsax_A88252.d index a90963e..eb7dd83 100644 --- a/plugins/arm/v7/opdefs/uhsax_A88252.d +++ b/plugins/arm/v7/opdefs/uhsax_A88252.d @@ -37,7 +37,7 @@ @syntax { - @subid 653 + @subid 745 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 654 + @subid 746 @conv { diff --git a/plugins/arm/v7/opdefs/uhsub16_A88253.d b/plugins/arm/v7/opdefs/uhsub16_A88253.d index 3dd4316..f526389 100644 --- a/plugins/arm/v7/opdefs/uhsub16_A88253.d +++ b/plugins/arm/v7/opdefs/uhsub16_A88253.d @@ -37,7 +37,7 @@ @syntax { - @subid 655 + @subid 747 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 656 + @subid 748 @conv { diff --git a/plugins/arm/v7/opdefs/uhsub8_A88254.d b/plugins/arm/v7/opdefs/uhsub8_A88254.d index a47622b..a2d27ac 100644 --- a/plugins/arm/v7/opdefs/uhsub8_A88254.d +++ b/plugins/arm/v7/opdefs/uhsub8_A88254.d @@ -37,7 +37,7 @@ @syntax { - @subid 657 + @subid 749 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 658 + @subid 750 @conv { diff --git a/plugins/arm/v7/opdefs/umaal_A88255.d b/plugins/arm/v7/opdefs/umaal_A88255.d index 21cd572..6e5f7e9 100644 --- a/plugins/arm/v7/opdefs/umaal_A88255.d +++ b/plugins/arm/v7/opdefs/umaal_A88255.d @@ -37,7 +37,7 @@ @syntax { - @subid 659 + @subid 751 @conv { @@ -60,7 +60,7 @@ @syntax { - @subid 660 + @subid 752 @conv { diff --git a/plugins/arm/v7/opdefs/umlal_A88256.d b/plugins/arm/v7/opdefs/umlal_A88256.d index 5b3c98d..0eccc37 100644 --- a/plugins/arm/v7/opdefs/umlal_A88256.d +++ b/plugins/arm/v7/opdefs/umlal_A88256.d @@ -37,7 +37,7 @@ @syntax { - @subid 661 + @subid 753 @conv { @@ -60,7 +60,7 @@ @syntax { - @subid 662 + @subid 754 @assert { @@ -89,7 +89,7 @@ @syntax { - @subid 663 + @subid 755 @assert { diff --git a/plugins/arm/v7/opdefs/umull_A88257.d b/plugins/arm/v7/opdefs/umull_A88257.d index 30bc0d2..b016016 100644 --- a/plugins/arm/v7/opdefs/umull_A88257.d +++ b/plugins/arm/v7/opdefs/umull_A88257.d @@ -37,7 +37,7 @@ @syntax { - @subid 664 + @subid 756 @conv { @@ -60,7 +60,7 @@ @syntax { - @subid 665 + @subid 757 @assert { @@ -89,7 +89,7 @@ @syntax { - @subid 666 + @subid 758 @assert { diff --git a/plugins/arm/v7/opdefs/uqadd16_A88258.d b/plugins/arm/v7/opdefs/uqadd16_A88258.d index 0badd71..ed4c130 100644 --- a/plugins/arm/v7/opdefs/uqadd16_A88258.d +++ b/plugins/arm/v7/opdefs/uqadd16_A88258.d @@ -37,7 +37,7 @@ @syntax { - @subid 667 + @subid 759 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 668 + @subid 760 @conv { diff --git a/plugins/arm/v7/opdefs/uqadd8_A88259.d b/plugins/arm/v7/opdefs/uqadd8_A88259.d index a91ed2a..ca6054d 100644 --- a/plugins/arm/v7/opdefs/uqadd8_A88259.d +++ b/plugins/arm/v7/opdefs/uqadd8_A88259.d @@ -37,7 +37,7 @@ @syntax { - @subid 669 + @subid 761 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 670 + @subid 762 @conv { diff --git a/plugins/arm/v7/opdefs/uqasx_A88260.d b/plugins/arm/v7/opdefs/uqasx_A88260.d index 6876ea3..12930a2 100644 --- a/plugins/arm/v7/opdefs/uqasx_A88260.d +++ b/plugins/arm/v7/opdefs/uqasx_A88260.d @@ -37,7 +37,7 @@ @syntax { - @subid 671 + @subid 763 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 672 + @subid 764 @conv { diff --git a/plugins/arm/v7/opdefs/uqsax_A88261.d b/plugins/arm/v7/opdefs/uqsax_A88261.d index a0e6f56..d39f0f4 100644 --- a/plugins/arm/v7/opdefs/uqsax_A88261.d +++ b/plugins/arm/v7/opdefs/uqsax_A88261.d @@ -37,7 +37,7 @@ @syntax { - @subid 673 + @subid 765 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 674 + @subid 766 @conv { diff --git a/plugins/arm/v7/opdefs/uqsub16_A88262.d b/plugins/arm/v7/opdefs/uqsub16_A88262.d index abbf88d..cd77b0a 100644 --- a/plugins/arm/v7/opdefs/uqsub16_A88262.d +++ b/plugins/arm/v7/opdefs/uqsub16_A88262.d @@ -37,7 +37,7 @@ @syntax { - @subid 675 + @subid 767 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 676 + @subid 768 @conv { diff --git a/plugins/arm/v7/opdefs/uqsub8_A88263.d b/plugins/arm/v7/opdefs/uqsub8_A88263.d index 7339ed6..aa42724 100644 --- a/plugins/arm/v7/opdefs/uqsub8_A88263.d +++ b/plugins/arm/v7/opdefs/uqsub8_A88263.d @@ -37,7 +37,7 @@ @syntax { - @subid 677 + @subid 769 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 678 + @subid 770 @conv { diff --git a/plugins/arm/v7/opdefs/usad8_A88264.d b/plugins/arm/v7/opdefs/usad8_A88264.d index 8a52d62..286ba2c 100644 --- a/plugins/arm/v7/opdefs/usad8_A88264.d +++ b/plugins/arm/v7/opdefs/usad8_A88264.d @@ -37,7 +37,7 @@ @syntax { - @subid 679 + @subid 771 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 680 + @subid 772 @conv { diff --git a/plugins/arm/v7/opdefs/usada8_A88265.d b/plugins/arm/v7/opdefs/usada8_A88265.d index 115f353..bce78eb 100644 --- a/plugins/arm/v7/opdefs/usada8_A88265.d +++ b/plugins/arm/v7/opdefs/usada8_A88265.d @@ -37,7 +37,7 @@ @syntax { - @subid 681 + @subid 773 @conv { @@ -60,7 +60,7 @@ @syntax { - @subid 682 + @subid 774 @conv { diff --git a/plugins/arm/v7/opdefs/usat16_A88267.d b/plugins/arm/v7/opdefs/usat16_A88267.d index e67b940..d36f52f 100644 --- a/plugins/arm/v7/opdefs/usat16_A88267.d +++ b/plugins/arm/v7/opdefs/usat16_A88267.d @@ -37,7 +37,7 @@ @syntax { - @subid 685 + @subid 777 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 686 + @subid 778 @conv { diff --git a/plugins/arm/v7/opdefs/usat_A88266.d b/plugins/arm/v7/opdefs/usat_A88266.d index d7bbd9f..d2a2819 100644 --- a/plugins/arm/v7/opdefs/usat_A88266.d +++ b/plugins/arm/v7/opdefs/usat_A88266.d @@ -37,7 +37,7 @@ @syntax { - @subid 683 + @subid 775 @conv { @@ -60,7 +60,7 @@ @syntax { - @subid 684 + @subid 776 @conv { diff --git a/plugins/arm/v7/opdefs/usax_A88268.d b/plugins/arm/v7/opdefs/usax_A88268.d index 009122e..d85083c 100644 --- a/plugins/arm/v7/opdefs/usax_A88268.d +++ b/plugins/arm/v7/opdefs/usax_A88268.d @@ -37,7 +37,7 @@ @syntax { - @subid 687 + @subid 779 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 688 + @subid 780 @conv { diff --git a/plugins/arm/v7/opdefs/usub16_A88269.d b/plugins/arm/v7/opdefs/usub16_A88269.d index 0bdc84c..6a9a2f5 100644 --- a/plugins/arm/v7/opdefs/usub16_A88269.d +++ b/plugins/arm/v7/opdefs/usub16_A88269.d @@ -37,7 +37,7 @@ @syntax { - @subid 689 + @subid 781 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 690 + @subid 782 @conv { diff --git a/plugins/arm/v7/opdefs/usub8_A88270.d b/plugins/arm/v7/opdefs/usub8_A88270.d index d102cf1..2987469 100644 --- a/plugins/arm/v7/opdefs/usub8_A88270.d +++ b/plugins/arm/v7/opdefs/usub8_A88270.d @@ -37,7 +37,7 @@ @syntax { - @subid 691 + @subid 783 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 692 + @subid 784 @conv { diff --git a/plugins/arm/v7/opdefs/uxtab16_A88272.d b/plugins/arm/v7/opdefs/uxtab16_A88272.d index 1a996c4..0cbc980 100644 --- a/plugins/arm/v7/opdefs/uxtab16_A88272.d +++ b/plugins/arm/v7/opdefs/uxtab16_A88272.d @@ -37,7 +37,7 @@ @syntax { - @subid 695 + @subid 787 @conv { @@ -60,7 +60,7 @@ @syntax { - @subid 696 + @subid 788 @conv { diff --git a/plugins/arm/v7/opdefs/uxtab_A88271.d b/plugins/arm/v7/opdefs/uxtab_A88271.d index 33001b0..104d379 100644 --- a/plugins/arm/v7/opdefs/uxtab_A88271.d +++ b/plugins/arm/v7/opdefs/uxtab_A88271.d @@ -37,7 +37,7 @@ @syntax { - @subid 693 + @subid 785 @conv { @@ -60,7 +60,7 @@ @syntax { - @subid 694 + @subid 786 @conv { diff --git a/plugins/arm/v7/opdefs/uxtah_A88273.d b/plugins/arm/v7/opdefs/uxtah_A88273.d index 8411da9..9e454ac 100644 --- a/plugins/arm/v7/opdefs/uxtah_A88273.d +++ b/plugins/arm/v7/opdefs/uxtah_A88273.d @@ -37,7 +37,7 @@ @syntax { - @subid 697 + @subid 789 @conv { @@ -60,7 +60,7 @@ @syntax { - @subid 698 + @subid 790 @conv { diff --git a/plugins/arm/v7/opdefs/uxtb16_A88275.d b/plugins/arm/v7/opdefs/uxtb16_A88275.d index 5efa180..5d67eb8 100644 --- a/plugins/arm/v7/opdefs/uxtb16_A88275.d +++ b/plugins/arm/v7/opdefs/uxtb16_A88275.d @@ -37,7 +37,7 @@ @syntax { - @subid 702 + @subid 794 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 703 + @subid 795 @conv { diff --git a/plugins/arm/v7/opdefs/uxtb_A88274.d b/plugins/arm/v7/opdefs/uxtb_A88274.d index 36bba8a..0ac40b6 100644 --- a/plugins/arm/v7/opdefs/uxtb_A88274.d +++ b/plugins/arm/v7/opdefs/uxtb_A88274.d @@ -37,7 +37,7 @@ @syntax { - @subid 699 + @subid 791 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 700 + @subid 792 @conv { @@ -81,7 +81,7 @@ @syntax { - @subid 701 + @subid 793 @conv { diff --git a/plugins/arm/v7/opdefs/uxth_A88276.d b/plugins/arm/v7/opdefs/uxth_A88276.d index 82b9fa0..3ebf512 100644 --- a/plugins/arm/v7/opdefs/uxth_A88276.d +++ b/plugins/arm/v7/opdefs/uxth_A88276.d @@ -37,7 +37,7 @@ @syntax { - @subid 704 + @subid 796 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 705 + @subid 797 @conv { @@ -81,7 +81,7 @@ @syntax { - @subid 706 + @subid 798 @conv { diff --git a/plugins/arm/v7/opdefs/wfe_A88424.d b/plugins/arm/v7/opdefs/wfe_A88424.d index 0ef7b43..dc0f72e 100644 --- a/plugins/arm/v7/opdefs/wfe_A88424.d +++ b/plugins/arm/v7/opdefs/wfe_A88424.d @@ -37,7 +37,7 @@ @syntax { - @subid 707 + @subid 1979 @asm wfe @@ -51,7 +51,7 @@ @syntax { - @subid 708 + @subid 1980 @asm wfe.w @@ -65,7 +65,7 @@ @syntax { - @subid 709 + @subid 1981 @asm wfe diff --git a/plugins/arm/v7/opdefs/wfi_A88425.d b/plugins/arm/v7/opdefs/wfi_A88425.d index 21553e1..961c293 100644 --- a/plugins/arm/v7/opdefs/wfi_A88425.d +++ b/plugins/arm/v7/opdefs/wfi_A88425.d @@ -37,7 +37,7 @@ @syntax { - @subid 710 + @subid 1982 @asm wfi @@ -51,7 +51,7 @@ @syntax { - @subid 711 + @subid 1983 @asm wfi.w @@ -65,7 +65,7 @@ @syntax { - @subid 712 + @subid 1984 @asm wfi diff --git a/plugins/arm/v7/opdefs/yield_A88426.d b/plugins/arm/v7/opdefs/yield_A88426.d index 7e67636..66e8f39 100644 --- a/plugins/arm/v7/opdefs/yield_A88426.d +++ b/plugins/arm/v7/opdefs/yield_A88426.d @@ -37,7 +37,7 @@ @syntax { - @subid 713 + @subid 1985 @asm yield @@ -51,7 +51,7 @@ @syntax { - @subid 714 + @subid 1986 @asm yield.w @@ -65,7 +65,7 @@ @syntax { - @subid 715 + @subid 1987 @asm yield diff --git a/plugins/arm/v7/operands/Makefile.am b/plugins/arm/v7/operands/Makefile.am index 7ba6d0a..41a809e 100644 --- a/plugins/arm/v7/operands/Makefile.am +++ b/plugins/arm/v7/operands/Makefile.am @@ -4,13 +4,15 @@ noinst_LTLIBRARIES = libarmv7operands.la libarmv7operands_la_SOURCES = \ coproc.h coproc.c \ estate.h estate.c \ + it.h it.c \ limitation.h limitation.c \ maccess.h maccess.c \ offset.h offset.c \ register.h register.c \ reglist.h reglist.c \ rotation.h rotation.c \ - shift.h shift.c + shift.h shift.c \ + specreg.h specreg.c libarmv7operands_la_LIBADD = diff --git a/plugins/arm/v7/operands/estate.c b/plugins/arm/v7/operands/estate.c index 472ac2b..8460375 100644 --- a/plugins/arm/v7/operands/estate.c +++ b/plugins/arm/v7/operands/estate.c @@ -1,6 +1,6 @@ /* Chrysalide - Outil d'analyse de fichiers binaires - * endian.c - décalages de valeurs + * estate.c - décalages de valeurs * * Copyright (C) 2016-2017 Cyrille Bagard * diff --git a/plugins/arm/v7/operands/it.c b/plugins/arm/v7/operands/it.c new file mode 100644 index 0000000..f8232d1 --- /dev/null +++ b/plugins/arm/v7/operands/it.c @@ -0,0 +1,402 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * it.c - manipulation des informations de l'instruction TI + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>. + */ + + +#include "it.h" + + +#include <assert.h> + + +#include <arch/operand-int.h> +#include <common/sort.h> + + + +/* Définition d'un opérande organisant l'application d'une instruction IT (instance) */ +struct _GArmV7ITCondOperand +{ + GArchOperand parent; /* Instance parente */ + + ArmCondCode firstcond; /* Condition première */ + uint8_t mask; /* Masque de l'interprétation */ + +}; + + +/* Définition d'un opérande organisant l'application d'une instruction IT (classe) */ +struct _GArmV7ITCondOperandClass +{ + GArchOperandClass parent; /* Classe parente */ + +}; + + +/* Initialise la classe des conditions d'application d'IT. */ +static void g_armv7_itcond_operand_class_init(GArmV7ITCondOperandClass *); + +/* Initialise une instance de conditions d'application d'IT. */ +static void g_armv7_itcond_operand_init(GArmV7ITCondOperand *); + +/* Supprime toutes les références externes. */ +static void g_armv7_itcond_operand_dispose(GArmV7ITCondOperand *); + +/* Procède à la libération totale de la mémoire. */ +static void g_armv7_itcond_operand_finalize(GArmV7ITCondOperand *); + +/* Compare un opérande avec un autre. */ +static int g_armv7_itcond_operand_compare(const GArmV7ITCondOperand *, const GArmV7ITCondOperand *); + +/* Traduit un opérande en version humainement lisible. */ +static void g_armv7_itcond_operand_print(const GArmV7ITCondOperand *, GBufferLine *, AsmSyntax); + + + +/* --------------------- TRANSPOSITIONS VIA CACHE DES OPERANDES --------------------- */ + + +/* Charge un opérande depuis une mémoire tampon. */ +static bool g_armv7_itcond_operand_unserialize(GArmV7ITCondOperand *, GAsmStorage *, GBinFormat *, packed_buffer *); + +/* Sauvegarde un opérande dans une mémoire tampon. */ +static bool g_armv7_itcond_operand_serialize(const GArmV7ITCondOperand *, GAsmStorage *, packed_buffer *); + + + +/* Indique le type défini par la GLib pour l'application d'une instruction IT. */ +G_DEFINE_TYPE(GArmV7ITCondOperand, g_armv7_itcond_operand, G_TYPE_ARCH_OPERAND); + + +/****************************************************************************** +* * +* Paramètres : klass = classe à initialiser. * +* * +* Description : Initialise la classe des conditions d'application d'IT. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +static void g_armv7_itcond_operand_class_init(GArmV7ITCondOperandClass *klass) +{ + GObjectClass *object; /* Autre version de la classe */ + GArchOperandClass *operand; /* Version de classe parente */ + + object = G_OBJECT_CLASS(klass); + operand = G_ARCH_OPERAND_CLASS(klass); + + object->dispose = (GObjectFinalizeFunc/* ! */)g_armv7_itcond_operand_dispose; + object->finalize = (GObjectFinalizeFunc)g_armv7_itcond_operand_finalize; + + operand->compare = (operand_compare_fc)g_armv7_itcond_operand_compare; + operand->print = (operand_print_fc)g_armv7_itcond_operand_print; + + operand->unserialize = (unserialize_operand_fc)g_armv7_itcond_operand_unserialize; + operand->serialize = (serialize_operand_fc)g_armv7_itcond_operand_serialize; + +} + + +/****************************************************************************** +* * +* Paramètres : operand = instance à initialiser. * +* * +* Description : Initialise une instance de conditions d'application d'IT. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +static void g_armv7_itcond_operand_init(GArmV7ITCondOperand *operand) +{ + +} + + +/****************************************************************************** +* * +* Paramètres : operand = instance d'objet GLib à traiter. * +* * +* Description : Supprime toutes les références externes. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +static void g_armv7_itcond_operand_dispose(GArmV7ITCondOperand *operand) +{ + G_OBJECT_CLASS(g_armv7_itcond_operand_parent_class)->dispose(G_OBJECT(operand)); + +} + + +/****************************************************************************** +* * +* Paramètres : operand = instance d'objet GLib à traiter. * +* * +* Description : Procède à la libération totale de la mémoire. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +static void g_armv7_itcond_operand_finalize(GArmV7ITCondOperand *operand) +{ + G_OBJECT_CLASS(g_armv7_itcond_operand_parent_class)->finalize(G_OBJECT(operand)); + +} + + +/****************************************************************************** +* * +* Paramètres : a = premier opérande à consulter. * +* b = second opérande à consulter. * +* * +* Description : Compare un opérande avec un autre. * +* * +* Retour : Bilan de la comparaison. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static int g_armv7_itcond_operand_compare(const GArmV7ITCondOperand *a, const GArmV7ITCondOperand *b) +{ + int result; /* Bilan à faire remonter */ + + result = sort_boolean(a->firstcond, b->firstcond); + + if (result == 0) + result = sort_unsigned_long(a->mask, b->mask); + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : operand = opérande à traiter. * +* line = ligne tampon où imprimer l'opérande donné. * +* syntax = type de représentation demandée. * +* * +* Description : Traduit un opérande en version humainement lisible. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +static void g_armv7_itcond_operand_print(const GArmV7ITCondOperand *operand, GBufferLine *line, AsmSyntax syntax) +{ + const char *kw; /* Mot clef à imprimer */ + + switch (operand->firstcond) + { + case ACC_EQ: kw = "EQ"; break; + case ACC_NE: kw = "NE"; break; + case ACC_HS: kw = "HS"; break; + case ACC_LO: kw = "LO"; break; + case ACC_MI: kw = "MI"; break; + case ACC_PL: kw = "PL"; break; + case ACC_VS: kw = "VS"; break; + case ACC_VC: kw = "VC"; break; + case ACC_HI: kw = "HI"; break; + case ACC_LS: kw = "LS"; break; + case ACC_GE: kw = "GE"; break; + case ACC_LT: kw = "LT"; break; + case ACC_GT: kw = "GT"; break; + case ACC_LE: kw = "LE"; break; + case ACC_AL: kw = NULL; break; + case ACC_NV: kw = "NV"; break; + + default: /* Pour GCC... */ + assert(false); + kw = NULL; + break; + + } + + if (kw != NULL) + g_buffer_line_append_text(line, BLC_ASSEMBLY, kw, 2, RTT_KEY_WORD, NULL); + +} + + +/****************************************************************************** +* * +* Paramètres : firstcond = valeur brute de la condition d'exécution. * +* mask = masque d'interprétation pour l'instruction. * +* * +* Description : Crée un opérande lié à une instruction IT. * +* * +* Retour : Opérande mis en place. * +* * +* Remarques : - * +* * +******************************************************************************/ + +GArchOperand *g_armv7_itcond_operand_new(uint8_t firstcond, uint8_t mask) +{ + GArmV7ITCondOperand *result; /* Structure à retourner */ + + if (firstcond > ACC_NV) + return NULL; + + result = g_object_new(G_TYPE_ARMV7_ITCOND_OPERAND, NULL); + + result->firstcond = firstcond; + result->mask = mask; + + return G_ARCH_OPERAND(result); + +} + + +/****************************************************************************** +* * +* Paramètres : operand = opérande à consulter. * +* * +* Description : Fournit la condition associée à l'opérande. * +* * +* Retour : Condition classique pour ARMv7. * +* * +* Remarques : - * +* * +******************************************************************************/ + +ArmCondCode g_armv7_itcond_operand_get_firstcond(const GArmV7ITCondOperand *operand) +{ + ArmCondCode result; /* Condition à renvoyer */ + + result = operand->firstcond; + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : operand = opérande à consulter. * +* * +* Description : Fournit le masque d'interprétation de la condition. * +* * +* Retour : Masque de bits. * +* * +* Remarques : - * +* * +******************************************************************************/ + +uint8_t g_armv7_itcond_operand_get_mask(const GArmV7ITCondOperand *operand) +{ + uint8_t result; /* Valeur à retourner */ + + result = operand->mask; + + return result; + +} + + + +/* ---------------------------------------------------------------------------------- */ +/* TRANSPOSITIONS VIA CACHE DES OPERANDES */ +/* ---------------------------------------------------------------------------------- */ + + +/****************************************************************************** +* * +* Paramètres : operand = opérande d'assemblage à constituer. * +* storage = mécanisme de sauvegarde à manipuler. * +* format = format binaire chargé associé à l'architecture. * +* pbuf = zone tampon à remplir. * +* * +* Description : Charge un opérande depuis une mémoire tampon. * +* * +* Retour : Bilan de l'opération. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static bool g_armv7_itcond_operand_unserialize(GArmV7ITCondOperand *operand, GAsmStorage *storage, GBinFormat *format, packed_buffer *pbuf) +{ + bool result; /* Bilan à retourner */ + GArchOperandClass *parent; /* Classe parente à consulter */ + + parent = G_ARCH_OPERAND_CLASS(g_armv7_itcond_operand_parent_class); + + result = parent->unserialize(G_ARCH_OPERAND(operand), storage, format, pbuf); + + if (result) + result = extract_packed_buffer(pbuf, &operand->firstcond, sizeof(ArmCondCode), true); + + if (result) + result = extract_packed_buffer(pbuf, &operand->mask, sizeof(uint8_t), false); + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : operand = opérande d'assemblage à consulter. * +* storage = mécanisme de sauvegarde à manipuler. * +* pbuf = zone tampon à remplir. * +* * +* Description : Sauvegarde un opérande dans une mémoire tampon. * +* * +* Retour : Bilan de l'opération. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static bool g_armv7_itcond_operand_serialize(const GArmV7ITCondOperand *operand, GAsmStorage *storage, packed_buffer *pbuf) +{ + bool result; /* Bilan à retourner */ + GArchOperandClass *parent; /* Classe parente à consulter */ + + parent = G_ARCH_OPERAND_CLASS(g_armv7_itcond_operand_parent_class); + + result = parent->serialize(G_ARCH_OPERAND(operand), storage, pbuf); + + if (result) + result = extend_packed_buffer(pbuf, &operand->firstcond, sizeof(ArmCondCode), true); + + if (result) + result = extend_packed_buffer(pbuf, &operand->mask, sizeof(uint8_t), false); + + return result; + +} diff --git a/plugins/arm/v7/operands/it.h b/plugins/arm/v7/operands/it.h new file mode 100644 index 0000000..9e1706b --- /dev/null +++ b/plugins/arm/v7/operands/it.h @@ -0,0 +1,67 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * it.h - prototypes pour la manipulation des informations de l'instruction TI + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>. + */ + + +#ifndef _PLUGINS_ARM_V7_OPERANDS_IT_H +#define _PLUGINS_ARM_V7_OPERANDS_IT_H + + +#include <glib-object.h> + + +#include <arch/operand.h> + + +#include "../../cond.h" + + + +#define G_TYPE_ARMV7_ITCOND_OPERAND g_armv7_itcond_operand_get_type() +#define G_ARMV7_ITCOND_OPERAND(obj) (G_TYPE_CHECK_INSTANCE_CAST((obj), G_TYPE_ARMV7_ITCOND_OPERAND, GArmV7ITCondOperand)) +#define G_IS_ARMV7_ITCOND_OPERAND(obj) (G_TYPE_CHECK_INSTANCE_TYPE((obj), G_TYPE_ARMV7_ITCOND_OPERAND)) +#define G_ARMV7_ITCOND_OPERAND_CLASS(klass) (G_TYPE_CHECK_CLASS_CAST((klass), G_TYPE_ARMV7_ITCOND_OPERAND, GArmV7ITCondOperandClass)) +#define G_IS_ARMV7_ITCOND_OPERAND_CLASS(klass) (G_TYPE_CHECK_CLASS_TYPE((klass), G_TYPE_ARMV7_ITCOND_OPERAND)) +#define G_ARMV7_ITCOND_OPERAND_GET_CLASS(obj) (G_TYPE_INSTANCE_GET_CLASS((obj), G_TYPE_ARMV7_ITCOND_OPERAND, GArmV7ITCondOperandClass)) + + +/* Définition d'un opérande organisant l'application d'une instruction IT (instance) */ +typedef struct _GArmV7ITCondOperand GArmV7ITCondOperand; + +/* Définition d'un opérande organisant l'application d'une instruction IT (classe) */ +typedef struct _GArmV7ITCondOperandClass GArmV7ITCondOperandClass; + + +/* Indique le type défini par la GLib pour l'application d'une instruction IT. */ +GType g_armv7_itcond_operand_get_type(void); + +/* Crée un opérande lié à une instruction IT. */ +GArchOperand *g_armv7_itcond_operand_new(uint8_t, uint8_t); + +/* Fournit la condition associée à l'opérande. */ +ArmCondCode g_armv7_itcond_operand_get_firstcond(const GArmV7ITCondOperand *); + +/* Fournit le masque d'interprétation de la condition. */ +uint8_t g_armv7_itcond_operand_get_mask(const GArmV7ITCondOperand *); + + + +#endif /* _PLUGINS_ARM_V7_OPERANDS_IT_H */ diff --git a/plugins/arm/v7/operands/register.c b/plugins/arm/v7/operands/register.c index 33a14f6..412d0f9 100644 --- a/plugins/arm/v7/operands/register.c +++ b/plugins/arm/v7/operands/register.c @@ -36,6 +36,8 @@ struct _GArmV7RegisterOperand { GRegisterOperand parent; /* Instance parente */ + bool write_back; /* Mise à jour du registre ? */ + }; @@ -59,6 +61,9 @@ static void g_armv7_register_operand_dispose(GArmV7RegisterOperand *); /* Procède à la libération totale de la mémoire. */ static void g_armv7_register_operand_finalize(GArmV7RegisterOperand *); +/* Traduit un opérande en version humainement lisible. */ +static void g_armv7_register_operand_print(const GArmV7RegisterOperand *, GBufferLine *, AsmSyntax); + /* --------------------- TRANSPOSITIONS VIA CACHE DES OPERANDES --------------------- */ @@ -100,6 +105,8 @@ static void g_armv7_register_operand_class_init(GArmV7RegisterOperandClass *klas operand = G_ARCH_OPERAND_CLASS(klass); + operand->print = (operand_print_fc)g_armv7_register_operand_print; + operand->unserialize = (unserialize_operand_fc)g_armv7_register_operand_unserialize; operand->serialize = (serialize_operand_fc)g_armv7_register_operand_serialize; @@ -120,6 +127,7 @@ static void g_armv7_register_operand_class_init(GArmV7RegisterOperandClass *klas static void g_armv7_register_operand_init(GArmV7RegisterOperand *operand) { + operand->write_back = false; } @@ -164,6 +172,34 @@ static void g_armv7_register_operand_finalize(GArmV7RegisterOperand *operand) /****************************************************************************** * * +* Paramètres : operand = opérande à traiter. * +* line = ligne tampon où imprimer l'opérande donné. * +* syntax = type de représentation demandée. * +* * +* Description : Traduit un opérande en version humainement lisible. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +static void g_armv7_register_operand_print(const GArmV7RegisterOperand *operand, GBufferLine *line, AsmSyntax syntax) +{ + GArchOperandClass *parent; /* Classe parente */ + + parent = G_ARCH_OPERAND_CLASS(g_armv7_register_operand_parent_class); + + parent->print(G_ARCH_OPERAND(operand), line, syntax); + + if (operand->write_back) + g_buffer_line_append_text(line, BLC_ASSEMBLY, "!", 1, RTT_PUNCT, NULL); + +} + + +/****************************************************************************** +* * * Paramètres : reg = registre déjà en place. * * * * Description : Crée un opérande visant un registre ARMv7. * @@ -210,6 +246,48 @@ const GArmV7Register *g_armv7_register_operand_get(const GArmV7RegisterOperand * } +/****************************************************************************** +* * +* Paramètres : operand = opérande représentant un registre. * +* wback = indique si le registre est mis à jour après coup. * +* * +* Description : Détermine si le registre est mis à jour après l'opération. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +void g_armv7_register_operand_write_back(GArmV7RegisterOperand *operand, bool wback) +{ + operand->write_back = wback; + +} + + +/****************************************************************************** +* * +* Paramètres : operand = opérande représentant un registre. * +* * +* Description : Indique si le registre est mis à jour après coup. * +* * +* Retour : Evolution du registre. * +* * +* Remarques : - * +* * +******************************************************************************/ + +bool g_armv7_register_operand_is_written_back(const GArmV7RegisterOperand *operand) +{ + bool result; /* Statut à retourner */ + + result = operand->write_back; + + return result; + +} + /* ---------------------------------------------------------------------------------- */ /* TRANSPOSITIONS VIA CACHE DES OPERANDES */ @@ -237,6 +315,7 @@ static bool g_armv7_register_operand_unserialize(GArmV7RegisterOperand *operand, GArchOperandClass *parent; /* Classe parente à consulter */ uint8_t index; /* Identifiant de registre */ GArmV7Register *reg; /* Registre à intégrer */ + uint8_t wback; /* Mise à jour après coup ? */ parent = G_ARCH_OPERAND_CLASS(g_armv7_register_operand_parent_class); @@ -257,6 +336,15 @@ static bool g_armv7_register_operand_unserialize(GArmV7RegisterOperand *operand, } + if (result) + { + result = extract_packed_buffer(pbuf, &wback, sizeof(uint8_t), false); + + if (result) + operand->write_back = (wback == 1 ? true : false); + + } + return result; } @@ -281,6 +369,7 @@ static bool g_armv7_register_operand_serialize(const GArmV7RegisterOperand *oper bool result; /* Bilan à retourner */ GArchOperandClass *parent; /* Classe parente à consulter */ uint8_t index; /* Identifiant de registre */ + uint8_t wback; /* Mise à jour après coup ? */ parent = G_ARCH_OPERAND_CLASS(g_armv7_register_operand_parent_class); @@ -292,6 +381,12 @@ static bool g_armv7_register_operand_serialize(const GArmV7RegisterOperand *oper result = extend_packed_buffer(pbuf, &index, sizeof(uint8_t), false); } + if (result) + { + wback = (operand->write_back ? 1 : 0); + result = extend_packed_buffer(pbuf, &wback, sizeof(uint8_t), false); + } + return result; } diff --git a/plugins/arm/v7/operands/register.h b/plugins/arm/v7/operands/register.h index 61f5d6e..2bd13c6 100644 --- a/plugins/arm/v7/operands/register.h +++ b/plugins/arm/v7/operands/register.h @@ -60,6 +60,12 @@ GArchOperand *g_armv7_register_operand_new(GArmV7Register *); /* Fournit le registre ARMv7 associé à l'opérande. */ const GArmV7Register *g_armv7_register_operand_get(const GArmV7RegisterOperand *); +/* Détermine si le registre est mis à jour après l'opération. */ +void g_armv7_register_operand_write_back(GArmV7RegisterOperand *, bool); + +/* Indique si le registre est mis à jour après coup. */ +bool g_armv7_register_operand_is_written_back(const GArmV7RegisterOperand *); + #endif /* _PLUGINS_ARM_V7_OPERANDS_REGISTER_H */ diff --git a/plugins/arm/v7/operands/specreg.c b/plugins/arm/v7/operands/specreg.c new file mode 100644 index 0000000..233e6fd --- /dev/null +++ b/plugins/arm/v7/operands/specreg.c @@ -0,0 +1,378 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * specreg.c - registres spéciaux + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>. + */ + + +#include "specreg.h" + + +#include <arch/operand-int.h> +#include <common/sort.h> + + + +/* Définition d'un opérande de registre spécial (instance) */ +struct _GArmV7SpecRegOperand +{ + GArchOperand parent; /* Instance parente */ + + SpecRegType reg; /* Identifiant de registre */ + +}; + + +/* Définition d'un opérande de registre spécial (classe) */ +struct _GArmV7SpecRegOperandClass +{ + GArchOperandClass parent; /* Classe parente */ + +}; + + +/* Initialise la classe des opérandes de registre spécial. */ +static void g_armv7_specreg_operand_class_init(GArmV7SpecRegOperandClass *); + +/* Initialise une instance d'opérande de registre spécial. */ +static void g_armv7_specreg_operand_init(GArmV7SpecRegOperand *); + +/* Supprime toutes les références externes. */ +static void g_armv7_specreg_operand_dispose(GArmV7SpecRegOperand *); + +/* Procède à la libération totale de la mémoire. */ +static void g_armv7_specreg_operand_finalize(GArmV7SpecRegOperand *); + +/* Compare un opérande avec un autre. */ +static int g_armv7_specreg_operand_compare(const GArmV7SpecRegOperand *, const GArmV7SpecRegOperand *); + +/* Traduit un opérande en version humainement lisible. */ +static void g_armv7_specreg_operand_print(const GArmV7SpecRegOperand *, GBufferLine *, AsmSyntax); + + + +/* --------------------- TRANSPOSITIONS VIA CACHE DES OPERANDES --------------------- */ + + +/* Charge un opérande depuis une mémoire tampon. */ +static bool g_armv7_specreg_operand_unserialize(GArmV7SpecRegOperand *, GAsmStorage *, GBinFormat *, packed_buffer *); + +/* Sauvegarde un opérande dans une mémoire tampon. */ +static bool g_armv7_specreg_operand_serialize(const GArmV7SpecRegOperand *, GAsmStorage *, packed_buffer *); + + + +/* Indique le type défini par la GLib pour un opérande de registre spécial ARMv7. */ +G_DEFINE_TYPE(GArmV7SpecRegOperand, g_armv7_specreg_operand, G_TYPE_ARCH_OPERAND); + + +/****************************************************************************** +* * +* Paramètres : klass = classe à initialiser. * +* * +* Description : Initialise la classe des opérandes de registre spécial. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +static void g_armv7_specreg_operand_class_init(GArmV7SpecRegOperandClass *klass) +{ + GObjectClass *object; /* Autre version de la classe */ + GArchOperandClass *operand; /* Version de classe parente */ + + object = G_OBJECT_CLASS(klass); + operand = G_ARCH_OPERAND_CLASS(klass); + + object->dispose = (GObjectFinalizeFunc/* ! */)g_armv7_specreg_operand_dispose; + object->finalize = (GObjectFinalizeFunc)g_armv7_specreg_operand_finalize; + + operand->compare = (operand_compare_fc)g_armv7_specreg_operand_compare; + operand->print = (operand_print_fc)g_armv7_specreg_operand_print; + + operand->unserialize = (unserialize_operand_fc)g_armv7_specreg_operand_unserialize; + operand->serialize = (serialize_operand_fc)g_armv7_specreg_operand_serialize; + +} + + +/****************************************************************************** +* * +* Paramètres : operand = instance à initialiser. * +* * +* Description : Initialise une instance d'opérande de registre spécial. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +static void g_armv7_specreg_operand_init(GArmV7SpecRegOperand *operand) +{ + +} + + +/****************************************************************************** +* * +* Paramètres : operand = instance d'objet GLib à traiter. * +* * +* Description : Supprime toutes les références externes. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +static void g_armv7_specreg_operand_dispose(GArmV7SpecRegOperand *operand) +{ + G_OBJECT_CLASS(g_armv7_specreg_operand_parent_class)->dispose(G_OBJECT(operand)); + +} + + +/****************************************************************************** +* * +* Paramètres : operand = instance d'objet GLib à traiter. * +* * +* Description : Procède à la libération totale de la mémoire. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +static void g_armv7_specreg_operand_finalize(GArmV7SpecRegOperand *operand) +{ + G_OBJECT_CLASS(g_armv7_specreg_operand_parent_class)->finalize(G_OBJECT(operand)); + +} + + +/****************************************************************************** +* * +* Paramètres : a = premier opérande à consulter. * +* b = second opérande à consulter. * +* * +* Description : Compare un opérande avec un autre. * +* * +* Retour : Bilan de la comparaison. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static int g_armv7_specreg_operand_compare(const GArmV7SpecRegOperand *a, const GArmV7SpecRegOperand *b) +{ + int result; /* Bilan à faire remonter */ + + result = sort_unsigned_long(a->reg, b->reg); + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : operand = opérande à traiter. * +* line = ligne tampon où imprimer l'opérande donné. * +* syntax = type de représentation demandée. * +* * +* Description : Traduit un opérande en version humainement lisible. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +static void g_armv7_specreg_operand_print(const GArmV7SpecRegOperand *operand, GBufferLine *line, AsmSyntax syntax) +{ + switch (operand->reg) + { + case SRT_APSR: + g_buffer_line_append_text(line, BLC_ASSEMBLY, "APSR", 4, RTT_REGISTER, NULL); + break; + + case SRT_CPSR: + g_buffer_line_append_text(line, BLC_ASSEMBLY, "CPSR", 4, RTT_REGISTER, NULL); + break; + + case SRT_SPSR: + g_buffer_line_append_text(line, BLC_ASSEMBLY, "SPSR", 4, RTT_REGISTER, NULL); + break; + + case SRT_APSR_NZCVQ: + g_buffer_line_append_text(line, BLC_ASSEMBLY, "APSR_nzcvq", 10, RTT_REGISTER, NULL); + break; + + case SRT_APSR_G: + g_buffer_line_append_text(line, BLC_ASSEMBLY, "APSR_g", 6, RTT_REGISTER, NULL); + break; + + case SRT_APSR_NZCVQG: + g_buffer_line_append_text(line, BLC_ASSEMBLY, "APSR_nzcvqg", 11, RTT_REGISTER, NULL); + break; + + case SRT_FPSID: + g_buffer_line_append_text(line, BLC_ASSEMBLY, "FPSID", 5, RTT_REGISTER, NULL); + break; + + case SRT_FPSCR: + g_buffer_line_append_text(line, BLC_ASSEMBLY, "FPSCR", 5, RTT_REGISTER, NULL); + break; + + case SRT_MVFR1: + g_buffer_line_append_text(line, BLC_ASSEMBLY, "MVFR1", 5, RTT_REGISTER, NULL); + break; + + case SRT_MVFR0: + g_buffer_line_append_text(line, BLC_ASSEMBLY, "MVFR0", 5, RTT_REGISTER, NULL); + break; + + case SRT_FPEXC: + g_buffer_line_append_text(line, BLC_ASSEMBLY, "FPEXC", 5, RTT_REGISTER, NULL); + break; + + } + +} + + +/****************************************************************************** +* * +* Paramètres : big = indication sur le boutisme à représenter. * +* * +* Description : Crée une représentation d'opérande de registre spécial. * +* * +* Retour : Opérande mis en place. * +* * +* Remarques : - * +* * +******************************************************************************/ + +GArchOperand *g_armv7_specreg_operand_new(SpecRegType reg) +{ + GArmV7SpecRegOperand *result; /* Structure à retourner */ + + result = g_object_new(G_TYPE_ARMV7_SPECREG_OPERAND, NULL); + + result->reg = reg; + + return G_ARCH_OPERAND(result); + +} + + +/****************************************************************************** +* * +* Paramètres : operand = opérande à consulter. * +* * +* Description : Indique le type de registre spécial représenté. * +* * +* Retour : Identifiant de registre spécial. * +* * +* Remarques : - * +* * +******************************************************************************/ + +SpecRegType g_armv7_specreg_operand_get_register(const GArmV7SpecRegOperand *operand) +{ + SpecRegType result; /* Désignation à retourner */ + + result = operand->reg; + + return result; + +} + + + +/* ---------------------------------------------------------------------------------- */ +/* TRANSPOSITIONS VIA CACHE DES OPERANDES */ +/* ---------------------------------------------------------------------------------- */ + + +/****************************************************************************** +* * +* Paramètres : operand = opérande d'assemblage à constituer. * +* storage = mécanisme de sauvegarde à manipuler. * +* format = format binaire chargé associé à l'architecture. * +* pbuf = zone tampon à remplir. * +* * +* Description : Charge un opérande depuis une mémoire tampon. * +* * +* Retour : Bilan de l'opération. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static bool g_armv7_specreg_operand_unserialize(GArmV7SpecRegOperand *operand, GAsmStorage *storage, GBinFormat *format, packed_buffer *pbuf) +{ + bool result; /* Bilan à retourner */ + GArchOperandClass *parent; /* Classe parente à consulter */ + + parent = G_ARCH_OPERAND_CLASS(g_armv7_specreg_operand_parent_class); + + result = parent->unserialize(G_ARCH_OPERAND(operand), storage, format, pbuf); + + if (result) + result = extract_packed_buffer(pbuf, &operand->reg, sizeof(SpecRegType), true); + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : operand = opérande d'assemblage à consulter. * +* storage = mécanisme de sauvegarde à manipuler. * +* pbuf = zone tampon à remplir. * +* * +* Description : Sauvegarde un opérande dans une mémoire tampon. * +* * +* Retour : Bilan de l'opération. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static bool g_armv7_specreg_operand_serialize(const GArmV7SpecRegOperand *operand, GAsmStorage *storage, packed_buffer *pbuf) +{ + bool result; /* Bilan à retourner */ + GArchOperandClass *parent; /* Classe parente à consulter */ + + parent = G_ARCH_OPERAND_CLASS(g_armv7_specreg_operand_parent_class); + + result = parent->serialize(G_ARCH_OPERAND(operand), storage, pbuf); + + if (result) + result = extend_packed_buffer(pbuf, &operand->reg, sizeof(SpecRegType), true); + + return result; + +} diff --git a/plugins/arm/v7/operands/specreg.h b/plugins/arm/v7/operands/specreg.h new file mode 100644 index 0000000..2d1d744 --- /dev/null +++ b/plugins/arm/v7/operands/specreg.h @@ -0,0 +1,79 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * specreg.h - prototypes pour les registres spéciaux + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>. + */ + + +#ifndef _PLUGINS_ARM_V7_OPERANDS_SPECREG_H +#define _PLUGINS_ARM_V7_OPERANDS_SPECREG_H + + +#include <glib-object.h> + + +#include <arch/operand.h> + + + +#define G_TYPE_ARMV7_SPECREG_OPERAND g_armv7_specreg_operand_get_type() +#define G_ARMV7_SPECREG_OPERAND(obj) (G_TYPE_CHECK_INSTANCE_CAST((obj), G_TYPE_ARMV7_SPECREG_OPERAND, GArmV7SpecRegOperand)) +#define G_IS_ARMV7_SPECREG_OPERAND(obj) (G_TYPE_CHECK_INSTANCE_TYPE((obj), G_TYPE_ARMV7_SPECREG_OPERAND)) +#define G_ARMV7_SPECREG_OPERAND_CLASS(klass) (G_TYPE_CHECK_CLASS_CAST((klass), G_TYPE_ARMV7_SPECREG_OPERAND, GArmV7SpecRegOperandClass)) +#define G_IS_ARMV7_SPECREG_OPERAND_CLASS(klass) (G_TYPE_CHECK_CLASS_TYPE((klass), G_TYPE_ARMV7_SPECREG_OPERAND)) +#define G_ARMV7_SPECREG_OPERAND_GET_CLASS(obj) (G_TYPE_INSTANCE_GET_CLASS((obj), G_TYPE_ARMV7_SPECREG_OPERAND, GArmV7SpecRegOperandClass)) + + +/* Définition d'un opérande de registre spécial (instance) */ +typedef struct _GArmV7SpecRegOperand GArmV7SpecRegOperand; + +/* Définition d'un opérande de registre spécial (classe) */ +typedef struct _GArmV7SpecRegOperandClass GArmV7SpecRegOperandClass; + + +/* Désignation des registres spéciaux */ +typedef enum _SpecRegType +{ + SRT_APSR, + SRT_CPSR, + SRT_SPSR, + SRT_APSR_NZCVQ, + SRT_APSR_G, + SRT_APSR_NZCVQG, + SRT_FPSID, + SRT_FPSCR, + SRT_MVFR1, + SRT_MVFR0, + SRT_FPEXC + +} SpecRegType; + + +/* Indique le type défini par la GLib pour un opérande de registre spécial ARMv7. */ +GType g_armv7_specreg_operand_get_type(void); + +/* Crée une représentation d'opérande de registre spécial. */ +GArchOperand *g_armv7_specreg_operand_new(SpecRegType ); + +/* Indique le type de registre spécial représenté. */ +SpecRegType g_armv7_specreg_operand_get_register(const GArmV7SpecRegOperand *); + + + +#endif /* _PLUGINS_ARM_V7_OPERANDS_SPECREG_H */ |