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| author | Cyrille Bagard <nocbos@gmail.com> | 2014-11-25 08:05:22 (GMT) |
|---|---|---|
| committer | Cyrille Bagard <nocbos@gmail.com> | 2014-11-25 08:05:22 (GMT) |
| commit | 7a42f3772ab31bb9c756fc5c5c86c531c04b1d70 (patch) | |
| tree | 1dc6440b1a1dde546c5eccf7744e1df5128bd833 /src/arch/arm/v7/helpers.h | |
| parent | 16f9d3b943e272112e01f5bc51e922e2ea2ddfb8 (diff) | |
Extended the range of supported ARMv7 instructions.
git-svn-id: svn://svn.gna.org/svn/chrysalide/trunk@427 abbe820e-26c8-41b2-8c08-b7b2b41f8b0a
Diffstat (limited to 'src/arch/arm/v7/helpers.h')
| -rw-r--r-- | src/arch/arm/v7/helpers.h | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/src/arch/arm/v7/helpers.h b/src/arch/arm/v7/helpers.h index 66a98f6..d72bb88 100644 --- a/src/arch/arm/v7/helpers.h +++ b/src/arch/arm/v7/helpers.h @@ -29,6 +29,7 @@ #include "pseudo.h" +#include "operands/shift.h" #include "../../operand.h" @@ -49,7 +50,35 @@ g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __val); \ }) +#define DecodeImmShift(type, imm5) \ + ({ \ + GArchOperand *__result; \ + SRType __shift_t; \ + uint32_t __shift_n; \ + GArchOperand *__op_n; \ + if (!armv7_decode_imm_shift(type, imm5, &__shift_t, &__shift_n)) \ + __result = NULL; \ + else \ + { \ + __op_n = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __shift_n); \ + __result = g_armv7_shift_operand_new(__shift_t, __op_n); \ + } \ + __result; \ + }) + + +#if 0 +// DecodeRegShift() +// ================ +SRType DecodeRegShift(bits(2) type) +case type of +when '00' shift_t = SRType_LSL; +when '01' shift_t = SRType_LSR; +when '10' shift_t = SRType_ASR; +when '11' shift_t = SRType_ROR; +return shift_t; +#endif |