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-rw-r--r--src/arch/arm/v7/helpers.h29
1 files changed, 29 insertions, 0 deletions
diff --git a/src/arch/arm/v7/helpers.h b/src/arch/arm/v7/helpers.h
index 66a98f6..d72bb88 100644
--- a/src/arch/arm/v7/helpers.h
+++ b/src/arch/arm/v7/helpers.h
@@ -29,6 +29,7 @@
#include "pseudo.h"
+#include "operands/shift.h"
#include "../../operand.h"
@@ -49,7 +50,35 @@
g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __val); \
})
+#define DecodeImmShift(type, imm5) \
+ ({ \
+ GArchOperand *__result; \
+ SRType __shift_t; \
+ uint32_t __shift_n; \
+ GArchOperand *__op_n; \
+ if (!armv7_decode_imm_shift(type, imm5, &__shift_t, &__shift_n)) \
+ __result = NULL; \
+ else \
+ { \
+ __op_n = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __shift_n); \
+ __result = g_armv7_shift_operand_new(__shift_t, __op_n); \
+ } \
+ __result; \
+ })
+
+
+#if 0
+// DecodeRegShift()
+// ================
+SRType DecodeRegShift(bits(2) type)
+case type of
+when '00' shift_t = SRType_LSL;
+when '01' shift_t = SRType_LSR;
+when '10' shift_t = SRType_ASR;
+when '11' shift_t = SRType_ROR;
+return shift_t;
+#endif