diff options
Diffstat (limited to 'plugins/arm/v7/opdefs/add_A8810.d')
| -rw-r--r-- | plugins/arm/v7/opdefs/add_A8810.d | 80 |
1 files changed, 59 insertions, 21 deletions
diff --git a/plugins/arm/v7/opdefs/add_A8810.d b/plugins/arm/v7/opdefs/add_A8810.d index 2047276..c7f30b4 100644 --- a/plugins/arm/v7/opdefs/add_A8810.d +++ b/plugins/arm/v7/opdefs/add_A8810.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title ADD (SP plus register, Thumb) -@desc This instruction adds an optionally-shifted register value to the SP value, and writes the result to the destination register. +@id 9 + +@desc { + + This instruction adds an optionally-shifted register value to the SP value, and writes the result to the destination register. + +} @encoding (t1) { @half 0 1 0 0 0 1 0 0 DM(1) 1 1 0 1 Rdm(3) - @syntax <reg_DM_1> <SP> <reg_DM_2> + @syntax { + + @conv { - @conv { + reg_D = Register(DM:Rdm) + reg_SP = Register(13) + reg_M = Register(DM:Rdm) - reg_DM_1 = Register(DM:Rdm) - reg_DM_2 = Register(DM:Rdm) - SP = Register(13) + } + + @asm add ?reg_D reg_SP reg_M } @@ -45,12 +55,17 @@ @half 0 1 0 0 0 1 0 0 1 Rm(4) 1 0 1 - @syntax <SP> <reg_M> + @syntax { + + @conv { + + reg_D = Register(13) + reg_SP = Register(13) + reg_M = Register(Rm) - @conv { + } - reg_M = Register(Rm) - SP = Register(13) + @asm add ?reg_D reg_SP reg_M } @@ -60,22 +75,45 @@ @word 1 1 1 0 1 0 1 1 0 0 0 S(1) 1 1 0 1 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - @syntax <reg_D> <SP> <reg_M> <?shift> + @syntax { + + @assert { + + S == 0 - @conv { + } - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm3:imm2) - SP = Register(13) + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm add.w ?reg_D reg_SP reg_M ?shift } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @asm adds.w ?reg_D reg_SP reg_M ?shift } |