diff options
Diffstat (limited to 'plugins/arm/v7')
231 files changed, 11977 insertions, 4720 deletions
diff --git a/plugins/arm/v7/Makefile.am b/plugins/arm/v7/Makefile.am index e2fc96c..bac6841 100644 --- a/plugins/arm/v7/Makefile.am +++ b/plugins/arm/v7/Makefile.am @@ -7,7 +7,7 @@ libarmv7_la_SOURCES = \ core.h core.c \ cregister.h cregister.c \ fetch.h fetch.c \ - helpers.h helpers.c \ + helpers.h \ instruction.h instruction.c \ link.h link.c \ post.h post.c \ diff --git a/plugins/arm/v7/helpers.c b/plugins/arm/v7/helpers.c deleted file mode 100644 index 637cd9c..0000000 --- a/plugins/arm/v7/helpers.c +++ /dev/null @@ -1,277 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * helpers.c - aide à la mise en place des opérandes ARMv7 - * - * Copyright (C) 2014-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#include "helpers.h" - - -#include <arch/register.h> -#include <arch/immediate.h> -#include <common/asm.h> -#include <common/bconst.h> - - -#include "register.h" - - - -/****************************************************************************** -* * -* Paramètres : x = valeur sur 32 bits maximum à traiter. * -* shift = nombre de décalages visés. * -* * -* Description : Effectue une rotation vers la droit d'une valeur. * -* * -* Retour : Adresse de la structure mise en place. * -* * -* Remarques : Correspond à la pseudo fonction 'ROR_C'. * -* * -******************************************************************************/ - -GArchOperand *ror_armv7_imm(uint32_t x, unsigned int shift) -{ - GArchOperand *result; /* Opérande à faire remonter */ - uint32_t val32; /* Valeur sur 32 bits */ - - shift %= 32; - - val32 = (x >> shift) | (x << (32 - shift)); - - result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, val32); - - return result; - -} - - - - - - - - - - - - -#if 0 - -// Shift_C() -// ========= -(bits(N), bit) Shift_C(bits(N) value, SRType type, integer amount, bit carry_in) -assert !(type == SRType_RRX && amount != 1); -if amount == 0 then -(result, carry_out) = (value, carry_in); -else -case type of - -when SRType_LSL -(result, carry_out) = LSL_C(value, amount); - -when SRType_LSR -(result, carry_out) - -when SRType_ASR -(result, carry_out) - -when SRType_ROR -(result, carry_out) - -when SRType_RRX -(result, carry_out) -= LSR_C(value, amount); -= ASR_C(value, amount); -= ROR_C(value, amount); -= RRX_C(value, carry_in); - -#endif - - - - - - -/****************************************************************************** -* * -* Paramètres : value = valeur sur 32 bits maximum à traiter. * -* topbit = valeur du bit de poids fort manipulé. * -* size = taille de la valeur finale à constituer. * -* * -* Description : Crée un opérande de valeur immédiate avec extension de signe.* -* * -* Retour : Adresse de la structure mise en place. * -* * -* Remarques : - * -* * -******************************************************************************/ - -GArchOperand *sign_extend_armv7_imm(uint32_t value, bool topbit, unsigned int size) -{ - GArchOperand *result; /* Opérande à faire remonter */ - unsigned int msb; /* Position du premier bit à 1 */ - MemoryDataSize mds; /* Conversion de la taille */ - uint32_t val4; /* Valeur sur 4 bits */ - uint32_t val8; /* Valeur sur 8 bits */ - uint32_t val16; /* Valeur sur 16 bits */ - uint32_t val32; /* Valeur sur 32 bits */ - unsigned int i; /* Boucle de parcours */ - - result = NULL; - - topbit &= msb_32(value, &msb); - - switch (size) - { - -#define SIGN_EXTEND_CASE(sz) \ - case sz: \ - mds = MDS_ ## sz ## _BITS_SIGNED; \ - val ## sz = value; \ - if (topbit) \ - for (i = msb; i < sz; i++) \ - val ## sz |= (1 << i); \ - result = g_imm_operand_new_from_value(mds, val ## sz); \ - break; - - SIGN_EXTEND_CASE(4); - SIGN_EXTEND_CASE(8); - SIGN_EXTEND_CASE(16); - SIGN_EXTEND_CASE(32); - - } - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : value = valeur sur 32 bits maximum à traiter. * -* * -* Description : Etend une valeur immédiate en mode 'Thumb' ARMv7. * -* * -* Retour : Adresse de la structure mise en place. * -* * -* Remarques : - * -* * -******************************************************************************/ - -GArchOperand *thumb_expand_armv7_imm(uint32_t value) -{ - GArchOperand *result; /* Opérande à faire remonter */ - uint8_t byte; /* Octet à reproduire */ - uint32_t val32; /* Valeur sur 32 bits */ - uint32_t unrotated; /* Transformation à décaller */ - - result = NULL; - - if (((value >> 10) & b11) == b00) - { - byte = value & 0xff; - - switch ((value >> 8) & b11) - { - case b00: - result = zero_extend_armv7_imm(byte, 32); - break; - - case b01: - if (byte == 0) return NULL; - val32 = byte << 16 | byte; - result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, val32); - break; - - case b10: - if (byte == 0) return NULL; - val32 = byte << 24 | byte << 8; - result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, val32); - break; - - case b11: - if (byte == 0) return NULL; - val32 = byte << 24 | byte << 16 | byte << 8 | byte; - result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, val32); - break; - - } - - } - else - { - unrotated = 1 << 7 | (value & 0x3f); - result = ror_armv7_imm(unrotated, (value >> 7) & 0x1f); - } - - return result; - -} - - - - - - -/****************************************************************************** -* * -* Paramètres : value = valeur sur 32 bits maximum à traiter. * -* size = taille de la valeur finale à constituer. * -* * -* Description : Réalise un simple transtypage de valeur entière. * -* * -* Retour : Adresse de la structure mise en place. * -* * -* Remarques : Correspond à la pseudo fonction 'ZeroExtend'. * -* * -******************************************************************************/ - -GArchOperand *zero_extend_armv7_imm(uint32_t value, unsigned int size) -{ - GArchOperand *result; /* Opérande à faire remonter */ - MemoryDataSize mds; /* Conversion de la taille */ - uint32_t val4; /* Valeur sur 4 bits */ - uint32_t val8; /* Valeur sur 8 bits */ - uint32_t val16; /* Valeur sur 16 bits */ - uint32_t val32; /* Valeur sur 32 bits */ - - result = NULL; - - switch (size) - { - -#define ZERO_EXTEND_CASE(sz) \ - case sz: \ - mds = MDS_ ## sz ## _BITS_UNSIGNED; \ - val ## sz = value; \ - result = g_imm_operand_new_from_value(mds, val ## sz); \ - break; - - ZERO_EXTEND_CASE(4); - ZERO_EXTEND_CASE(8); - ZERO_EXTEND_CASE(16); - ZERO_EXTEND_CASE(32); - - } - - return result; - -} diff --git a/plugins/arm/v7/helpers.h b/plugins/arm/v7/helpers.h index 94b85f9..aa3de34 100644 --- a/plugins/arm/v7/helpers.h +++ b/plugins/arm/v7/helpers.h @@ -25,245 +25,265 @@ #define _PLUGINS_ARM_V7_HELPERS_H -#include <arch/operand.h> +#include <arch/immediate.h> +#include <arch/register.h> -#include "cregister.h" #include "pseudo.h" +#include "register.h" #include "operands/coproc.h" #include "operands/estate.h" -#include "operands/limitation.h" #include "operands/maccess.h" -#include "operands/offset.h" #include "operands/reglist.h" #include "operands/rotation.h" #include "operands/shift.h" -#include "../register.h" +/** + * Définitions élaborées à partir des spécifications. + */ -#define BarrierLimitation(opt) \ - ({ \ - GArchOperand *__result; \ - __result = g_armv7_limitation_operand_new(opt); \ - __result; \ +#define ARMExpandImm(imm12) \ + ({ \ + GArchOperand *__result; \ + uint32_t __val; \ + if (armv7_arm_expand_imm(imm12, &__val)) \ + __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __val); \ + else \ + __result = NULL; \ + __result; \ }) -#define BitDiff(msb, lsb) \ - ({ \ - GArchOperand *__result; \ - uint32_t __width; \ - __width = g_imm_operand_get_raw_value(G_IMM_OPERAND(msb)); \ - __width -= g_imm_operand_get_raw_value(G_IMM_OPERAND(lsb)); \ - __width += 1; \ - __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __width); \ - __result; \ +#define ARMExpandImm_C(imm12, c) \ + ({ \ + GArchOperand *__result; \ + uint32_t __val; \ + if (armv7_arm_expand_imm_c(imm12, (bool []) { c }, &__val)) \ + __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __val); \ + else \ + __result = NULL; \ + __result; \ }) -#define BuildImm8(val) \ - ({ \ - GArchOperand *__result; \ - __result = g_imm_operand_new_from_value(MDS_8_BITS_UNSIGNED, (uint8_t)val); \ - __result; \ +#define BitDiff(msb, lsb) \ + ({ \ + GArchOperand *__result; \ + uint32_t __width; \ + __width = msb - lsb + 1; \ + __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __width); \ + __result; \ }) -#define BuildImm16(val) \ - ({ \ - GArchOperand *__result; \ - __result = g_imm_operand_new_from_value(MDS_16_BITS_UNSIGNED, (uint16_t)val); \ - __result; \ +#define BuildRegShift(type, reg) \ + ({ \ + GArchOperand *__result; \ + SRType __shift_t; \ + if (!armv7_decode_reg_shift(type, &__shift_t)) \ + __result = NULL; \ + else \ + __result = g_armv7_shift_operand_new(__shift_t, reg); \ + __result; \ }) -#define CoProcessor(idx) \ - ({ \ - GArchOperand *__result; \ - __result = g_armv7_coproc_operand_new(idx); \ - __result; \ +#define CoProcessor(idx) \ + ({ \ + GArchOperand *__result; \ + __result = g_armv7_coproc_operand_new(idx); \ + __result; \ }) -#define CRegister(idx) \ - ({ \ - GArchOperand *__result; \ - GArmV7CRegister *__reg; \ - __reg = g_armv7_cregister_new(idx); \ - if (__reg == NULL) \ - __result = NULL; \ - else \ - __result = g_register_operand_new(G_ARCH_REGISTER(__reg)); \ - __result; \ +#define DecodeImmShift(type, imm5) \ + ({ \ + GArchOperand *__result; \ + SRType __shift_t; \ + uint8_t __shift_n; \ + GArchOperand *__op_n; \ + if (!armv7_decode_imm_shift(type, imm5, &__shift_t, &__shift_n)) \ + __result = NULL; \ + else \ + { \ + __op_n = g_imm_operand_new_from_value(MDS_8_BITS_UNSIGNED, __shift_n); \ + __result = g_armv7_shift_operand_new(__shift_t, __op_n); \ + } \ + __result; \ }) -#define IncWidth(widthm1) \ - ({ \ - GArchOperand *__result; \ - uint32_t __width; \ - __width = widthm1 + 1; \ - __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __width); \ - __result; \ +#define DecodeImmShiftAmount(type, imm5) \ + ({ \ + GArchOperand *__result; \ + uint8_t __shift_n; \ + if (!armv7_decode_imm_shift(type, imm5, (SRType []) { 0 }, &__shift_n)) \ + __result = NULL; \ + else \ + __result = g_imm_operand_new_from_value(MDS_8_BITS_UNSIGNED, __shift_n);\ + __result; \ }) -#define DecodeImmShift(type, imm5) \ - ({ \ - GArchOperand *__result; \ - SRType __shift_t; \ - uint32_t __shift_n; \ - GArchOperand *__op_n; \ - if (!armv7_decode_imm_shift(type, imm5, &__shift_t, &__shift_n)) \ - __result = NULL; \ - else \ - { \ - __op_n = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __shift_n); \ - __result = g_armv7_shift_operand_new(__shift_t, __op_n); \ - } \ - __result; \ +#define Endian(big) \ + ({ \ + GArchOperand *__result; \ + __result = g_armv7_endian_operand_new(big); \ + __result; \ }) -#define EndianState(big) \ - ({ \ - GArchOperand *__result; \ - __result = g_armv7_endian_operand_new(big); \ - __result; \ +#define FixedShift(type, imm5) \ + ({ \ + GArchOperand *__result; \ + uint8_t __shift_n; \ + __shift_n = imm5; \ + __result = g_imm_operand_new_from_value(MDS_8_BITS_UNSIGNED, __shift_n); \ + __result; \ }) -#define MakeMemoryAccess(base, off, shift, index, add, wback) \ - ({ \ - GArchOperand *__result; \ - GArchOperand *__offset; \ - if (off != NULL) \ - __offset = g_armv7_offset_operand_new(add, off); \ - else \ - __offset = NULL; \ - __result = g_armv7_maccess_operand_new(base, __offset, shift, index, wback); \ - __result; \ +#define MemAccessOffset(base, off) \ + ({ \ + GArchOperand *__result; \ + __result = g_armv7_maccess_operand_new(base, off, NULL, false, false); \ + __result; \ }) -#define NextRegister(prev) \ - ({ \ - GRegisterOperand *__prev_op; \ - GArchRegister *__reg; \ - uint8_t __id; \ - __prev_op = G_REGISTER_OPERAND(prev); \ - __reg = g_register_operand_get_register(__prev_op); \ - __id = g_arm_register_get_index(G_ARM_REGISTER(__reg)); \ - Register(__id + 1); \ +#define MemAccessOffsetExtended(base, off, shift) \ + ({ \ + GArchOperand *__result; \ + __result = g_armv7_maccess_operand_new(base, off, shift, false, false); \ + __result; \ }) -#define RawValue(val) \ - ({ \ - GArchOperand *__result; \ - __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, (uint32_t)val); \ - __result; \ +#define MemAccessPreIndexed(base, off) \ + ({ \ + GArchOperand *__result; \ + __result = g_armv7_maccess_operand_new(base, off, NULL, false, true); \ + __result; \ }) -#define Register(idx) \ - ({ \ - GArchOperand *__result; \ - GArmV7Register *__reg; \ - __reg = g_armv7_register_new(idx); \ - if (__reg == NULL) \ - __result = NULL; \ - else \ - __result = g_register_operand_new(G_ARCH_REGISTER(__reg)); \ - __result; \ +#define MemAccessPreIndexedExtended(base, off, shift) \ + ({ \ + GArchOperand *__result; \ + __result = g_armv7_maccess_operand_new(base, off, shift, false, true); \ + __result; \ }) -#define RegisterShift(shift_t, rs) \ - ({ \ - GArchOperand *__result; \ - GArchOperand *__reg; \ - __reg = Register(rs); \ - if (__reg == NULL) \ - __result = NULL; \ - else \ - __result = g_armv7_shift_operand_new(shift_t, __reg); \ - __result; \ +#define MemAccessPostIndexed(base, off) \ + ({ \ + GArchOperand *__result; \ + __result = g_armv7_maccess_operand_new(base, off, NULL, true, true); \ + __result; \ }) -#define Rotation(val5) \ +#define MemAccessPostIndexedExtended(base, off, shift) \ ({ \ GArchOperand *__result; \ - uint8_t __rot; \ - GArchOperand *__rot_op; \ - __rot = val5; \ - __rot_op = g_imm_operand_new_from_value(MDS_8_BITS_UNSIGNED, __rot); \ - __result = g_armv7_rotation_operand_new(__rot_op); \ - if (__result == NULL) \ - g_object_unref(G_OBJECT(__rot_op)); \ + __result = g_armv7_maccess_operand_new(base, off, shift, true, true); \ __result; \ }) -#define UInt(val) \ - ({ \ - GArchOperand *__result; \ - __result = g_imm_operand_new_from_value(MDS_8_BITS_UNSIGNED, (uint8_t)val); \ - __result; \ +#define MinusBitDiff(msb, lsb) \ + ({ \ + GArchOperand *__result; \ + uint32_t __width; \ + __width = msb - lsb + 1 + 1; \ + __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __width); \ + __result; \ }) +#define NextRegister(idx) \ + ({ \ + GArchOperand *__result; \ + GArmV7Register *__reg; \ + __reg = g_armv7_register_new(idx + 1); \ + if (__reg == NULL) \ + __result = NULL; \ + else \ + __result = g_register_operand_new(G_ARCH_REGISTER(__reg)); \ + __result; \ + }) -//#define DecodeImmShift(raw_type, raw_imm5); -//g_armv7_shift_operand_new(SRType type, GArchOperand *value) - - - -//#define MakeMemoryAccess(base, off, shift, index, add, wback) NULL - -//g_armv7_maccess_operand_new(GArchOperand *base, GArchOperand *offset, GArchOperand *shift, bool indexed, bool writeb) +#define SignExtend(val, size, top) \ + ({ \ + GArchOperand *__result; \ + MemoryDataSize __mds; \ + uint ## size ## _t __val; \ + __mds = MDS_ ## size ## _BITS_SIGNED; \ + __val = armv7_sign_extend(val, top, size); \ + __result = g_imm_operand_new_from_value(__mds, __val); \ + __result; \ + }) -//g_armv7_offset_operand_new(add, off) +#define SingleRegList(t) \ + ({ \ + GArchOperand *__result; \ + __result = g_armv7_reglist_operand_new(1 << t); \ + __result; \ + }) +#define Register(idx) \ + ({ \ + GArchOperand *__result; \ + GArmV7Register *__reg; \ + __reg = g_armv7_register_new(idx); \ + if (__reg == NULL) \ + __result = NULL; \ + else \ + __result = g_register_operand_new(G_ARCH_REGISTER(__reg)); \ + __result; \ + }) -//////////////////// -#define Imm16(imm16) \ - ({ \ - GArchOperand *__result; \ - __result = g_imm_operand_new_from_value(MDS_16_BITS_UNSIGNED, (uint16_t)imm16); \ - __result; \ +#define RegList(mask) \ + ({ \ + GArchOperand *__result; \ + __result = g_armv7_reglist_operand_new(mask); \ + __result; \ }) -#define ARMExpandImm_C(imm12, c) \ + +#define Rotation(val5) \ ({ \ GArchOperand *__result; \ - uint32_t __val; \ - if (armv7_arm_expand_imm_c(imm12, (bool []) { c }, &__val)) \ - __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __val); \ - else \ - __result = NULL; \ + uint8_t __rot; \ + GArchOperand *__rot_op; \ + __rot = val5; \ + __rot_op = g_imm_operand_new_from_value(MDS_8_BITS_UNSIGNED, __rot); \ + __result = g_armv7_rotation_operand_new(__rot_op); \ + if (__result == NULL) \ + g_object_unref(G_OBJECT(__rot_op)); \ __result; \ }) -#define ARMExpandImm(imm12) \ + +#define ThumbExpandImm(imm12) \ ({ \ GArchOperand *__result; \ uint32_t __val; \ - if (armv7_arm_expand_imm(imm12, &__val)) \ + if (armv7_thumb_expand_imm(imm12, &__val)) \ __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __val); \ else \ __result = NULL; \ __result; \ }) + #define ThumbExpandImm_C(imm12, c) \ ({ \ GArchOperand *__result; \ @@ -275,166 +295,98 @@ __result; \ }) -#define ThumbExpandImm(imm12) \ + +#define UInt(val) \ ({ \ GArchOperand *__result; \ - uint32_t __val; \ - if (armv7_thumb_expand_imm(imm12, &__val)) \ - __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __val); \ - else \ - __result = NULL; \ + __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, val); \ __result; \ }) - - - - - -#define DecodeImmShiftValue(imm5) \ - ({ \ - GArchOperand *__result; \ - uint32_t __shift_n; \ - if (!armv7_decode_imm_shift(0, imm5, (SRType []) { 0 }, &__shift_n)) \ - __result = NULL; \ - else \ - __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __shift_n); \ - __result; \ +#define UIntInc(sat4) \ + ({ \ + GArchOperand *__result; \ + uint8_t __val; \ + __val = sat4; \ + __result = g_imm_operand_new_from_value(MDS_8_BITS_UNSIGNED, __val); \ + __result; \ }) -#if 0 -// DecodeRegShift() -// ================ -SRType DecodeRegShift(bits(2) type) -case type of -when '00' shift_t = SRType_LSL; -when '01' shift_t = SRType_LSR; -when '10' shift_t = SRType_ASR; -when '11' shift_t = SRType_ROR; -return shift_t; -#endif - - - -#define ZeroExtend(x, i) \ - ({ \ - MemoryDataSize __mds; \ - uint ## i ## _t __val; \ - __mds = MDS_ ## i ## _BITS_UNSIGNED; \ - __val = armv7_zero_extend(x, 0/**/, i); \ - g_imm_operand_new_from_value(__mds, __val); \ +#define Zeros(i) \ + ({ \ + GArchOperand *__result; \ + MemoryDataSize __mds; \ + uint ## i ## _t __val; \ + __mds = MDS_ ## i ## _BITS_UNSIGNED; \ + __val = 0; \ + __result = g_imm_operand_new_from_value(__mds, __val); \ + __result; \ }) - -#define Zeros(i) \ - ({ \ - MemoryDataSize __mds; \ - uint ## i ## _t __val; \ - __mds = MDS_ ## i ## _BITS_UNSIGNED; \ - __val = 0; \ - g_imm_operand_new_from_value(__mds, __val); \ +#define ZeroExtend(x, i) \ + ({ \ + GArchOperand *__result; \ + MemoryDataSize __mds; \ + uint ## i ## _t __val; \ + __mds = MDS_ ## i ## _BITS_UNSIGNED; \ + __val = armv7_zero_extend(x, -1, i); \ + __result = g_imm_operand_new_from_value(__mds, __val); \ + __result; \ }) - - - - - - /** - * Glue purement interne. + * Définitions complémentaires. */ -#define MakeAccessOffset(add, off) \ - g_armv7_offset_operand_new(add, off) - - -#define MakeShiftedMemoryAccess(base, off, shift, wr) \ - g_armv7_maccess_operand_new(base, off, shift, wr) +#define APSR_C 0 -#define _MakeMemoryAccess(base, off, wr) \ - MakeShiftedMemoryAccess(base, off, NULL, wr) - -/* -#define MakeMemoryAccess(base, off, add, wr) \ - ({ \ - GArchOperand *__off; \ - __off = MakeAccessOffset(add, off); \ - _MakeMemoryAccess(base, __off, wr); \ - }) -*/ - -#define MakeMemoryNotIndexed(base, wr) \ - _MakeMemoryAccess(base, NULL, wr) - - - - - - - - -// type == '10', pas 2 ! (FIXME) -#define FixedShift(type, imm5) \ - ({ \ - GArchOperand *__result; \ - uint32_t __shift_n; \ - __shift_n = imm5; \ - __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __shift_n); \ - __result; \ - }) +/** + * Petite glue vers le format ARM générique... + */ +#define g_armv7_instruction_extend_keyword(ins, ext) \ + g_arm_instruction_extend_keyword(G_ARM_INSTRUCTION(ins), ext) /** - * Glue purement interne pour les listes de registres. + * Vieilleries à conserver au cas où... */ -#define RegistersList(mask) \ - ({ \ - GArchOperand *__result; \ - __result = g_armv7_reglist_operand_new(); \ - if (!g_armv7_reglist_load_registers(G_ARMV7_REGLIST_OPERAND(__result), mask)) \ - { \ - g_object_unref(G_OBJECT(__result)); \ - __result = NULL; \ - } \ - __result; \ - }) - - -#define ListFromRegister(regop) \ - ({ \ - GArchOperand *__result; \ - GArmV7Register *__reg; \ - __result = g_armv7_reglist_operand_new(); \ - __reg = G_ARMV7_REGISTER(regop); \ - g_armv7_reglist_add_register(G_ARMV7_REGLIST_OPERAND(__result), __reg); \ - __result; \ - }) +#if 0 +#include "cregister.h" +#include "operands/limitation.h" -/* Effectue une rotation vers la droit d'une valeur. */ -GArchOperand *ror_armv7_imm(uint32_t, unsigned int); +#define BarrierLimitation(opt) \ + ({ \ + GArchOperand *__result; \ + __result = g_armv7_limitation_operand_new(opt); \ + __result; \ + }) -/* Crée un opérande de valeur immédiate avec extension de signe. */ -GArchOperand *sign_extend_armv7_imm(uint32_t, bool, unsigned int); -/* Etend une valeur immédiate en mode 'Thumb' ARMv7. */ -GArchOperand *thumb_expand_armv7_imm(uint32_t); +#define CRegister(idx) \ + ({ \ + GArchOperand *__result; \ + GArmV7CRegister *__reg; \ + __reg = g_armv7_cregister_new(idx); \ + if (__reg == NULL) \ + __result = NULL; \ + else \ + __result = g_register_operand_new(G_ARCH_REGISTER(__reg)); \ + __result; \ -/* Réalise un simple transtypage de valeur entière. */ -GArchOperand *zero_extend_armv7_imm(uint32_t, unsigned int); +#endif diff --git a/plugins/arm/v7/opcodes/Makefile.am b/plugins/arm/v7/opcodes/Makefile.am index a169c2b..ddaabb7 100644 --- a/plugins/arm/v7/opcodes/Makefile.am +++ b/plugins/arm/v7/opcodes/Makefile.am @@ -23,4 +23,7 @@ AM_CPPFLAGS = $(LIBGTK_CFLAGS) $(LIBXML_CFLAGS) AM_CFLAGS = $(DEBUG_CFLAGS) $(WARNING_FLAGS) $(COMPLIANCE_FLAGS) -I$(top_srcdir)/src +CLEANFILES = $(GENERATED_FILES) + + EXTRA_DIST = opcodes_tmp_arm.h opcodes_tmp_simd.h opcodes_tmp_thumb_16.h opcodes_tmp_thumb_32.h diff --git a/plugins/arm/v7/opdefs/Makefile.am b/plugins/arm/v7/opdefs/Makefile.am index 3f69a3f..0538359 100644 --- a/plugins/arm/v7/opdefs/Makefile.am +++ b/plugins/arm/v7/opdefs/Makefile.am @@ -1,60 +1,48 @@ -include ../../../../tools/d2c/d2c.mk +include $(top_srcdir)/tools/d2c/d2c.mk -D2C_BIN = ../../../../tools/d2c/d2c -GEN_BIN = ../../../../tools/d2c/d2c_genmakefile.sh +D2C_BIN = $(top_srcdir)/tools/d2c/d2c +GEN_BIN = $(top_srcdir)/tools/d2c/d2c_genmakefile.sh -D2C_TYPE = raw -D2C_OUTDIR = $(PWD)/.. +D2C_OUTDIR = $(PWD)/../opcodes/ + +D2C_TYPE = raw -D2C_ARCH = armv7 -D2C_HEADER = _ARCH_ARM_V7 +D2C_ARCH = ARMv7 +D2C_ARCH_CN = ARMv7 +D2C_GUARD = PLUGINS_ARM_V7_OPCODES D2C_ENCODINGS = \ - -e A=arm_ \ - -e t=thumb_16_ \ - -e T=thumb_32_ + -e A=arm \ + -e t=thumb_16 \ + -e T=thumb_32 + +D2C_ID_PREFIX = AOP7 +D2C_ID_COUNT = 500 -D2C_MACROS = \ - -M SetFlags=g_armv7_instruction_define_setflags \ - -M Condition=g_arm_instruction_set_cond \ - -M "ExpandImmC32=g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, " \ - -M SignExtend=sign_extend_armv7_imm \ - -M SetInsFlag=g_arch_instruction_set_flag \ - -M StoreCondition=g_arm_instruction_set_cond \ - -M ExtendKeyword=g_arm_instruction_extend_keyword +D2C_SPECIFIC = -D2C_OPERANDS = \ - -n BarrierLimitation \ - -n BitDiff \ - -n IncWidth \ - -n DecodeImmShift \ - -n MakeMemoryAccess \ - -n Register \ - -n RegisterShift \ - -n UInt \ - -n ZeroExtend -FIXED_C_INCLUDES = \ - \n\#include <arch/link.h> \ - \n\#include <common/bconst.h> \ - \n \ - \n\#include \"../helpers.h\" \ - \n\#include \"../instruction.h\" \ - \n\#include \"../fetch.h\" \ - \n\#include \"../link.h\" \ - \n\#include \"../post.h\" \ - \n\#include \"../../instruction.h\" \ - \n\#include \"../../link.h\" \ - \n\n +FIXED_C_INCLUDES = \ + \#include <assert.h> \ + \n \ + \n\#include <arch/link.h> \ + \n\#include <common/bconst.h> \ + \n \ + \n\#include "../helpers.h" \ + \n\#include "../instruction.h" \ + \n\#include "../fetch.h" \ + \n\#include "../link.h" \ + \n\#include "../post.h" \ + \n\#include "../../instruction.h" \ + \n\#include "../../link.h" -FIXED_H_INCLUDES = \ - \n\#include <stdint.h> \ - \n \ - \n\#include <arch/instruction.h> \ - \n\n +FIXED_H_INCLUDES = \ + \#include <stdint.h> \ + \n \ + \n\#include <arch/instruction.h> # for i in $(seq 1 426); do test -f *A88$i.d && (ls *A88$i.d | sed 's/^/\t/' | sed 's/$/\t\t\t\t\t\t\\/') ; done @@ -278,7 +266,6 @@ ARMV7_DEFS = \ wfi_A88425.d \ yield_A88426.d -# subs_B9320.d # make dist procède répertoire par répertoire. Or le répertoire opcodes utilise # le contenu du répertoire opdefs. Il faut donc générer les fichiers nécessaires @@ -295,7 +282,7 @@ dist-hook: all: $(ARMV7_DEFS:.d=.g) fmk.done d2c_final_rules fmk.done: $(ARMV7_DEFS) - $(GEN_BIN) ../opcodes/ ../opdefs/.gen ../../../../tools/d2c/globalgen.mk arm thumb_32 thumb_16 + $(GEN_BIN) $(D2C_OUTDIR) arm thumb_32 thumb_16 touch $@ clean: diff --git a/plugins/arm/v7/opdefs/adc_A881.d b/plugins/arm/v7/opdefs/adc_A881.d index 6bc66e2..5033749 100644 --- a/plugins/arm/v7/opdefs/adc_A881.d +++ b/plugins/arm/v7/opdefs/adc_A881.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,26 +23,55 @@ @title ADC (immediate) -@desc Add with Carry (immediate) adds an immediate value and the Carry flag value to a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 0 + +@desc { + + Add with Carry (immediate) adds an immediate value and the Carry flag value to a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (T1) { @word 1 1 1 1 0 i(1) 0 1 0 1 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - @syntax <reg_D> <reg_N> <imm32> + @syntax { + + @assert { + + S == 0 + + } + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ThumbExpandImm(i:imm3:imm8) - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ThumbExpandImm(i:imm3:imm8) + } + + @asm adc ?reg_D reg_N imm32 } - @rules { + @syntax { + + @assert { + + S == 1 + + } - if (setflags); chk_call ExtendKeyword("s") + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + + @asm adcs ?reg_D reg_N imm32 } @@ -52,21 +81,55 @@ @word cond(4) 0 0 1 0 1 0 1 S(1) Rn(4) Rd(4) imm12(12) - @syntax <reg_D> <reg_N> <imm32> + @syntax { + + @assert { - @conv { + S == 0 - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ARMExpandImm(imm12) + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ARMExpandImm(imm12) + + } + + @asm adc ?reg_D reg_N imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ARMExpandImm(imm12) + + } + + @asm adcs ?reg_D reg_N imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/adc_A882.d b/plugins/arm/v7/opdefs/adc_A882.d index 27ce6ad..77b53df 100644 --- a/plugins/arm/v7/opdefs/adc_A882.d +++ b/plugins/arm/v7/opdefs/adc_A882.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,29 @@ @title ADC (register) -@desc Add with Carry (register) adds a register value, the Carry flag value, and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 1 + +@desc { + + Add with Carry (register) adds a register value, the Carry flag value, and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (t1) { @half 0 1 0 0 0 0 0 1 0 1 Rm(3) Rdn(3) - @syntax "adcs" <reg_DN> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rdn) + reg_N = Register(Rdn) + reg_M = Register(Rm) - reg_DN = Register(Rdn) - reg_M = Register(Rm) + } + + @asm adc ?reg_D reg_N reg_M } @@ -44,22 +55,45 @@ @word 1 1 1 0 1 0 1 1 0 1 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?shift> + @syntax { + + @assert { + + S == 0 + + } - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm3:imm2) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm adc.w ?reg_D reg_N reg_M ?shift } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @asm adcs.w ?reg_D reg_N reg_M ?shift } @@ -69,22 +103,57 @@ @word cond(4) 0 0 0 0 1 0 1 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?shift> + @syntax { - @conv { + @assert { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm5) + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm adc ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm adcs ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/adc_A883.d b/plugins/arm/v7/opdefs/adc_A883.d index a9c56d8..6371445 100644 --- a/plugins/arm/v7/opdefs/adc_A883.d +++ b/plugins/arm/v7/opdefs/adc_A883.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,28 +23,73 @@ @title ADC (register-shifted register) -@desc Add with Carry (register-shifted register) adds a register value, the Carry flag value, and a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result. +@id 2 + +@desc { + + Add with Carry (register-shifted register) adds a register value, the Carry flag value, and a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result. + +} @encoding (A1) { @word cond(4) 0 0 0 0 1 0 1 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <reg_shift> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm adc ?reg_D reg_N reg_M shift - @conv { + @rules { - reg_shift = RegisterShift(type, Rs) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm adcs ?reg_D reg_N reg_M shift + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/add_A8810.d b/plugins/arm/v7/opdefs/add_A8810.d index 2047276..c7f30b4 100644 --- a/plugins/arm/v7/opdefs/add_A8810.d +++ b/plugins/arm/v7/opdefs/add_A8810.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title ADD (SP plus register, Thumb) -@desc This instruction adds an optionally-shifted register value to the SP value, and writes the result to the destination register. +@id 9 + +@desc { + + This instruction adds an optionally-shifted register value to the SP value, and writes the result to the destination register. + +} @encoding (t1) { @half 0 1 0 0 0 1 0 0 DM(1) 1 1 0 1 Rdm(3) - @syntax <reg_DM_1> <SP> <reg_DM_2> + @syntax { + + @conv { - @conv { + reg_D = Register(DM:Rdm) + reg_SP = Register(13) + reg_M = Register(DM:Rdm) - reg_DM_1 = Register(DM:Rdm) - reg_DM_2 = Register(DM:Rdm) - SP = Register(13) + } + + @asm add ?reg_D reg_SP reg_M } @@ -45,12 +55,17 @@ @half 0 1 0 0 0 1 0 0 1 Rm(4) 1 0 1 - @syntax <SP> <reg_M> + @syntax { + + @conv { + + reg_D = Register(13) + reg_SP = Register(13) + reg_M = Register(Rm) - @conv { + } - reg_M = Register(Rm) - SP = Register(13) + @asm add ?reg_D reg_SP reg_M } @@ -60,22 +75,45 @@ @word 1 1 1 0 1 0 1 1 0 0 0 S(1) 1 1 0 1 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - @syntax <reg_D> <SP> <reg_M> <?shift> + @syntax { + + @assert { + + S == 0 - @conv { + } - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm3:imm2) - SP = Register(13) + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm add.w ?reg_D reg_SP reg_M ?shift } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @asm adds.w ?reg_D reg_SP reg_M ?shift } diff --git a/plugins/arm/v7/opdefs/add_A8811.d b/plugins/arm/v7/opdefs/add_A8811.d index 5b6c0d1..e70c33c 100644 --- a/plugins/arm/v7/opdefs/add_A8811.d +++ b/plugins/arm/v7/opdefs/add_A8811.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,28 +23,69 @@ @title ADD (SP plus register, ARM) -@desc This instruction adds an optionally-shifted register value to the SP value, and writes the result to the destination register. +@id 10 + +@desc { + + This instruction adds an optionally-shifted register value to the SP value, and writes the result to the destination register. + +} @encoding (A1) { @word cond(4) 0 0 0 0 1 0 0 S(1) 1 1 0 1 Rd(4) imm5(5) type(2) 0 Rm(4) - @syntax <reg_D> <SP> <reg_M> <?shift> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm add ?reg_D reg_SP reg_M ?shift - @conv { + @rules { - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm5) - SP = Register(13) + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm adds ?reg_D reg_SP reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/add_A884.d b/plugins/arm/v7/opdefs/add_A884.d index 8b624a7..f61d447 100644 --- a/plugins/arm/v7/opdefs/add_A884.d +++ b/plugins/arm/v7/opdefs/add_A884.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title ADD (immediate, Thumb) -@desc This instruction adds an immediate value to a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 3 + +@desc { + + This instruction adds an immediate value to a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (t1) { @half 0 0 0 1 1 1 0 imm3(3) Rn(3) Rd(3) - @syntax "adds" <reg_D> <reg_N> <imm32> + @syntax { + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm3, 32) - @conv { + } - reg_D = Register(Rd) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm3, 32) + @asm add ?reg_D reg_N imm32 } @@ -45,12 +55,17 @@ @half 0 0 1 1 0 Rdn(3) imm8(8) - @syntax "adds" <reg_DN> <imm32> + @syntax { - @conv { + @conv { - reg_DN = Register(Rdn) - imm32 = ZeroExtend(imm8, 32) + reg_D = Register(Rdn) + reg_N = Register(Rdn) + imm32 = ZeroExtend(imm8, 32) + + } + + @asm add ?reg_D reg_N imm32 } @@ -60,21 +75,43 @@ @word 1 1 1 1 0 i(1) 0 1 0 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - @syntax <reg_D> <reg_N> <imm32> + @syntax { + + @assert { + + S == 0 + + } - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ThumbExpandImm(i:imm3:imm8) + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + + @asm add.w ?reg_D reg_N imm32 } - @rules { + @syntax { + + @assert { + + S == 1 + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + + @asm adds.w ?reg_D reg_N imm32 } @@ -84,13 +121,17 @@ @word 1 1 1 1 0 i(1) 1 0 0 0 0 0 Rn(4) 0 imm3(3) Rd(4) imm8(8) - @syntax "addw" <reg_D> <reg_N> <imm32> + @syntax { + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ZeroExtend(i:imm3:imm8, 32) - @conv { + } - reg_D = Register(Rd) - reg_N = Register(Rn) - imm32 = ZeroExtend(i:imm3:imm8, 32) + @asm addw ?reg_D reg_N imm32 } diff --git a/plugins/arm/v7/opdefs/add_A885.d b/plugins/arm/v7/opdefs/add_A885.d index 0f4a919..5bb4e6f 100644 --- a/plugins/arm/v7/opdefs/add_A885.d +++ b/plugins/arm/v7/opdefs/add_A885.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,27 +23,67 @@ @title ADD (immediate, ARM) -@desc This instruction adds an immediate value to a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 4 + +@desc { + + This instruction adds an immediate value to a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (A1) { @word cond(4) 0 0 1 0 1 0 0 S(1) Rn(4) Rd(4) imm12(12) - @syntax <reg_D> <reg_N> <imm32> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ARMExpandImm(imm12) + + } + + @asm add ?reg_D reg_N imm32 - @conv { + @rules { - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ARMExpandImm(imm12) + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ARMExpandImm(imm12) + + } + + @asm adds ?reg_D reg_N imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/add_A886.d b/plugins/arm/v7/opdefs/add_A886.d index e4f9e00..c84259f 100644 --- a/plugins/arm/v7/opdefs/add_A886.d +++ b/plugins/arm/v7/opdefs/add_A886.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title ADD (register, Thumb) -@desc This instruction adds a register value and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 5 + +@desc { + + This instruction adds a register value and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (t1) { @half 0 0 0 1 1 0 0 Rm(3) Rn(3) Rd(3) - @syntax "adds" <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm add ?reg_D reg_N reg_M } @@ -45,12 +55,17 @@ @half 0 1 0 0 0 1 0 0 DN(1) Rm(4) Rdn(3) - @syntax <reg_DN> <reg_M> + @syntax { + + @conv { + + reg_D = Register(DN:Rdn) + reg_N = Register(DN:Rdn) + reg_M = Register(Rm) - @conv { + } - reg_DN = Register(DN:Rdn) - reg_M = Register(Rm) + @asm add ?reg_D reg_N reg_M } @@ -60,22 +75,45 @@ @word 1 1 1 0 1 0 1 1 0 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?shift> + @syntax { + + @assert { + + S == 0 - @conv { + } - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm3:imm2) + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm add.w ?reg_D reg_N reg_M ?shift } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @asm adds.w ?reg_D reg_N reg_M ?shift } diff --git a/plugins/arm/v7/opdefs/add_A887.d b/plugins/arm/v7/opdefs/add_A887.d index 18400a6..400e179 100644 --- a/plugins/arm/v7/opdefs/add_A887.d +++ b/plugins/arm/v7/opdefs/add_A887.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,28 +23,69 @@ @title ADD (register, ARM) -@desc This instruction adds a register value and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 6 + +@desc { + + This instruction adds a register value and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (A1) { @word cond(4) 0 0 0 0 1 0 0 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?shift> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm add ?reg_D reg_N reg_M ?shift - @conv { + @rules { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm5) + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm adds ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/add_A888.d b/plugins/arm/v7/opdefs/add_A888.d index 5549145..0e4757b 100644 --- a/plugins/arm/v7/opdefs/add_A888.d +++ b/plugins/arm/v7/opdefs/add_A888.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,28 +23,73 @@ @title ADD (register-shifted register) -@desc Add (register-shifted register) adds a register value and a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result. +@id 7 + +@desc { + + Add (register-shifted register) adds a register value and a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result. + +} @encoding (A1) { @word cond(4) 0 0 0 0 1 0 0 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <reg_shift> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm add ?reg_D reg_N reg_M shift - @conv { + @rules { - reg_shift = RegisterShift(type, Rs) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm adds ?reg_D reg_N reg_M shift + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/add_A889.d b/plugins/arm/v7/opdefs/add_A889.d index 5fab17c..6c6c572 100644 --- a/plugins/arm/v7/opdefs/add_A889.d +++ b/plugins/arm/v7/opdefs/add_A889.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title ADD (SP plus immediate) -@desc This instruction adds an immediate value to the SP value, and writes the result to the destination register. +@id 8 + +@desc { + + This instruction adds an immediate value to the SP value, and writes the result to the destination register. + +} @encoding (t1) { @half 1 0 1 0 1 Rd(3) imm8(8) - @syntax <reg_D> <SP> <imm32> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_SP = Register(13) + imm32 = ZeroExtend(imm8:'00', 32) - reg_D = Register(Rd) - imm32 = ZeroExtend(imm8:'00', 32) - SP = Register(13) + } + + @asm add ?reg_D reg_SP imm32 } @@ -45,13 +55,17 @@ @half 1 0 1 1 0 0 0 0 0 imm7(7) - @syntax <SP_0> <SP_1> <imm32> + @syntax { + + @conv { + + reg_D = Register(13) + reg_SP = Register(13) + imm32 = ZeroExtend(imm7:'00', 32) - @conv { + } - imm32 = ZeroExtend(imm7:'00', 32) - SP_0 = Register(13) - SP_1 = Register(13) + @asm add ?reg_D reg_SP imm32 } @@ -61,21 +75,43 @@ @word 1 1 1 1 0 i(1) 0 1 0 0 0 S(1) 1 1 0 1 0 imm3(3) Rd(4) imm8(8) - @syntax <reg_D> <SP> <imm32> + @syntax { + + @assert { + + S == 0 - @conv { + } - reg_D = Register(Rd) - setflags = (S == '1') - imm32 = ThumbExpandImm(i:imm3:imm8) - SP = Register(13) + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + + @asm add.w ?reg_D reg_SP imm32 } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @asm adds.w ?reg_D reg_SP imm32 } @@ -85,13 +121,17 @@ @word 1 1 1 1 0 i(1) 1 0 0 0 0 0 1 1 0 1 0 imm3(3) Rd(4) imm8(8) - @syntax "addw" <reg_D> <SP> <imm32> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - imm32 = ZeroExtend(i:imm3:imm8, 32) - SP = Register(13) + reg_D = Register(Rd) + reg_SP = Register(13) + imm32 = ZeroExtend(i:imm3:imm8, 32) + + } + + @asm addw ?reg_D reg_SP imm32 } @@ -101,21 +141,55 @@ @word cond(4) 0 0 1 0 1 0 0 S(1) 1 1 0 1 Rd(4) imm12(12) - @syntax <reg_D> <SP> <imm32> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + imm32 = ARMExpandImm(imm12) + + } + + @asm add ?reg_D reg_SP imm32 + + @rules { - @conv { + check g_arm_instruction_set_cond(cond) - reg_D = Register(Rd) - setflags = (S == '1') - imm32 = ARMExpandImm(imm12) - SP = Register(13) + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + imm32 = ARMExpandImm(imm12) + + } + + @asm adds ?reg_D reg_SP imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/adr_A8812.d b/plugins/arm/v7/opdefs/adr_A8812.d index 16615cb..ee5ed75 100644 --- a/plugins/arm/v7/opdefs/adr_A8812.d +++ b/plugins/arm/v7/opdefs/adr_A8812.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title ADR -@desc This instruction adds an immediate value to the PC value to form a PC-relative address, and writes the result to the destination register. +@id 11 + +@desc { + + This instruction adds an immediate value to the PC value to form a PC-relative address, and writes the result to the destination register. + +} @encoding (t1) { @half 1 0 1 0 0 Rd(3) imm8(8) - @syntax <reg_D> <imm32> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - imm32 = ZeroExtend(imm8:'00', 32) + reg_D = Register(Rd) + imm32 = ZeroExtend(imm8:'00', 32) + + } + + @asm adr reg_D imm32 } @@ -44,12 +54,16 @@ @word 1 1 1 1 0 i(1) 1 0 1 0 1 0 1 1 1 1 0 imm3(3) Rd(4) imm8(8) - @syntax ".W" <reg_D> <imm32> + @syntax { + + @conv { + + reg_D = Register(Rd) + imm32 = ZeroExtend(i:imm3:imm8, 32) - @conv { + } - reg_D = Register(Rd) - imm32 = ZeroExtend(i:imm3:imm8, 32) + @asm adr.w reg_D imm32 } @@ -59,12 +73,16 @@ @word 1 1 1 1 0 i(1) 1 0 0 0 0 0 1 1 1 1 0 imm3(3) Rd(4) imm8(8) - @syntax ".W" <reg_D> <imm32> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - imm32 = ZeroExtend(i:imm3:imm8, 32) + reg_D = Register(Rd) + imm32 = ZeroExtend(i:imm3:imm8, 32) + + } + + @asm adr.w reg_D imm32 } @@ -74,18 +92,22 @@ @word cond(4) 0 0 1 0 1 0 0 0 1 1 1 1 Rd(4) imm12(12) - @syntax <reg_D> <imm32> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - imm32 = ARMExpandImm(imm12) + reg_D = Register(Rd) + imm32 = ARMExpandImm(imm12) - } + } + + @asm adr reg_D imm32 - @rules { + @rules { - chk_call StoreCondition(cond) + check g_arm_instruction_set_cond(cond) + + } } @@ -95,18 +117,22 @@ @word cond(4) 0 0 1 0 0 1 0 0 1 1 1 1 Rd(4) imm12(12) - @syntax <reg_D> <imm32> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - imm32 = ARMExpandImm(imm12) + reg_D = Register(Rd) + imm32 = ARMExpandImm(imm12) - } + } + + @asm adr reg_D imm32 + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/and_A8813.d b/plugins/arm/v7/opdefs/and_A8813.d index 3e1d0ed..0e303f2 100644 --- a/plugins/arm/v7/opdefs/and_A8813.d +++ b/plugins/arm/v7/opdefs/and_A8813.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,26 +23,55 @@ @title AND (immediate) -@desc This instruction performs a bitwise AND of a register value and an immediate value, and writes the result to the destination register. +@id 12 + +@desc { + + This instruction performs a bitwise AND of a register value and an immediate value, and writes the result to the destination register. + +} @encoding (T1) { @word 1 1 1 1 0 i(1) 0 0 0 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - @syntax <reg_D> <reg_N> <imm32> + @syntax { + + @assert { + + S == 0 + + } + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ThumbExpandImm_C(i:imm3:imm8, 0) + } + + @asm and ?reg_D reg_N const } - @rules { + @syntax { + + @assert { + + S == 1 + + } - if (setflags); chk_call ExtendKeyword("s") + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) + + } + + @asm ands ?reg_D reg_N const } @@ -52,21 +81,55 @@ @word cond(4) 0 0 1 0 0 0 0 S(1) Rn(4) Rd(4) imm12(12) - @syntax <reg_D> <reg_N> <imm32> + @syntax { + + @assert { - @conv { + S == 0 - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ARMExpandImm_C(imm12, 0) + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ARMExpandImm_C(imm12, APSR_C) + + } + + @asm and ?reg_D reg_N const + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ARMExpandImm_C(imm12, APSR_C) + + } + + @asm ands ?reg_D reg_N const + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/and_A8814.d b/plugins/arm/v7/opdefs/and_A8814.d index 77f7e55..94ea843 100644 --- a/plugins/arm/v7/opdefs/and_A8814.d +++ b/plugins/arm/v7/opdefs/and_A8814.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,29 @@ @title AND (register) -@desc This instruction performs a bitwise AND of a register value and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 13 + +@desc { + + This instruction performs a bitwise AND of a register value and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (t1) { @half 0 1 0 0 0 0 0 0 0 0 Rm(3) Rdn(3) - @syntax "ands" <reg_DN> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rdn) + reg_N = Register(Rdn) + reg_M = Register(Rm) - reg_DN = Register(Rdn) - reg_M = Register(Rm) + } + + @asm and ?reg_D reg_N reg_M } @@ -44,22 +55,45 @@ @word 1 1 1 0 1 0 1 0 0 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?shift> + @syntax { + + @assert { + + S == 0 + + } - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm3:imm2) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm and.w ?reg_D reg_N reg_M ?shift } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @asm ands.w ?reg_D reg_N reg_M ?shift } @@ -69,22 +103,57 @@ @word cond(4) 0 0 0 0 0 0 0 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?shift> + @syntax { - @conv { + @assert { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm5) + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm and ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm ands ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/and_A8815.d b/plugins/arm/v7/opdefs/and_A8815.d index 5ace3fa..ca44183 100644 --- a/plugins/arm/v7/opdefs/and_A8815.d +++ b/plugins/arm/v7/opdefs/and_A8815.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,28 +23,73 @@ @title AND (register-shifted register) -@desc This instruction performs a bitwise AND of a register value and a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result. +@id 14 + +@desc { + + This instruction performs a bitwise AND of a register value and a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result. + +} @encoding (A1) { @word cond(4) 0 0 0 0 0 0 0 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <reg_shift> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm and ?reg_D reg_N reg_M shift - @conv { + @rules { - reg_shift = RegisterShift(type, Rs) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm ands ?reg_D reg_N reg_M shift + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/asr_A8816.d b/plugins/arm/v7/opdefs/asr_A8816.d index 006a26c..87d4b3e 100644 --- a/plugins/arm/v7/opdefs/asr_A8816.d +++ b/plugins/arm/v7/opdefs/asr_A8816.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title ASR (immediate) -@desc Arithmetic Shift Right (immediate) shifts a register value right by an immediate number of bits, shifting in copies of its sign bit, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 15 + +@desc { + + Arithmetic Shift Right (immediate) shifts a register value right by an immediate number of bits, shifting in copies of its sign bit, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (t1) { @half 0 0 0 1 0 imm5(5) Rm(3) Rd(3) - @syntax "asrs" <reg_D> <reg_M> <shift_imm> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('10', imm5) - reg_D = Register(Rd) - reg_M = Register(Rm) - shift_imm = DecodeImmShift('10', imm5) + } + + @asm asr ?reg_D reg_M shift_n } @@ -45,21 +55,43 @@ @word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm2(2) 1 0 Rm(4) - @syntax <reg_D> <reg_M> <shift_imm> + @syntax { + + @assert { + + S == 0 + + } - @conv { + @conv { - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - shift_imm = DecodeImmShift('10', imm3:imm2) + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('10', imm3:imm2) + + } + + @asm asr.w ?reg_D reg_M shift_n } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('10', imm3:imm2) + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @asm asrs.w ?reg_D reg_M shift_n } @@ -69,21 +101,55 @@ @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) imm5(5) 1 0 0 Rm(4) - @syntax <reg_D> <reg_M> <shift_imm> + @syntax { - @conv { + @assert { - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - shift_imm = DecodeImmShift('10', imm5) + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('10', imm5) + + } + + @asm asr ?reg_D reg_M shift_n + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('10', imm5) + + } + + @asm asrs ?reg_D reg_M shift_n + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/asr_A8817.d b/plugins/arm/v7/opdefs/asr_A8817.d index 1e1e9c1..6d5b5ef 100644 --- a/plugins/arm/v7/opdefs/asr_A8817.d +++ b/plugins/arm/v7/opdefs/asr_A8817.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,29 @@ @title ASR (register) -@desc Arithmetic Shift Right (register) shifts a register value right by a variable number of bits, shifting in copies of its sign bit, and writes the result to the destination register. The variable number of bits is read from the bottom byte of a register. It can optionally update the condition flags based on the result. +@id 16 + +@desc { + + Arithmetic Shift Right (register) shifts a register value right by a variable number of bits, shifting in copies of its sign bit, and writes the result to the destination register. The variable number of bits is read from the bottom byte of a register. It can optionally update the condition flags based on the result. + +} @encoding (t1) { @half 0 1 0 0 0 0 0 1 0 0 Rm(3) Rdn(3) - @syntax "asrs" <reg_DN> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rdn) + reg_N = Register(Rdn) + reg_M = Register(Rm) - reg_DN = Register(Rdn) - reg_M = Register(Rm) + } + + @asm asr ?reg_D reg_N reg_M } @@ -44,21 +55,43 @@ @word 1 1 1 1 1 0 1 0 0 1 0 S(1) Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @assert { + + S == 0 + + } - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm asr.w ?reg_D reg_N reg_M } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @asm asrs.w ?reg_D reg_N reg_M } @@ -68,21 +101,55 @@ @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) Rm(4) 0 1 0 1 Rn(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @assert { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm asr ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm asrs ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/b_A8818.d b/plugins/arm/v7/opdefs/b_A8818.d index 9e27753..abd542f 100644 --- a/plugins/arm/v7/opdefs/b_A8818.d +++ b/plugins/arm/v7/opdefs/b_A8818.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,23 +23,33 @@ @title B -@desc Branch causes a branch to a target address. +@id 17 + +@desc { + + Branch causes a branch to a target address. + +} @encoding (t1) { @half 1 1 0 1 cond(4) imm8(8) - @syntax <imm32> + @syntax { - @conv { + @conv { - imm32 = SignExtend(imm8:'0', imm8 & 0x80, 32) + imm32 = SignExtend(imm8:'0', 32, 8) - } + } - @rules { + @asm b imm32 - chk_call StoreCondition(cond) + @rules { + + check g_arm_instruction_set_cond(cond) + + } } @@ -57,11 +67,15 @@ @half 1 1 1 0 0 imm11(11) - @syntax <imm32> + @syntax { + + @conv { + + imm32 = SignExtend(imm11:'0', 32, 11) - @conv { + } - imm32 = SignExtend(imm11:'0', imm11 & 0x400, 32) + @asm b imm32 } @@ -79,17 +93,22 @@ @word 1 1 1 1 0 S(1) cond(4) imm6(6) 1 0 J1(1) 0 J2(1) imm11(11) - @syntax ".W" <imm32> + @syntax { - @conv { + @conv { - imm32 = SignExtend(S:J2:J1:imm6:imm11:'0', S & 0x1, 32) + imm32 = SignExtend(S:J2:J1:imm6:imm11:'0', 32, 20) - } + } + + @asm b imm32 - @rules { + @rules { - chk_call StoreCondition(cond) + check g_arm_instruction_set_cond(cond) + check g_armv7_instruction_extend_keyword(".W") + + } } @@ -107,13 +126,15 @@ @word 1 1 1 1 0 S(1) imm10(10) 1 0 J1(1) 1 J2(1) imm11(11) - @syntax ".W" <imm32> + @syntax { + + @conv { - @conv { + imm32 = SignExtend(S:J2:J1:imm10:imm11:'0', 32, 24) - I1 = NOT(J1 EOR S) - I2 = NOT(J2 EOR S) - imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', S & 0x1, 32) + } + + @asm b.w imm32 } @@ -131,17 +152,21 @@ @word cond(4) 1 0 1 0 imm24(24) - @syntax <imm32> + @syntax { - @conv { + @conv { - imm32 = SignExtend(imm24:'00', imm24 & 0x800000, 32) + imm32 = SignExtend(imm24:'00', 32, 25) - } + } + + @asm b imm32 + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/bfc_A8819.d b/plugins/arm/v7/opdefs/bfc_A8819.d index 0ee99c8..bb0e448 100644 --- a/plugins/arm/v7/opdefs/bfc_A8819.d +++ b/plugins/arm/v7/opdefs/bfc_A8819.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title BFC -@desc Bit Field Clear clears any number of adjacent bits at any position in a register, without affecting the other bits in the register. +@id 18 + +@desc { + + Bit Field Clear clears any number of adjacent bits at any position in a register, without affecting the other bits in the register. + +} @encoding (T1) { @word 1 1 1 1 0 0 1 1 0 1 1 0 1 1 1 1 0 imm3(3) Rd(4) imm2(2) 0 msb(5) - @syntax <reg_D> <lsbit> <width> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + lsbit = UInt(imm3:imm2) + msbit = UInt(msb) + width = BitDiff(msbit, lsbit) - reg_D = Register(Rd) - msbit = UInt(msb) - lsbit = UInt(imm3:imm2) - width = BitDiff(msbit, lsbit) + } + + @asm bfc reg_D lsbit width } @@ -46,20 +56,24 @@ @word cond(4) 0 1 1 1 1 1 0 msb(5) Rd(4) lsb(5) 0 0 1 1 1 1 1 - @syntax <reg_D> <lsbit> <width> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - msbit = UInt(msb) - lsbit = UInt(lsb) - width = BitDiff(msbit, lsbit) + reg_D = Register(Rd) + lsbit = UInt(lsb) + msbit = UInt(msb) + width = BitDiff(msbit, lsbit) - } + } + + @asm bfc reg_D lsbit width + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/bfi_A8820.d b/plugins/arm/v7/opdefs/bfi_A8820.d index 1d2bb2f..ac33950 100644 --- a/plugins/arm/v7/opdefs/bfi_A8820.d +++ b/plugins/arm/v7/opdefs/bfi_A8820.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,21 +23,31 @@ @title BFI -@desc Bit Field Insert copies any number of low order bits from a register into the same number of adjacent bits at any position in the destination register. +@id 19 + +@desc { + + Bit Field Insert copies any number of low order bits from a register into the same number of adjacent bits at any position in the destination register. + +} @encoding (T1) { @word 1 1 1 1 0 0 1 1 0 1 1 0 Rn(4) 0 imm3(3) Rd(4) imm2(2) 0 msb(5) - @syntax <reg_D> <reg_N> <lsbit> <width> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + lsbit = UInt(imm3:imm2) + msbit = UInt(msb) + width = BitDiff(msbit, lsbit) - reg_D = Register(Rd) - reg_N = Register(Rn) - msbit = UInt(msb) - lsbit = UInt(imm3:imm2) - width = BitDiff(msbit, lsbit) + } + + @asm bfi reg_D reg_N lsbit width } @@ -47,21 +57,25 @@ @word cond(4) 0 1 1 1 1 1 0 msb(5) Rd(4) lsb(5) 0 0 1 Rn(4) - @syntax <reg_D> <reg_N> <lsbit> <width> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - msbit = UInt(msb) - lsbit = UInt(lsb) - width = BitDiff(msbit, lsbit) + reg_D = Register(Rd) + reg_N = Register(Rn) + lsbit = UInt(lsb) + msbit = UInt(msb) + width = BitDiff(msbit, lsbit) - } + } + + @asm bfi reg_D reg_N lsbit width + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/bic_A8821.d b/plugins/arm/v7/opdefs/bic_A8821.d index 9171b69..1fa6092 100644 --- a/plugins/arm/v7/opdefs/bic_A8821.d +++ b/plugins/arm/v7/opdefs/bic_A8821.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,26 +23,55 @@ @title BIC (immediate) -@desc Bitwise Bit Clear (immediate) performs a bitwise AND of a register value and the complement of an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 20 + +@desc { + + Bitwise Bit Clear (immediate) performs a bitwise AND of a register value and the complement of an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (T1) { @word 1 1 1 1 0 i(1) 0 0 0 0 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - @syntax <reg_D> <reg_N> <imm32> + @syntax { + + @assert { + + S == 0 + + } + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ThumbExpandImm_C(i:imm3:imm8, 0) + } + + @asm bic ?reg_D reg_N const } - @rules { + @syntax { + + @assert { + + S == 1 + + } - if (setflags); chk_call ExtendKeyword("s") + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) + + } + + @asm bics ?reg_D reg_N const } @@ -52,21 +81,55 @@ @word cond(4) 0 0 1 1 1 1 0 S(1) Rn(4) Rd(4) imm12(12) - @syntax <reg_D> <reg_N> <imm32> + @syntax { + + @assert { - @conv { + S == 0 - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ARMExpandImm_C(imm12, 0) + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ARMExpandImm_C(imm12, APSR_C) + + } + + @asm bic ?reg_D reg_N const + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ARMExpandImm_C(imm12, APSR_C) + + } + + @asm bics ?reg_D reg_N const + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/bic_A8822.d b/plugins/arm/v7/opdefs/bic_A8822.d index 8503460..858adb8 100644 --- a/plugins/arm/v7/opdefs/bic_A8822.d +++ b/plugins/arm/v7/opdefs/bic_A8822.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,29 @@ @title BIC (register) -@desc Bitwise Bit Clear (register) performs a bitwise AND of a register value and the complement of an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 21 + +@desc { + + Bitwise Bit Clear (register) performs a bitwise AND of a register value and the complement of an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (t1) { @half 0 1 0 0 0 0 1 1 1 0 Rm(3) Rdn(3) - @syntax "bics" <reg_DN> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rdn) + reg_N = Register(Rdn) + reg_M = Register(Rm) - reg_DN = Register(Rdn) - reg_M = Register(Rm) + } + + @asm bic ?reg_D reg_N reg_M } @@ -44,22 +55,45 @@ @word 1 1 1 0 1 0 1 0 0 0 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?shift> + @syntax { + + @assert { + + S == 0 + + } - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm3:imm2) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm bic.w ?reg_D reg_N reg_M ?shift } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @asm bics.w ?reg_D reg_N reg_M ?shift } @@ -69,22 +103,57 @@ @word cond(4) 0 0 0 1 1 1 0 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?shift> + @syntax { - @conv { + @assert { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm5) + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm bic ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm bics ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/bic_A8823.d b/plugins/arm/v7/opdefs/bic_A8823.d index e6903db..3058125 100644 --- a/plugins/arm/v7/opdefs/bic_A8823.d +++ b/plugins/arm/v7/opdefs/bic_A8823.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,28 +23,73 @@ @title BIC (register-shifted register) -@desc Bitwise Bit Clear (register-shifted register) performs a bitwise AND of a register value and the complement of a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result. +@id 22 + +@desc { + + Bitwise Bit Clear (register-shifted register) performs a bitwise AND of a register value and the complement of a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result. + +} @encoding (A1) { @word cond(4) 0 0 0 1 1 1 0 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <reg_shift> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm bic ?reg_D reg_N reg_M shift - @conv { + @rules { - reg_shift = RegisterShift(type, Rs) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm bics ?reg_D reg_N reg_M shift + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/bkpt_A8824.d b/plugins/arm/v7/opdefs/bkpt_A8824.d index f0aa13a..bc034e9 100644 --- a/plugins/arm/v7/opdefs/bkpt_A8824.d +++ b/plugins/arm/v7/opdefs/bkpt_A8824.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,17 +23,27 @@ @title BKPT -@desc Breakpoint causes a software breakpoint to occur. Breakpoint is always unconditional, even when inside an IT block. +@id 23 + +@desc { + + Breakpoint causes a software breakpoint to occur. Breakpoint is always unconditional, even when inside an IT block. + +} @encoding (t1) { @half 1 0 1 1 1 1 1 0 imm8(8) - @syntax <imm32> + @syntax { - @conv { + @conv { - imm32 = ZeroExtend(imm8, 32) + imm32 = ZeroExtend(imm8, 32) + + } + + @asm bkpt imm32 } @@ -43,11 +53,15 @@ @word cond(4) 0 0 0 1 0 0 1 0 imm12(12) 0 1 1 1 imm4(4) - @syntax <imm32> + @syntax { + + @conv { + + imm32 = ZeroExtend(imm12:imm4, 32) - @conv { + } - imm32 = ZeroExtend(imm12:imm4, 32) + @asm bkpt imm32 } diff --git a/plugins/arm/v7/opdefs/bl_A8825.d b/plugins/arm/v7/opdefs/bl_A8825.d index da0def4..f584f0b 100644 --- a/plugins/arm/v7/opdefs/bl_A8825.d +++ b/plugins/arm/v7/opdefs/bl_A8825.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,27 @@ @title BL, BLX (immediate) -@desc Branch with Link calls a subroutine at a PC-relative address. Branch with Link and Exchange Instruction Sets (immediate) calls a subroutine at a PC-relative address, and changes instruction set from ARM to Thumb, or from Thumb to ARM. +@id 24 + +@desc { + + Branch with Link calls a subroutine at a PC-relative address. Branch with Link and Exchange Instruction Sets (immediate) calls a subroutine at a PC-relative address, and changes instruction set from ARM to Thumb, or from Thumb to ARM. + +} @encoding (T1) { @word 1 1 1 1 0 S(1) imm10(10) 1 1 J1(1) 1 J2(1) imm11(11) - @syntax <imm32> + @syntax { - @conv { + @conv { - I1 = NOT(J1 EOR S) - I2 = NOT(J2 EOR S) - imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', S & 0x1, 32) + imm32 = SignExtend(S:J2:J1:imm10:imm11:'0', 32, 24) + + } + + @asm bl imm32 } @@ -53,13 +61,15 @@ @word 1 1 1 1 0 S(1) imm10H(10) 1 1 J1(1) 0 J2(1) imm10L(10) H(1) - @syntax "blx" <imm32> + @syntax { + + @conv { - @conv { + imm32 = SignExtend(S:J1:J2:imm10H:imm10L:'00', 32, 24) - I1 = NOT(J1 EOR S) - I2 = NOT(J2 EOR S) - imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', S & 0x1, 32) + } + + @asm blx imm32 } @@ -77,17 +87,21 @@ @word cond(4) 1 0 1 1 imm24(24) - @syntax <imm32> + @syntax { - @conv { + @conv { - imm32 = SignExtend(imm24:'00', imm24 & 0x800000, 32) + imm32 = SignExtend(imm24:'00', 32, 25) - } + } + + @asm bl imm32 - @rules { + @rules { - chk_call StoreCondition(cond) + check g_arm_instruction_set_cond(cond) + + } } @@ -105,11 +119,15 @@ @word 1 1 1 1 1 0 1 H(1) imm24(24) - @syntax "blx" <imm32> + @syntax { + + @conv { + + imm32 = SignExtend(imm24:H:'0', 32, 25) - @conv { + } - imm32 = SignExtend(imm24:H:'0', imm24 & 0x800000, 32) + @asm blx imm32 } diff --git a/plugins/arm/v7/opdefs/blx_A8826.d b/plugins/arm/v7/opdefs/blx_A8826.d index 29719fa..9a856b1 100644 --- a/plugins/arm/v7/opdefs/blx_A8826.d +++ b/plugins/arm/v7/opdefs/blx_A8826.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,17 +23,27 @@ @title BLX (register) -@desc Branch with Link and Exchange (register) calls a subroutine at an address and instruction set specified by a register. +@id 25 + +@desc { + + Branch with Link and Exchange (register) calls a subroutine at an address and instruction set specified by a register. + +} @encoding (t1) { @half 0 1 0 0 0 1 1 1 1 Rm(4) 0 0 0 - @syntax <reg_M> + @syntax { + + @conv { - @conv { + reg_M = Register(Rm) - reg_M = Register(Rm) + } + + @asm blx reg_M } @@ -43,17 +53,21 @@ @word cond(4) 0 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 Rm(4) - @syntax <reg_M> + @syntax { - @conv { + @conv { - reg_M = Register(Rm) + reg_M = Register(Rm) - } + } + + @asm blx reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/bx_A8827.d b/plugins/arm/v7/opdefs/bx_A8827.d index f3681e7..15d6288 100644 --- a/plugins/arm/v7/opdefs/bx_A8827.d +++ b/plugins/arm/v7/opdefs/bx_A8827.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,24 +23,33 @@ @title BX -@desc Branch and Exchange causes a branch to an address and instruction set specified by a register. +@id 26 + +@desc { + + Branch and Exchange causes a branch to an address and instruction set specified by a register. + +} @encoding (t1) { @half 0 1 0 0 0 1 1 1 0 Rm(4) 0 0 0 - @syntax <reg_M> + @syntax { + + @conv { - @conv { + reg_M = Register(Rm) - reg_M = Register(Rm) + } + + @asm bx reg_M } @hooks { fetch = help_fetching_with_instruction_bx_from_thumb - link = handle_armv7_conditional_branch_from_register } @@ -50,24 +59,27 @@ @word cond(4) 0 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 Rm(4) - @syntax <reg_M> + @syntax { - @conv { + @conv { - reg_M = Register(Rm) + reg_M = Register(Rm) - } + } + + @asm bx reg_M - @rules { + @rules { - chk_call StoreCondition(cond) + check g_arm_instruction_set_cond(cond) + + } } @hooks { - fetch = help_fetching_with_instruction_bx_from_arm - link = handle_armv7_conditional_branch_from_register + fetch = help_fetching_with_instruction_bx_from_thumb } diff --git a/plugins/arm/v7/opdefs/bxj_A8828.d b/plugins/arm/v7/opdefs/bxj_A8828.d index efa2de2..0716a31 100644 --- a/plugins/arm/v7/opdefs/bxj_A8828.d +++ b/plugins/arm/v7/opdefs/bxj_A8828.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,17 +23,27 @@ @title BXJ -@desc Branch and Exchange Jazelle attempts to change to Jazelle state. If the attempt fails, it branches to an address and instruction set specified by a register as though it were a BX instruction. In an implementation that includes the Virtualization Extensions, if HSTR.TJDBX is set to 1, execution of a BXJ instruction in a Non-secure mode other than Hyp mode generates a Hyp Trap exception. For more information see Trapping accesses to Jazelle functionality on page B1-1255. +@id 27 + +@desc { + + Branch and Exchange Jazelle attempts to change to Jazelle state. If the attempt fails, it branches to an address and instruction set specified by a register as though it were a BX instruction. In an implementation that includes the Virtualization Extensions, if HSTR.TJDBX is set to 1, execution of a BXJ instruction in a Non-secure mode other than Hyp mode generates a Hyp Trap exception. For more information see Trapping accesses to Jazelle functionality on page B1-1255. + +} @encoding (T1) { @word 1 1 1 1 0 0 1 1 1 1 0 0 Rm(4) 1 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 - @syntax <reg_M> + @syntax { + + @conv { - @conv { + reg_M = Register(Rm) - reg_M = Register(Rm) + } + + @asm bxj reg_M } @@ -43,17 +53,21 @@ @word cond(4) 0 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 Rm(4) - @syntax <reg_M> + @syntax { - @conv { + @conv { - reg_M = Register(Rm) + reg_M = Register(Rm) - } + } + + @asm bxj reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/cb_A8829.d b/plugins/arm/v7/opdefs/cb_A8829.d index 134e0f4..3ac923a 100644 --- a/plugins/arm/v7/opdefs/cb_A8829.d +++ b/plugins/arm/v7/opdefs/cb_A8829.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,26 +23,53 @@ @title CBNZ, CBZ -@desc Compare and Branch on Nonzero and Compare and Branch on Zero compare the value in a register with zero, and conditionally branch forward a constant value. They do not affect the condition flags. +@id 28 + +@desc { + + Compare and Branch on Nonzero and Compare and Branch on Zero compare the value in a register with zero, and conditionally branch forward a constant value. They do not affect the condition flags. + +} @encoding (t1) { @half 1 0 1 1 op(1) 0 i(1) 1 imm5(5) Rn(3) - @syntax <reg_N> <imm32> + @syntax { + + @assert { + + op == 0 + + } + + @conv { - @conv { + reg_N = Register(Rn) + imm32 = ZeroExtend(i:imm5:'0', 32) - reg_N = Register(Rn) - imm32 = ZeroExtend(i:imm5:'0', 32) - nonzero = (op == '1') + } + + @asm cbz reg_N imm32 } - @rules { + @syntax { + + @assert { + + op == 1 + + } + + @conv { + + reg_N = Register(Rn) + imm32 = ZeroExtend(i:imm5:'0', 32) + + } - if (nonzero); chk_call ExtendKeyword("n") - chk_call ExtendKeyword("z") + @asm cbnz reg_N imm32 } diff --git a/plugins/arm/v7/opdefs/cdp_A8830.d b/plugins/arm/v7/opdefs/cdp_A8830.d index 109b89b..6d2148d 100644 --- a/plugins/arm/v7/opdefs/cdp_A8830.d +++ b/plugins/arm/v7/opdefs/cdp_A8830.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,22 +23,32 @@ @title CDP, CDP2 -@desc Coprocessor Data Processing tells a coprocessor to perform an operation that is independent of ARM core registers and memory. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the opc1, opc2, CRd, CRn, and CRm fields. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid CDP and CDP2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. +@id 29 + +@desc { + + Coprocessor Data Processing tells a coprocessor to perform an operation that is independent of ARM core registers and memory. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the opc1, opc2, CRd, CRn, and CRm fields. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid CDP and CDP2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. + +} @encoding (T1) { @word 1 1 1 0 1 1 1 0 opc1(4) CRn(4) CRd(4) coproc(4) opc2(3) 0 CRm(4) - @syntax <cp> <undef_opc1> <creg_D> <creg_N> <creg_M> <undef_opc2> + @syntax { - @conv { + @conv { - cp = CoProcessor(coproc) - undef_opc1 = RawValue(opc1) - creg_D = CRegister(CRd) - creg_N = CRegister(CRn) - creg_M = CRegister(CRm) - undef_opc2 = RawValue(opc2) + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + direct_CRd = UInt(CRd) + direct_CRn = UInt(CRn) + direct_CRm = UInt(CRm) + direct_opc2 = UInt(opc2) + + } + + @asm cdp cp direct_opc1 direct_CRd direct_CRn direct_CRm ?direct_opc2 } @@ -46,24 +56,22 @@ @encoding (A1) { - @word cond(4) 1 1 1 0 opc1(4) CRn(4) CRd(4) coproc(4) opc2(3) 0 CRm(4) - - @syntax <cp> <undef_opc1> <creg_D> <creg_N> <creg_M> <undef_opc2> + @word 1 1 1 0 1 1 1 0 opc1(4) CRn(4) CRd(4) coproc(4) opc2(3) 0 CRm(4) - @conv { + @syntax { - cp = CoProcessor(coproc) - undef_opc1 = RawValue(opc1) - creg_D = CRegister(CRd) - creg_N = CRegister(CRn) - creg_M = CRegister(CRm) - undef_opc2 = RawValue(opc2) + @conv { - } + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + direct_CRd = UInt(CRd) + direct_CRn = UInt(CRn) + direct_CRm = UInt(CRm) + direct_opc2 = UInt(opc2) - @rules { + } - chk_call StoreCondition(cond) + @asm cdp cp direct_opc1 direct_CRd direct_CRn direct_CRm ?direct_opc2 } @@ -73,16 +81,20 @@ @word 1 1 1 1 1 1 1 0 opc1(4) CRn(4) CRd(4) coproc(4) opc2(3) 0 CRm(4) - @syntax "cdp2" <cp> <undef_opc1> <creg_D> <creg_N> <creg_M> <undef_opc2> + @syntax { + + @conv { - @conv { + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + direct_CRd = UInt(CRd) + direct_CRn = UInt(CRn) + direct_CRm = UInt(CRm) + direct_opc2 = UInt(opc2) - cp = CoProcessor(coproc) - undef_opc1 = RawValue(opc1) - creg_D = CRegister(CRd) - creg_N = CRegister(CRn) - creg_M = CRegister(CRm) - undef_opc2 = RawValue(opc2) + } + + @asm cdp cp direct_opc1 direct_CRd direct_CRn direct_CRm ?direct_opc2 } @@ -92,16 +104,20 @@ @word 1 1 1 1 1 1 1 0 opc1(4) CRn(4) CRd(4) coproc(4) opc2(3) 0 CRm(4) - @syntax "cdp2" <cp> <undef_opc1> <creg_D> <creg_N> <creg_M> <undef_opc2> + @syntax { + + @conv { + + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + direct_CRd = UInt(CRd) + direct_CRn = UInt(CRn) + direct_CRm = UInt(CRm) + direct_opc2 = UInt(opc2) - @conv { + } - cp = CoProcessor(coproc) - undef_opc1 = RawValue(opc1) - creg_D = CRegister(CRd) - creg_N = CRegister(CRn) - creg_M = CRegister(CRm) - undef_opc2 = RawValue(opc2) + @asm cdp cp direct_opc1 direct_CRd direct_CRn direct_CRm ?direct_opc2 } diff --git a/plugins/arm/v7/opdefs/clrex_A8832.d b/plugins/arm/v7/opdefs/clrex_A8832.d index 4f313f2..38dbca2 100644 --- a/plugins/arm/v7/opdefs/clrex_A8832.d +++ b/plugins/arm/v7/opdefs/clrex_A8832.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,17 +23,35 @@ @title CLREX -@desc Clear-Exclusive clears the local record of the executing processor that an address has had a request for an exclusive access. +@id 31 + +@desc { + + Clear-Exclusive clears the local record of the executing processor that an address has had a request for an exclusive access. + +} @encoding (T1) { @word 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 1 0 1 1 1 1 + @syntax { + + @asm clrex + + } + } @encoding (A1) { @word 1 1 1 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 + @syntax { + + @asm clrex + + } + } diff --git a/plugins/arm/v7/opdefs/clz_A8833.d b/plugins/arm/v7/opdefs/clz_A8833.d index d4fdac6..079e36d 100644 --- a/plugins/arm/v7/opdefs/clz_A8833.d +++ b/plugins/arm/v7/opdefs/clz_A8833.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title CLZ -@desc Count Leading Zeros returns the number of binary zero bits before the first binary one bit in a value. +@id 32 + +@desc { + + Count Leading Zeros returns the number of binary zero bits before the first binary one bit in a value. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 1 1 Rm(4) 1 1 1 1 Rd(4) 1 0 0 0 Rm(4) - @syntax <reg_D> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_M = Register(Rm) + } + + @asm clz reg_D reg_M } @@ -44,18 +54,22 @@ @word cond(4) 0 0 0 1 0 1 1 0 1 1 1 1 Rd(4) 1 1 1 1 0 0 0 1 Rm(4) - @syntax <reg_D> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_M = Register(Rm) - } + } + + @asm clz reg_D reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/cmn_A8834.d b/plugins/arm/v7/opdefs/cmn_A8834.d index fc0b19f..dbf0977 100644 --- a/plugins/arm/v7/opdefs/cmn_A8834.d +++ b/plugins/arm/v7/opdefs/cmn_A8834.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title CMN (immediate) -@desc Compare Negative (immediate) adds a register value and an immediate value. It updates the condition flags based on the result, and discards the result. +@id 33 + +@desc { + + Compare Negative (immediate) adds a register value and an immediate value. It updates the condition flags based on the result, and discards the result. + +} @encoding (T1) { @word 1 1 1 1 0 i(1) 0 1 0 0 0 1 Rn(4) 0 imm3(3) 1 1 1 1 imm8(8) - @syntax <reg_N> <imm32> + @syntax { + + @conv { - @conv { + reg_N = Register(Rn) + imm32 = ThumbExpandImm(i:imm3:imm8) - reg_N = Register(Rn) - imm32 = ThumbExpandImm(i:imm3:imm8) + } + + @asm cmn reg_N imm32 } @@ -44,18 +54,22 @@ @word cond(4) 0 0 1 1 0 1 1 1 Rn(4) 0 0 0 0 imm12(12) - @syntax <reg_N> <imm32> + @syntax { - @conv { + @conv { - reg_N = Register(Rn) - imm32 = ARMExpandImm(imm12) + reg_N = Register(Rn) + imm32 = ARMExpandImm(imm12) - } + } + + @asm cmn reg_N imm32 + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/cmn_A8835.d b/plugins/arm/v7/opdefs/cmn_A8835.d index cd228de..deeef21 100644 --- a/plugins/arm/v7/opdefs/cmn_A8835.d +++ b/plugins/arm/v7/opdefs/cmn_A8835.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title CMN (register) -@desc Compare Negative (register) adds a register value and an optionally-shifted register value. It updates the condition flags based on the result, and discards the result. +@id 34 + +@desc { + + Compare Negative (register) adds a register value and an optionally-shifted register value. It updates the condition flags based on the result, and discards the result. + +} @encoding (t1) { @half 0 1 0 0 0 0 1 0 1 1 Rm(3) Rn(3) - @syntax <reg_N> <reg_M> + @syntax { + + @conv { + + reg_N = Register(Rn) + reg_M = Register(Rm) - @conv { + } - reg_N = Register(Rn) - reg_M = Register(Rm) + @asm cmn reg_N reg_M } @@ -44,13 +54,17 @@ @word 1 1 1 0 1 0 1 1 0 0 0 1 Rn(4) 0 imm3(3) 1 1 1 1 imm2(2) type(2) Rm(4) - @syntax ".W" <reg_N> <reg_M> <?shift> + @syntax { - @conv { + @conv { - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm cmn.w reg_N reg_M ?shift } @@ -60,19 +74,23 @@ @word cond(4) 0 0 0 1 0 1 1 1 Rn(4) 0 0 0 0 imm5(5) type(2) 0 Rm(4) - @syntax <reg_N> <reg_M> <?shift> + @syntax { - @conv { + @conv { - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) - } + } + + @asm cmn reg_N reg_M ?shift + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/cmn_A8836.d b/plugins/arm/v7/opdefs/cmn_A8836.d index ad58482..44d414d 100644 --- a/plugins/arm/v7/opdefs/cmn_A8836.d +++ b/plugins/arm/v7/opdefs/cmn_A8836.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,25 +23,37 @@ @title CMN (register-shifted register) -@desc Compare Negative (register-shifted register) adds a register value and a register-shifted register value. It updates the condition flags based on the result, and discards the result. +@id 35 + +@desc { + + Compare Negative (register-shifted register) adds a register value and a register-shifted register value. It updates the condition flags based on the result, and discards the result. + +} @encoding (A1) { @word cond(4) 0 0 0 1 0 1 1 1 Rn(4) 0 0 0 0 Rs(4) 0 type(2) 1 Rm(4) - @syntax <reg_N> <reg_M> <reg_shift> + @syntax { - @conv { + @conv { - reg_shift = RegisterShift(type, Rs) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) - } + } + + @asm cmn reg_N reg_M shift + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/cmp_A8837.d b/plugins/arm/v7/opdefs/cmp_A8837.d index 76b7a76..bd35c57 100644 --- a/plugins/arm/v7/opdefs/cmp_A8837.d +++ b/plugins/arm/v7/opdefs/cmp_A8837.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title CMP (immediate) -@desc Compare (immediate) subtracts an immediate value from a register value. It updates the condition flags based on the result, and discards the result. +@id 36 + +@desc { + + Compare (immediate) subtracts an immediate value from a register value. It updates the condition flags based on the result, and discards the result. + +} @encoding (t1) { @half 0 0 1 0 1 Rn(3) imm8(8) - @syntax <reg_N> <imm32> + @syntax { + + @conv { + + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) - @conv { + } - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) + @asm cmp reg_N imm32 } @@ -44,12 +54,16 @@ @word 1 1 1 1 0 i(1) 0 1 1 0 1 1 Rn(4) 0 imm3(3) 1 1 1 1 imm8(8) - @syntax ".W" <reg_N> <imm32> + @syntax { - @conv { + @conv { - reg_N = Register(Rn) - imm32 = ThumbExpandImm(i:imm3:imm8) + reg_N = Register(Rn) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + + @asm cmp.w reg_N imm32 } @@ -59,18 +73,22 @@ @word cond(4) 0 0 1 1 0 1 0 1 Rn(4) 0 0 0 0 imm12(12) - @syntax <reg_N> <imm32> + @syntax { - @conv { + @conv { - reg_N = Register(Rn) - imm32 = ARMExpandImm(imm12) + reg_N = Register(Rn) + imm32 = ARMExpandImm(imm12) - } + } + + @asm cmp reg_N imm32 + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/cmp_A8838.d b/plugins/arm/v7/opdefs/cmp_A8838.d index cd02543..4c1bf73 100644 --- a/plugins/arm/v7/opdefs/cmp_A8838.d +++ b/plugins/arm/v7/opdefs/cmp_A8838.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title CMP (register) -@desc Compare (register) subtracts an optionally-shifted register value from a register value. It updates the condition flags based on the result, and discards the result. +@id 37 + +@desc { + + Compare (register) subtracts an optionally-shifted register value from a register value. It updates the condition flags based on the result, and discards the result. + +} @encoding (t1) { @half 0 1 0 0 0 0 1 0 1 0 Rm(3) Rn(3) - @syntax <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm cmp reg_N reg_M } @@ -44,12 +54,16 @@ @half 0 1 0 0 0 1 0 1 N(1) Rm(4) Rn(3) - @syntax <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_N = Register(N:Rn) + reg_M = Register(Rm) - reg_N = Register(N:Rn) - reg_M = Register(Rm) + } + + @asm cmp reg_N reg_M } @@ -59,13 +73,17 @@ @word 1 1 1 0 1 0 1 1 1 0 1 1 Rn(4) 0 imm3(3) 1 1 1 1 imm2(2) type(2) Rm(4) - @syntax ".W" <reg_N> <reg_M> <?shift> + @syntax { + + @conv { + + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) - @conv { + } - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) + @asm cmp.w reg_N reg_M ?shift } @@ -75,19 +93,23 @@ @word cond(4) 0 0 0 1 0 1 0 1 Rn(4) 0 0 0 0 imm5(5) type(2) 0 Rm(4) - @syntax <reg_N> <reg_M> <?shift> + @syntax { - @conv { + @conv { - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) - } + } + + @asm cmp reg_N reg_M ?shift + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/cmp_A8839.d b/plugins/arm/v7/opdefs/cmp_A8839.d index 45ed0f9..4d8a8cf 100644 --- a/plugins/arm/v7/opdefs/cmp_A8839.d +++ b/plugins/arm/v7/opdefs/cmp_A8839.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,25 +23,37 @@ @title CMP (register-shifted register) -@desc Compare (register-shifted register) subtracts a register-shifted register value from a register value. It updates the condition flags based on the result, and discards the result. +@id 38 + +@desc { + + Compare (register-shifted register) subtracts a register-shifted register value from a register value. It updates the condition flags based on the result, and discards the result. + +} @encoding (A1) { @word cond(4) 0 0 0 1 0 1 0 1 Rn(4) 0 0 0 0 Rs(4) 0 type(2) 1 Rm(4) - @syntax <reg_N> <reg_M> <reg_shift> + @syntax { - @conv { + @conv { - reg_shift = RegisterShift(type, Rs) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) - } + } + + @asm cmp reg_N reg_M shift + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/dbg_A8842.d b/plugins/arm/v7/opdefs/dbg_A8842.d index 62142f5..aa06c16 100644 --- a/plugins/arm/v7/opdefs/dbg_A8842.d +++ b/plugins/arm/v7/opdefs/dbg_A8842.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,17 +23,27 @@ @title DBG -@desc Debug Hint provides a hint to debug and related systems. See their documentation for what use (if any) they make of this instruction. +@id 41 + +@desc { + + Debug Hint provides a hint to debug and related systems. See their documentation for what use (if any) they make of this instruction. + +} @encoding (T1) { @word 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 option(4) - @syntax <undef_option> + @syntax { + + @conv { - @conv { + direct_option = UInt(option) - undef_option = RawValue(option) + } + + @asm dbg direct_option } @@ -43,17 +53,21 @@ @word cond(4) 0 0 1 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 option(4) - @syntax <undef_option> + @syntax { - @conv { + @conv { - undef_option = RawValue(option) + direct_option = UInt(option) - } + } + + @asm dbg direct_option + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/dmb_A8843.d b/plugins/arm/v7/opdefs/dmb_A8843.d index 34f053a..da9abdc 100644 --- a/plugins/arm/v7/opdefs/dmb_A8843.d +++ b/plugins/arm/v7/opdefs/dmb_A8843.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,17 +23,27 @@ @title DMB -@desc Data Memory Barrier is a memory barrier that ensures the ordering of observations of memory accesses, see Data Memory Barrier (DMB) on page A3-151. +@id 42 + +@desc { + + Data Memory Barrier is a memory barrier that ensures the ordering of observations of memory accesses, see Data Memory Barrier (DMB) on page A3-151. + +} @encoding (T1) { @word 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 1 0 1 option(4) - @syntax <limitation> + @syntax { - @conv { + @conv { - limitation = BarrierLimitation(option) + direct_option = UInt(option) + + } + + @asm dmb ?direct_option } @@ -43,11 +53,15 @@ @word 1 1 1 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 1 option(4) - @syntax <limitation> + @syntax { + + @conv { + + direct_option = UInt(option) - @conv { + } - limitation = BarrierLimitation(option) + @asm dmb ?direct_option } diff --git a/plugins/arm/v7/opdefs/dsb_A8844.d b/plugins/arm/v7/opdefs/dsb_A8844.d index 512220c..87925ae 100644 --- a/plugins/arm/v7/opdefs/dsb_A8844.d +++ b/plugins/arm/v7/opdefs/dsb_A8844.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,17 +23,27 @@ @title DSB -@desc Data Synchronization Barrier is a memory barrier that ensures the completion of memory accesses, see Data Synchronization Barrier (DSB) on page A3-152. +@id 43 + +@desc { + + Data Synchronization Barrier is a memory barrier that ensures the completion of memory accesses, see Data Synchronization Barrier (DSB) on page A3-152. + +} @encoding (T1) { @word 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 1 0 0 option(4) - @syntax <limitation> + @syntax { - @conv { + @conv { - limitation = BarrierLimitation(option) + direct_option = UInt(option) + + } + + @asm dsb ?direct_option } @@ -43,11 +53,15 @@ @word 1 1 1 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 option(4) - @syntax <limitation> + @syntax { + + @conv { + + direct_option = UInt(option) - @conv { + } - limitation = BarrierLimitation(option) + @asm dsb ?direct_option } diff --git a/plugins/arm/v7/opdefs/eor_A8846.d b/plugins/arm/v7/opdefs/eor_A8846.d index 38dc858..3dc39cc 100644 --- a/plugins/arm/v7/opdefs/eor_A8846.d +++ b/plugins/arm/v7/opdefs/eor_A8846.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,26 +23,55 @@ @title EOR (immediate) -@desc Bitwise Exclusive OR (immediate) performs a bitwise Exclusive OR of a register value and an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 45 + +@desc { + + Bitwise Exclusive OR (immediate) performs a bitwise Exclusive OR of a register value and an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (T1) { @word 1 1 1 1 0 i(1) 0 0 1 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - @syntax <reg_D> <reg_N> <imm32> + @syntax { + + @assert { + + S == 0 + + } + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ThumbExpandImm_C(i:imm3:imm8, 0) + } + + @asm eor ?reg_D reg_N const } - @rules { + @syntax { + + @assert { + + S == 1 + + } - if (setflags); chk_call ExtendKeyword("s") + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) + + } + + @asm eors ?reg_D reg_N const } @@ -52,21 +81,55 @@ @word cond(4) 0 0 1 0 0 0 1 S(1) Rn(4) Rd(4) imm12(12) - @syntax <reg_D> <reg_N> <imm32> + @syntax { + + @assert { - @conv { + S == 0 - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ARMExpandImm_C(imm12, 0) + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ARMExpandImm_C(imm12, APSR_C) + + } + + @asm eor ?reg_D reg_N const + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ARMExpandImm_C(imm12, APSR_C) + + } + + @asm eors ?reg_D reg_N const + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/eor_A8847.d b/plugins/arm/v7/opdefs/eor_A8847.d index 66643a1..4746ef8 100644 --- a/plugins/arm/v7/opdefs/eor_A8847.d +++ b/plugins/arm/v7/opdefs/eor_A8847.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,29 @@ @title EOR (register) -@desc Bitwise Exclusive OR (register) performs a bitwise Exclusive OR of a register value and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 46 + +@desc { + + Bitwise Exclusive OR (register) performs a bitwise Exclusive OR of a register value and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (t1) { @half 0 1 0 0 0 0 0 0 0 1 Rm(3) Rdn(3) - @syntax "eors" <reg_DN> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rdn) + reg_N = Register(Rdn) + reg_M = Register(Rm) - reg_DN = Register(Rdn) - reg_M = Register(Rm) + } + + @asm eor ?reg_D reg_N reg_M } @@ -44,22 +55,45 @@ @word 1 1 1 0 1 0 1 0 1 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?shift> + @syntax { + + @assert { + + S == 0 + + } - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm3:imm2) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm eor.w ?reg_D reg_N reg_M ?shift } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @asm eors.w ?reg_D reg_N reg_M ?shift } @@ -69,22 +103,57 @@ @word cond(4) 0 0 0 0 0 0 1 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?shift> + @syntax { - @conv { + @assert { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm5) + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm eor ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm eors ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/eor_A8848.d b/plugins/arm/v7/opdefs/eor_A8848.d index f38fa74..1248e43 100644 --- a/plugins/arm/v7/opdefs/eor_A8848.d +++ b/plugins/arm/v7/opdefs/eor_A8848.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,28 +23,73 @@ @title EOR (register-shifted register) -@desc Bitwise Exclusive OR (register-shifted register) performs a bitwise Exclusive OR of a register value and a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result. +@id 47 + +@desc { + + Bitwise Exclusive OR (register-shifted register) performs a bitwise Exclusive OR of a register value and a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result. + +} @encoding (A1) { @word cond(4) 0 0 0 0 0 0 1 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <reg_shift> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm eor ?reg_D reg_N reg_M shift - @conv { + @rules { - reg_shift = RegisterShift(type, Rs) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm eors ?reg_D reg_N reg_M shift + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldr_A8862.d b/plugins/arm/v7/opdefs/ldr_A8862.d index 03df506..5672fe3 100644 --- a/plugins/arm/v7/opdefs/ldr_A8862.d +++ b/plugins/arm/v7/opdefs/ldr_A8862.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title LDR (immediate, Thumb) -@desc Load Register (immediate) calculates an address from a base register value and an immediate offset, loads a word from memory, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. +@id 61 + +@desc { + + Load Register (immediate) calculates an address from a base register value and an immediate offset, loads a word from memory, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (t1) { @half 0 1 1 0 1 imm5(5) Rn(3) Rt(3) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm5:'00', 32) + maccess = MemAccessOffset(reg_N, imm32) - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm5:'00', 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + } + + @asm ldr reg_T maccess } @@ -46,14 +56,18 @@ @half 1 0 0 1 1 Rt(3) imm8(8) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(13) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessOffset(reg_N, imm32) - reg_T = Register(Rt) - imm32 = ZeroExtend(imm8:'00', 32) - SP = Register(13) - mem_access = MakeMemoryAccess(SP, imm32, NULL, true, true, false) + } + + @asm ldr reg_T maccess } @@ -63,14 +77,18 @@ @word 1 1 1 1 1 0 0 0 1 1 0 1 Rn(4) Rt(4) imm12(12) - @syntax ".W" <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessOffset(reg_N, imm32) - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + } + + @asm ldr.w reg_T maccess } @@ -80,17 +98,69 @@ @word 1 1 1 1 1 0 0 0 0 1 0 1 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) - @syntax <reg_T> <mem_access> + @syntax { + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldr reg_T maccess + + } + + @syntax { + + @assert { + + P == 1 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm ldr reg_T maccess + + } + + @syntax { + + @assert { + + P == 0 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - index = (P == '1') - add = (U == '1') - wback = (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + @asm ldr reg_T maccess } diff --git a/plugins/arm/v7/opdefs/ldr_A8863.d b/plugins/arm/v7/opdefs/ldr_A8863.d index 0d0ce1f..3e1b255 100644 --- a/plugins/arm/v7/opdefs/ldr_A8863.d +++ b/plugins/arm/v7/opdefs/ldr_A8863.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,29 +23,99 @@ @title LDR (immediate, ARM) -@desc Load Register (immediate) calculates an address from a base register value and an immediate offset, loads a word from memory, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. +@id 62 + +@desc { + + Load Register (immediate) calculates an address from a base register value and an immediate offset, loads a word from memory, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (A1) { @word cond(4) 0 1 0 P(1) U(1) 0 W(1) 1 Rn(4) Rt(4) imm12(12) - @syntax <reg_T> <mem_access> + @syntax { + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldr reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { - @conv { + @assert { - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm ldr reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm ldr reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldr_A8864.d b/plugins/arm/v7/opdefs/ldr_A8864.d index 74afa2d..7c78df5 100644 --- a/plugins/arm/v7/opdefs/ldr_A8864.d +++ b/plugins/arm/v7/opdefs/ldr_A8864.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title LDR (literal) -@desc Load Register (literal) calculates an address from the PC value and an immediate offset, loads a word from memory, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. +@id 63 + +@desc { + + Load Register (literal) calculates an address from the PC value and an immediate offset, loads a word from memory, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (t1) { @half 0 1 0 0 1 Rt(3) imm8(8) - @syntax <reg_T> <imm32> + @syntax { + + @conv { + + reg_T = Register(Rt) + imm32 = ZeroExtend(imm8:'00', 32) - @conv { + } - reg_T = Register(Rt) - imm32 = ZeroExtend(imm8:'00', 32) + @asm ldr reg_T imm32 } @@ -51,12 +61,16 @@ @word 1 1 1 1 1 0 0 0 U(1) 1 0 1 1 1 1 1 Rt(4) imm12(12) - @syntax ".W" <reg_T> <imm32> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - imm32 = ZeroExtend(imm12, 32) + reg_T = Register(Rt) + imm32 = ZeroExtend(imm12, 32) + + } + + @asm ldr.w reg_T imm32 } @@ -73,18 +87,22 @@ @word cond(4) 0 1 0 1 U(1) 0 0 1 1 1 1 1 Rt(4) imm12(12) - @syntax <reg_T> <imm32> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - imm32 = ZeroExtend(imm12, 32) + reg_T = Register(Rt) + imm32 = ZeroExtend(imm12, 32) - } + } + + @asm ldr reg_T imm32 + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldr_A8865.d b/plugins/arm/v7/opdefs/ldr_A8865.d index ebb4e09..e94eccb 100644 --- a/plugins/arm/v7/opdefs/ldr_A8865.d +++ b/plugins/arm/v7/opdefs/ldr_A8865.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title LDR (register, Thumb) -@desc Load Register (register) calculates an address from a base register value and an offset register value, loads a word from memory, and writes it to a register. The offset register value can optionally be shifted. For information about memory accesses, see Memory accesses on page A8-294. The Thumb form of LDR (register) does not support register writeback. +@id 64 + +@desc { + + Load Register (register) calculates an address from a base register value and an offset register value, loads a word from memory, and writes it to a register. The offset register value can optionally be shifted. For information about memory accesses, see Memory accesses on page A8-294. The Thumb form of LDR (register) does not support register writeback. + +} @encoding (t1) { @half 0 1 0 1 1 0 0 Rm(3) Rn(3) Rt(3) - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, true, false, false) + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessOffset(reg_N, reg_M) + + } + + @asm ldr reg_T maccess } @@ -46,15 +56,19 @@ @word 1 1 1 1 1 0 0 0 0 1 0 1 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) - @syntax ".W" <reg_T> <mem_access> + @syntax { + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = FixedShift(SRType_LSL, imm2) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(0, imm2) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, true, false, false) + @asm ldr.w reg_T maccess } diff --git a/plugins/arm/v7/opdefs/ldr_A8866.d b/plugins/arm/v7/opdefs/ldr_A8866.d index b161043..6ba19f7 100644 --- a/plugins/arm/v7/opdefs/ldr_A8866.d +++ b/plugins/arm/v7/opdefs/ldr_A8866.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,30 +23,102 @@ @title LDR (register, ARM) -@desc Load Register (register) calculates an address from a base register value and an offset register value, loads a word from memory, and writes it to a register. The offset register value can optionally be shifted. For information about memory accesses, see Memory accesses on page A8-294. +@id 65 + +@desc { + + Load Register (register) calculates an address from a base register value and an offset register value, loads a word from memory, and writes it to a register. The offset register value can optionally be shifted. For information about memory accesses, see Memory accesses on page A8-294. + +} @encoding (A1) { @word cond(4) 0 1 1 P(1) U(1) 0 W(1) 1 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) - @syntax <reg_T> <mem_access> + @syntax { + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) + + } + + @asm ldr reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { - @conv { + @assert { - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - shift = DecodeImmShift(type, imm5) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, index, add, wback) + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessPreIndexedExtended(reg_N, reg_M, shift) + + } + + @asm ldr reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessPostIndexedExtended(reg_N, reg_M, shift) + + } + + @asm ldr reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldrb_A8867.d b/plugins/arm/v7/opdefs/ldrb_A8867.d index 2dea64e..cbfa097 100644 --- a/plugins/arm/v7/opdefs/ldrb_A8867.d +++ b/plugins/arm/v7/opdefs/ldrb_A8867.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title LDRB (immediate, Thumb) -@desc Load Register Byte (immediate) calculates an address from a base register value and an immediate offset, loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. +@id 66 + +@desc { + + Load Register Byte (immediate) calculates an address from a base register value and an immediate offset, loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (t1) { @half 0 1 1 1 1 imm5(5) Rn(3) Rt(3) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm5, 32) + maccess = MemAccessOffset(reg_N, imm32) - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm5, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + } + + @asm ldrb reg_T maccess } @@ -46,14 +56,18 @@ @word 1 1 1 1 1 0 0 0 1 0 0 1 Rn(4) Rt(4) imm12(12) - @syntax ".W" <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessOffset(reg_N, imm32) - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + } + + @asm ldrb.w reg_T maccess } @@ -63,17 +77,69 @@ @word 1 1 1 1 1 0 0 0 0 0 0 1 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) - @syntax <reg_T> <mem_access> + @syntax { + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrb reg_T maccess + + } + + @syntax { + + @assert { + + P == 1 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm ldrb reg_T maccess + + } + + @syntax { + + @assert { + + P == 0 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - index = (P == '1') - add = (U == '1') - wback = (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + @asm ldrb reg_T maccess } diff --git a/plugins/arm/v7/opdefs/ldrb_A8868.d b/plugins/arm/v7/opdefs/ldrb_A8868.d index 519c309..71c6c43 100644 --- a/plugins/arm/v7/opdefs/ldrb_A8868.d +++ b/plugins/arm/v7/opdefs/ldrb_A8868.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,29 +23,99 @@ @title LDRB (immediate, ARM) -@desc Load Register Byte (immediate) calculates an address from a base register value and an immediate offset, loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. +@id 67 + +@desc { + + Load Register Byte (immediate) calculates an address from a base register value and an immediate offset, loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (A1) { @word cond(4) 0 1 0 P(1) U(1) 1 W(1) 1 Rn(4) Rt(4) imm12(12) - @syntax <reg_T> <mem_access> + @syntax { + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { - @conv { + @assert { - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm ldrb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm ldrb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldrb_A8869.d b/plugins/arm/v7/opdefs/ldrb_A8869.d index fb80049..37abb30 100644 --- a/plugins/arm/v7/opdefs/ldrb_A8869.d +++ b/plugins/arm/v7/opdefs/ldrb_A8869.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title LDRB (literal) -@desc Load Register Byte (literal) calculates an address from the PC value and an immediate offset, loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. +@id 68 + +@desc { + + Load Register Byte (literal) calculates an address from the PC value and an immediate offset, loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (T1) { @word 1 1 1 1 1 0 0 0 U(1) 0 0 1 1 1 1 1 Rt(4) imm12(12) - @syntax <reg_T> <imm32> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + imm32 = ZeroExtend(imm12, 32) - reg_T = Register(Rt) - imm32 = ZeroExtend(imm12, 32) + } + + @asm ldrb reg_T imm32 } @@ -44,18 +54,22 @@ @word cond(4) 0 1 0 1 U(1) 1 0 1 1 1 1 1 Rt(4) imm12(12) - @syntax <reg_T> <imm32> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - imm32 = ZeroExtend(imm12, 32) + reg_T = Register(Rt) + imm32 = ZeroExtend(imm12, 32) - } + } + + @asm ldrb reg_T imm32 + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldrb_A8870.d b/plugins/arm/v7/opdefs/ldrb_A8870.d index 35f95ab..3324549 100644 --- a/plugins/arm/v7/opdefs/ldrb_A8870.d +++ b/plugins/arm/v7/opdefs/ldrb_A8870.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title LDRB (register) -@desc Load Register Byte (register) calculates an address from a base register value and an offset register value, loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. The offset register value can optionally be shifted. For information about memory accesses see Memory accesses on page A8-294. +@id 69 + +@desc { + + Load Register Byte (register) calculates an address from a base register value and an offset register value, loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. The offset register value can optionally be shifted. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (t1) { @half 0 1 0 1 1 1 0 Rm(3) Rn(3) Rt(3) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessOffset(reg_N, reg_M) - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, true, true, false) + } + + @asm ldrb reg_T maccess } @@ -46,15 +56,19 @@ @word 1 1 1 1 1 0 0 0 0 0 0 1 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) - @syntax ".W" <reg_T> <mem_access> + @syntax { + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = FixedShift(SRType_LSL, imm2) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(0, imm2) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, true, true, false) + @asm ldrb.w reg_T maccess } @@ -64,24 +78,90 @@ @word cond(4) 0 1 1 P(1) U(1) 1 W(1) 1 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) - @syntax <reg_T> <mem_access> + @syntax { + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) + + } + + @asm ldrb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @assert { + + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessPreIndexedExtended(reg_N, reg_M, shift) + + } + + @asm ldrb reg_T maccess + + @rules { - @conv { + check g_arm_instruction_set_cond(cond) - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - shift = DecodeImmShift(type, imm5) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, index, add, wback) + } } - @rules { + @syntax { + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessPostIndexedExtended(reg_N, reg_M, shift) + + } + + @asm ldrb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldrbt_A8871.d b/plugins/arm/v7/opdefs/ldrbt_A8871.d index 0bf9c3c..f0d91fd 100644 --- a/plugins/arm/v7/opdefs/ldrbt_A8871.d +++ b/plugins/arm/v7/opdefs/ldrbt_A8871.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title LDRBT -@desc Load Register Byte Unprivileged loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. LDRBT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or an optionally-shifted register value. +@id 70 + +@desc { + + Load Register Byte Unprivileged loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. LDRBT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or an optionally-shifted register value. + +} @encoding (T1) { @word 1 1 1 1 1 0 0 0 0 0 0 1 Rn(4) Rt(4) 1 1 1 0 imm8(8) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + @asm ldrbt reg_T maccess } @@ -46,21 +56,24 @@ @word cond(4) 0 1 0 0 U(1) 1 1 1 Rn(4) Rt(4) imm12(12) - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_N = Register(Rn) - add = (U == '1') - imm32 = ZeroExtend(imm12, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, false, add, false) + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) - } + } + + @asm ldrbt reg_T maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } @@ -70,22 +83,25 @@ @word cond(4) 0 1 1 0 U(1) 1 1 1 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - add = (U == '1') - shift = DecodeImmShift(type, imm5) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, false, add, false) + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessPostIndexedExtended(reg_N, reg_M, shift) - } + } + + @asm ldrbt reg_T maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldrd_A8872.d b/plugins/arm/v7/opdefs/ldrd_A8872.d index c73fdca..2b95b6d 100644 --- a/plugins/arm/v7/opdefs/ldrd_A8872.d +++ b/plugins/arm/v7/opdefs/ldrd_A8872.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,24 +23,84 @@ @title LDRD (immediate) -@desc Load Register Dual (immediate) calculates an address from a base register value and an immediate offset, loads two words from memory, and writes them to two registers. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. +@id 71 + +@desc { + + Load Register Dual (immediate) calculates an address from a base register value and an immediate offset, loads two words from memory, and writes them to two registers. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (T1) { @word 1 1 1 0 1 0 0 P(1) U(1) 1 W(1) 1 Rn(4) Rt(4) Rt2(4) imm8(8) - @syntax <reg_T> <reg_T2> <mem_access> + @syntax { + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrd reg_T reg_T2 maccess + + } + + @syntax { + + @assert { - @conv { + P == 1 + W == 1 - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8:'00', 32) - index = (P == '1') - add = (U == '1') - wback = (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm ldrd reg_T reg_T2 maccess + + } + + @syntax { + + @assert { + + P == 0 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm ldrd reg_T reg_T2 maccess } @@ -50,24 +110,90 @@ @word cond(4) 0 0 0 P(1) U(1) 1 W(1) 0 Rn(4) Rt(4) imm4H(4) 1 1 0 1 imm4L(4) - @syntax <reg_T> <reg_T2> <mem_access> + @syntax { + + @assert { - @conv { + P == 1 + P == 1 && W == 0 - reg_T = Register(Rt) - reg_T2 = NextRegister(reg_T) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm4H:imm4L, 32) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = NextRegister(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrd reg_T reg_T2 maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = NextRegister(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm ldrd reg_T reg_T2 maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = NextRegister(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm ldrd reg_T reg_T2 maccess + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldrd_A8873.d b/plugins/arm/v7/opdefs/ldrd_A8873.d index 828e4a3..fd64c78 100644 --- a/plugins/arm/v7/opdefs/ldrd_A8873.d +++ b/plugins/arm/v7/opdefs/ldrd_A8873.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title LDRD (literal) -@desc Load Register Dual (literal) calculates an address from the PC value and an immediate offset, loads two words from memory, and writes them to two registers. For information about memory accesses see Memory accesses on page A8-294. +@id 72 + +@desc { + + Load Register Dual (literal) calculates an address from the PC value and an immediate offset, loads two words from memory, and writes them to two registers. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (T1) { @word 1 1 1 0 1 0 0 P(1) U(1) 1 W(1) 1 1 1 1 1 Rt(4) Rt2(4) imm8(8) - @syntax <reg_T> <reg_T2> <imm32> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + imm32 = ZeroExtend(imm8:'00', 32) - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - imm32 = ZeroExtend(imm8:'00', 32) + } + + @asm ldrd reg_T reg_T2 imm32 } @@ -45,19 +55,23 @@ @word cond(4) 0 0 0 1 U(1) 1 0 0 1 1 1 1 Rt(4) imm4H(4) 1 1 0 1 imm4L(4) - @syntax <reg_T> <reg_T2> <imm32> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_T2 = NextRegister(reg_T) - imm32 = ZeroExtend(imm4H:imm4L, 32) + reg_T = Register(Rt) + reg_T2 = NextRegister(Rt) + imm32 = ZeroExtend(imm4H:imm4L, 32) - } + } + + @asm ldrd reg_T reg_T2 imm32 + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldrd_A8874.d b/plugins/arm/v7/opdefs/ldrd_A8874.d index ed055a6..abf8143 100644 --- a/plugins/arm/v7/opdefs/ldrd_A8874.d +++ b/plugins/arm/v7/opdefs/ldrd_A8874.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,30 +23,102 @@ @title LDRD (register) -@desc Load Register Dual (register) calculates an address from a base register value and a register offset, loads two words from memory, and writes them to two registers. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. +@id 73 + +@desc { + + Load Register Dual (register) calculates an address from a base register value and a register offset, loads two words from memory, and writes them to two registers. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (A1) { @word cond(4) 0 0 0 P(1) U(1) 0 W(1) 0 Rn(4) Rt(4) 0 0 0 0 1 1 0 1 Rm(4) - @syntax <reg_T> <reg_T2> <mem_access> + @syntax { + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = NextRegister(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessOffset(reg_N, reg_M) + + } + + @asm ldrd reg_T reg_T2 maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { - @conv { + @assert { - reg_T = Register(Rt) - reg_T2 = NextRegister(reg_T) - reg_N = Register(Rn) - reg_M = Register(Rm) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, index, add, wback) + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = NextRegister(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPreIndexed(reg_N, reg_M) + + } + + @asm ldrd reg_T reg_T2 maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = NextRegister(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(reg_N, reg_M) + + } + + @asm ldrd reg_T reg_T2 maccess + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldrex_A8875.d b/plugins/arm/v7/opdefs/ldrex_A8875.d index b915061..b30ae86 100644 --- a/plugins/arm/v7/opdefs/ldrex_A8875.d +++ b/plugins/arm/v7/opdefs/ldrex_A8875.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title LDREX -@desc Load Register Exclusive calculates an address from a base register value and an immediate offset, loads a word from memory, writes it to a register and: • if the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing processor in a global monitor • causes the executing processor to indicate an active exclusive access in the local monitor. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. +@id 74 + +@desc { + + Load Register Exclusive calculates an address from a base register value and an immediate offset, loads a word from memory, writes it to a register and: • if the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing processor in a global monitor • causes the executing processor to indicate an active exclusive access in the local monitor. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (T1) { @word 1 1 1 0 1 0 0 0 0 1 0 1 Rn(4) Rt(4) 1 1 1 1 imm8(8) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessOffset(reg_N, imm32) - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8:'00', 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, false, false) + } + + @asm ldrex reg_T maccess } @@ -46,19 +56,24 @@ @word cond(4) 0 0 0 1 1 0 0 1 Rn(4) Rt(4) 1 1 1 1 1 0 0 1 1 1 1 1 - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_N = Register(Rn) - mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = Zeros(32) + maccess = MemAccessOffset(reg_N, imm32) - } + } + + @asm ldrex reg_T maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldrexb_A8876.d b/plugins/arm/v7/opdefs/ldrexb_A8876.d index e398ef2..8827994 100644 --- a/plugins/arm/v7/opdefs/ldrexb_A8876.d +++ b/plugins/arm/v7/opdefs/ldrexb_A8876.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title LDREXB -@desc Load Register Exclusive Byte derives an address from a base register value, loads a byte from memory, zero-extends it to form a 32-bit word, writes it to a register and: • if the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing processor in a global monitor • causes the executing processor to indicate an active exclusive access in the local monitor. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. +@id 75 + +@desc { + + Load Register Exclusive Byte derives an address from a base register value, loads a byte from memory, zero-extends it to form a 32-bit word, writes it to a register and: • if the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing processor in a global monitor • causes the executing processor to indicate an active exclusive access in the local monitor. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (T1) { @word 1 1 1 0 1 0 0 0 1 1 0 1 Rn(4) Rt(4) 1 1 1 1 0 1 0 0 1 1 1 1 - @syntax <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) - reg_T = Register(Rt) - reg_N = Register(Rn) - mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + } + + @asm ldrexb reg_T maccess } @@ -45,19 +55,23 @@ @word cond(4) 0 0 0 1 1 1 0 1 Rn(4) Rt(4) 1 1 1 1 1 0 0 1 1 1 1 1 - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_N = Register(Rn) - mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + reg_T = Register(Rt) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) - } + } + + @asm ldrexb reg_T maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldrexd_A8877.d b/plugins/arm/v7/opdefs/ldrexd_A8877.d index 0188cb7..16f6ea6 100644 --- a/plugins/arm/v7/opdefs/ldrexd_A8877.d +++ b/plugins/arm/v7/opdefs/ldrexd_A8877.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title LDREXD -@desc Load Register Exclusive Doubleword derives an address from a base register value, loads a 64-bit doubleword from memory, writes it to two registers and: • if the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing processor in a global monitor • causes the executing processor to indicate an active exclusive access in the local monitor. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. +@id 76 + +@desc { + + Load Register Exclusive Doubleword derives an address from a base register value, loads a 64-bit doubleword from memory, writes it to two registers and: • if the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing processor in a global monitor • causes the executing processor to indicate an active exclusive access in the local monitor. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (T1) { @word 1 1 1 0 1 0 0 0 1 1 0 1 Rn(4) Rt(4) Rt2(4) 0 1 1 1 1 1 1 1 - @syntax <reg_T> <reg_T2> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - reg_N = Register(Rn) - mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + } + + @asm ldrexd reg_T reg_T2 maccess } @@ -46,20 +56,24 @@ @word cond(4) 0 0 0 1 1 0 1 1 Rn(4) Rt(4) 1 1 1 1 1 0 0 1 1 1 1 1 - @syntax <reg_T> <reg_T2> <mem_access> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_T2 = NextRegister(reg_T) - reg_N = Register(Rn) - mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + reg_T = Register(Rt) + reg_T2 = NextRegister(Rt) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) - } + } + + @asm ldrexd reg_T reg_T2 maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldrexh_A8878.d b/plugins/arm/v7/opdefs/ldrexh_A8878.d index 8e9366f..637a6c9 100644 --- a/plugins/arm/v7/opdefs/ldrexh_A8878.d +++ b/plugins/arm/v7/opdefs/ldrexh_A8878.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title LDREXH -@desc Load Register Exclusive Halfword derives an address from a base register value, loads a halfword from memory, zero-extends it to form a 32-bit word, writes it to a register and: • if the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing processor in a global monitor • causes the executing processor to indicate an active exclusive access in the local monitor. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. +@id 77 + +@desc { + + Load Register Exclusive Halfword derives an address from a base register value, loads a halfword from memory, zero-extends it to form a 32-bit word, writes it to a register and: • if the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing processor in a global monitor • causes the executing processor to indicate an active exclusive access in the local monitor. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (T1) { @word 1 1 1 0 1 0 0 0 1 1 0 1 Rn(4) Rt(4) 1 1 1 1 0 1 0 1 1 1 1 1 - @syntax <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) - reg_T = Register(Rt) - reg_N = Register(Rn) - mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + } + + @asm ldrexh reg_T maccess } @@ -45,19 +55,23 @@ @word cond(4) 0 0 0 1 1 1 1 1 Rn(4) Rt(4) 1 1 1 1 1 0 0 1 1 1 1 1 - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_N = Register(Rn) - mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + reg_T = Register(Rt) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) - } + } + + @asm ldrexh reg_T maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldrh_A8879.d b/plugins/arm/v7/opdefs/ldrh_A8879.d index 3b57bf8..4c21348 100644 --- a/plugins/arm/v7/opdefs/ldrh_A8879.d +++ b/plugins/arm/v7/opdefs/ldrh_A8879.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title LDRH (immediate, Thumb) -@desc Load Register Halfword (immediate) calculates an address from a base register value and an immediate offset, loads a halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. +@id 78 + +@desc { + + Load Register Halfword (immediate) calculates an address from a base register value and an immediate offset, loads a halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (t1) { @half 1 0 0 0 1 imm5(5) Rn(3) Rt(3) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm5:'0', 32) + maccess = MemAccessOffset(reg_N, imm32) - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm5:'0', 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + } + + @asm ldrh reg_T maccess } @@ -46,14 +56,18 @@ @word 1 1 1 1 1 0 0 0 1 0 1 1 Rn(4) Rt(4) imm12(12) - @syntax ".W" <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessOffset(reg_N, imm32) - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + } + + @asm ldrh.w reg_T maccess } @@ -63,17 +77,69 @@ @word 1 1 1 1 1 0 0 0 0 0 1 1 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) - @syntax <reg_T> <mem_access> + @syntax { + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrh reg_T maccess + + } + + @syntax { + + @assert { + + P == 1 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm ldrh reg_T maccess + + } + + @syntax { + + @assert { + + P == 0 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - index = (P == '1') - add = (U == '1') - wback = (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + @asm ldrh reg_T maccess } diff --git a/plugins/arm/v7/opdefs/ldrh_A8880.d b/plugins/arm/v7/opdefs/ldrh_A8880.d index f5f7ab0..17c2bee 100644 --- a/plugins/arm/v7/opdefs/ldrh_A8880.d +++ b/plugins/arm/v7/opdefs/ldrh_A8880.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,29 +23,99 @@ @title LDRH (immediate, ARM) -@desc Load Register Halfword (immediate) calculates an address from a base register value and an immediate offset, loads a halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. +@id 79 + +@desc { + + Load Register Halfword (immediate) calculates an address from a base register value and an immediate offset, loads a halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (A1) { @word cond(4) 0 0 0 P(1) U(1) 1 W(1) 1 Rn(4) Rt(4) imm4H(4) 1 0 1 1 imm4L(4) - @syntax <reg_T> <mem_access> + @syntax { + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { - @conv { + @assert { - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm4H:imm4L, 32) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm ldrh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm ldrh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldrh_A8881.d b/plugins/arm/v7/opdefs/ldrh_A8881.d index 59005e4..3828d51 100644 --- a/plugins/arm/v7/opdefs/ldrh_A8881.d +++ b/plugins/arm/v7/opdefs/ldrh_A8881.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title LDRH (literal) -@desc Load Register Halfword (literal) calculates an address from the PC value and an immediate offset, loads a halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. +@id 80 + +@desc { + + Load Register Halfword (literal) calculates an address from the PC value and an immediate offset, loads a halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (T1) { @word 1 1 1 1 1 0 0 0 U(1) 0 1 1 1 1 1 1 Rt(4) imm12(12) - @syntax <reg_T> <imm32> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + imm32 = ZeroExtend(imm12, 32) - reg_T = Register(Rt) - imm32 = ZeroExtend(imm12, 32) + } + + @asm ldrh reg_T imm32 } @@ -44,18 +54,22 @@ @word cond(4) 0 0 0 P(1) U(1) 1 W(1) 1 1 1 1 1 Rt(4) imm4H(4) 1 0 1 1 imm4L(4) - @syntax <reg_T> <imm32> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - imm32 = ZeroExtend(imm4H:imm4L, 32) + reg_T = Register(Rt) + imm32 = ZeroExtend(imm4H:imm4L, 32) - } + } + + @asm ldrh reg_T imm32 + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldrh_A8882.d b/plugins/arm/v7/opdefs/ldrh_A8882.d index 823bf24..3994a53 100644 --- a/plugins/arm/v7/opdefs/ldrh_A8882.d +++ b/plugins/arm/v7/opdefs/ldrh_A8882.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title LDRH (register) -@desc Load Register Halfword (register) calculates an address from a base register value and an offset register value, loads a halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. The offset register value can be shifted left by 0, 1, 2, or 3 bits. For information about memory accesses see Memory accesses on page A8-294. +@id 81 + +@desc { + + Load Register Halfword (register) calculates an address from a base register value and an offset register value, loads a halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. The offset register value can be shifted left by 0, 1, 2, or 3 bits. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (t1) { @half 0 1 0 1 1 0 1 Rm(3) Rn(3) Rt(3) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessOffset(reg_N, reg_M) - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, true, true, false) + } + + @asm ldrh reg_T maccess } @@ -46,15 +56,19 @@ @word 1 1 1 1 1 0 0 0 0 0 1 1 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) - @syntax ".W" <reg_T> <mem_access> + @syntax { + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = FixedShift(SRType_LSL, imm2) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(0, imm2) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, true, true, false) + @asm ldrh.w reg_T maccess } @@ -64,23 +78,87 @@ @word cond(4) 0 0 0 P(1) U(1) 0 W(1) 1 Rn(4) Rt(4) 0 0 0 0 1 0 1 1 Rm(4) - @syntax <reg_T> <mem_access> + @syntax { + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessOffset(reg_N, reg_M) + + } + + @asm ldrh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @assert { + + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPreIndexed(reg_N, reg_M) + + } + + @asm ldrh reg_T maccess + + @rules { - @conv { + check g_arm_instruction_set_cond(cond) - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, index, add, wback) + } } - @rules { + @syntax { + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(reg_N, reg_M) + + } + + @asm ldrh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldrht_A8883.d b/plugins/arm/v7/opdefs/ldrht_A8883.d index 8f8f015..d096d4e 100644 --- a/plugins/arm/v7/opdefs/ldrht_A8883.d +++ b/plugins/arm/v7/opdefs/ldrht_A8883.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title LDRHT -@desc Load Register Halfword Unprivileged loads a halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. LDRHT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or a register value. +@id 82 + +@desc { + + Load Register Halfword Unprivileged loads a halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. LDRHT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or a register value. + +} @encoding (T1) { @word 1 1 1 1 1 0 0 0 0 0 1 1 Rn(4) Rt(4) 1 1 1 0 imm8(8) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + @asm ldrht reg_T maccess } @@ -46,21 +56,24 @@ @word cond(4) 0 0 0 0 U(1) 1 1 1 Rn(4) Rt(4) imm4H(4) 1 0 1 1 imm4L(4) - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_N = Register(Rn) - add = (U == '1') - imm32 = ZeroExtend(imm4H:imm4L, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, false, add, false) + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) - } + } + + @asm ldrht reg_T maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } @@ -70,21 +83,24 @@ @word cond(4) 0 0 0 0 U(1) 0 1 1 Rn(4) Rt(4) 0 0 0 0 1 0 1 1 Rm(4) - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - add = (U == '1') - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, false, add, false) + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(reg_N, reg_M) - } + } + + @asm ldrht reg_T maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldrsb_A8884.d b/plugins/arm/v7/opdefs/ldrsb_A8884.d index fc41134..05a0372 100644 --- a/plugins/arm/v7/opdefs/ldrsb_A8884.d +++ b/plugins/arm/v7/opdefs/ldrsb_A8884.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title LDRSB (immediate) -@desc Load Register Signed Byte (immediate) calculates an address from a base register value and an immediate offset, loads a byte from memory, sign-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. +@id 83 + +@desc { + + Load Register Signed Byte (immediate) calculates an address from a base register value and an immediate offset, loads a byte from memory, sign-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (T1) { @word 1 1 1 1 1 0 0 1 1 0 0 1 Rn(4) Rt(4) imm12(12) - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrsb reg_T maccess } @@ -46,17 +56,69 @@ @word 1 1 1 1 1 0 0 1 0 0 0 1 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) - @syntax <reg_T> <mem_access> + @syntax { + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrsb reg_T maccess + + } + + @syntax { + + @assert { + + P == 1 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm ldrsb reg_T maccess + + } + + @syntax { + + @assert { + + P == 0 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - index = (P == '1') - add = (U == '1') - wback = (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + @asm ldrsb reg_T maccess } @@ -66,23 +128,87 @@ @word cond(4) 0 0 0 P(1) U(1) 1 W(1) 1 Rn(4) Rt(4) imm4H(4) 1 1 0 1 imm4L(4) - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @assert { - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm4H:imm4L, 32) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrsb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @assert { + + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm ldrsb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm ldrsb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldrsb_A8885.d b/plugins/arm/v7/opdefs/ldrsb_A8885.d index 6cb1d34..46c7b35 100644 --- a/plugins/arm/v7/opdefs/ldrsb_A8885.d +++ b/plugins/arm/v7/opdefs/ldrsb_A8885.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title LDRSB (literal) -@desc Load Register Signed Byte (literal) calculates an address from the PC value and an immediate offset, loads a byte from memory, sign-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. +@id 84 + +@desc { + + Load Register Signed Byte (literal) calculates an address from the PC value and an immediate offset, loads a byte from memory, sign-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (T1) { @word 1 1 1 1 1 0 0 1 U(1) 0 0 1 1 1 1 1 Rt(4) imm12(12) - @syntax <reg_T> <imm32> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + imm32 = ZeroExtend(imm12, 32) - reg_T = Register(Rt) - imm32 = ZeroExtend(imm12, 32) + } + + @asm ldrsb reg_T imm32 } @@ -44,18 +54,22 @@ @word cond(4) 0 0 0 1 U(1) 1 0 1 1 1 1 1 Rt(4) imm4H(4) 1 1 0 1 imm4L(4) - @syntax <reg_T> <imm32> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - imm32 = ZeroExtend(imm4H:imm4L, 32) + reg_T = Register(Rt) + imm32 = ZeroExtend(imm4H:imm4L, 32) - } + } + + @asm ldrsb reg_T imm32 + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldrsb_A8886.d b/plugins/arm/v7/opdefs/ldrsb_A8886.d index 4a66278..e7da94f 100644 --- a/plugins/arm/v7/opdefs/ldrsb_A8886.d +++ b/plugins/arm/v7/opdefs/ldrsb_A8886.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title LDRSB (register) -@desc Load Register Signed Byte (register) calculates an address from a base register value and an offset register value, loads a byte from memory, sign-extends it to form a 32-bit word, and writes it to a register. The offset register value can be shifted left by 0, 1, 2, or 3 bits. For information about memory accesses see Memory accesses on page A8-294. +@id 85 + +@desc { + + Load Register Signed Byte (register) calculates an address from a base register value and an offset register value, loads a byte from memory, sign-extends it to form a 32-bit word, and writes it to a register. The offset register value can be shifted left by 0, 1, 2, or 3 bits. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (t1) { @half 0 1 0 1 0 1 1 Rm(3) Rn(3) Rt(3) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessOffset(reg_N, reg_M) - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, true, true, false) + } + + @asm ldrsb reg_T maccess } @@ -46,15 +56,19 @@ @word 1 1 1 1 1 0 0 1 0 0 0 1 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) - @syntax ".W" <reg_T> <mem_access> + @syntax { + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = FixedShift(SRType_LSL, imm2) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(0, imm2) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, true, true, false) + @asm ldrsb.w reg_T maccess } @@ -64,23 +78,87 @@ @word cond(4) 0 0 0 P(1) U(1) 0 W(1) 1 Rn(4) Rt(4) 0 0 0 0 1 1 0 1 Rm(4) - @syntax <reg_T> <mem_access> + @syntax { + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessOffset(reg_N, reg_M) + + } + + @asm ldrsb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @assert { + + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPreIndexed(reg_N, reg_M) + + } + + @asm ldrsb reg_T maccess + + @rules { - @conv { + check g_arm_instruction_set_cond(cond) - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, index, add, wback) + } } - @rules { + @syntax { + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(reg_N, reg_M) + + } + + @asm ldrsb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldrsbt_A8887.d b/plugins/arm/v7/opdefs/ldrsbt_A8887.d index b545f32..3182168 100644 --- a/plugins/arm/v7/opdefs/ldrsbt_A8887.d +++ b/plugins/arm/v7/opdefs/ldrsbt_A8887.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title LDRSBT -@desc Load Register Signed Byte Unprivileged loads a byte from memory, sign-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. LDRSBT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or a register value. +@id 86 + +@desc { + + Load Register Signed Byte Unprivileged loads a byte from memory, sign-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. LDRSBT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or a register value. + +} @encoding (T1) { @word 1 1 1 1 1 0 0 1 0 0 0 1 Rn(4) Rt(4) 1 1 1 0 imm8(8) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + @asm ldrsbt reg_T maccess } @@ -46,21 +56,24 @@ @word cond(4) 0 0 0 0 U(1) 1 1 1 Rn(4) Rt(4) imm4H(4) 1 1 0 1 imm4L(4) - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_N = Register(Rn) - add = (U == '1') - imm32 = ZeroExtend(imm4H:imm4L, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, false, add, false) + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) - } + } + + @asm ldrsbt reg_T maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } @@ -70,21 +83,24 @@ @word cond(4) 0 0 0 0 U(1) 0 1 1 Rn(4) Rt(4) 0 0 0 0 1 1 0 1 Rm(4) - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - add = (U == '1') - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, false, add, false) + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(reg_N, reg_M) - } + } + + @asm ldrsbt reg_T maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldrsh_A8888.d b/plugins/arm/v7/opdefs/ldrsh_A8888.d index f01024c..a6f62b6 100644 --- a/plugins/arm/v7/opdefs/ldrsh_A8888.d +++ b/plugins/arm/v7/opdefs/ldrsh_A8888.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title LDRSH (immediate) -@desc Load Register Signed Halfword (immediate) calculates an address from a base register value and an immediate offset, loads a halfword from memory, sign-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. +@id 87 + +@desc { + + Load Register Signed Halfword (immediate) calculates an address from a base register value and an immediate offset, loads a halfword from memory, sign-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (T1) { @word 1 1 1 1 1 0 0 1 1 0 1 1 Rn(4) Rt(4) imm12(12) - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrsh reg_T maccess } @@ -46,17 +56,69 @@ @word 1 1 1 1 1 0 0 1 0 0 1 1 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) - @syntax <reg_T> <mem_access> + @syntax { + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrsh reg_T maccess + + } + + @syntax { + + @assert { + + P == 1 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm ldrsh reg_T maccess + + } + + @syntax { + + @assert { + + P == 0 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - index = (P == '1') - add = (U == '1') - wback = (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + @asm ldrsh reg_T maccess } @@ -66,23 +128,87 @@ @word cond(4) 0 0 0 P(1) U(1) 1 W(1) 1 Rn(4) Rt(4) imm4H(4) 1 1 1 1 imm4L(4) - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @assert { - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm4H:imm4L, 32) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrsh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @assert { + + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm ldrsh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm ldrsh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldrsh_A8889.d b/plugins/arm/v7/opdefs/ldrsh_A8889.d index 074cd5c..ae8e458 100644 --- a/plugins/arm/v7/opdefs/ldrsh_A8889.d +++ b/plugins/arm/v7/opdefs/ldrsh_A8889.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title LDRSH (literal) -@desc Load Register Signed Halfword (literal) calculates an address from the PC value and an immediate offset, loads a halfword from memory, sign-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. +@id 88 + +@desc { + + Load Register Signed Halfword (literal) calculates an address from the PC value and an immediate offset, loads a halfword from memory, sign-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (T1) { @word 1 1 1 1 1 0 0 1 U(1) 0 1 1 1 1 1 1 Rt(4) imm12(12) - @syntax <reg_T> <imm32> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + imm32 = ZeroExtend(imm12, 32) - reg_T = Register(Rt) - imm32 = ZeroExtend(imm12, 32) + } + + @asm ldrsh reg_T imm32 } @@ -44,18 +54,22 @@ @word cond(4) 0 0 0 1 U(1) 1 0 1 1 1 1 1 Rt(4) imm4H(4) 1 1 1 1 imm4L(4) - @syntax <reg_T> <imm32> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - imm32 = ZeroExtend(imm4H:imm4L, 32) + reg_T = Register(Rt) + imm32 = ZeroExtend(imm4H:imm4L, 32) - } + } + + @asm ldrsh reg_T imm32 + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldrsh_A8890.d b/plugins/arm/v7/opdefs/ldrsh_A8890.d index eac6c09..6e4feeb 100644 --- a/plugins/arm/v7/opdefs/ldrsh_A8890.d +++ b/plugins/arm/v7/opdefs/ldrsh_A8890.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title LDRSH (register) -@desc Load Register Signed Halfword (register) calculates an address from a base register value and an offset register value, loads a halfword from memory, sign-extends it to form a 32-bit word, and writes it to a register. The offset register value can be shifted left by 0, 1, 2, or 3 bits. For information about memory accesses see Memory accesses on page A8-294. +@id 89 + +@desc { + + Load Register Signed Halfword (register) calculates an address from a base register value and an offset register value, loads a halfword from memory, sign-extends it to form a 32-bit word, and writes it to a register. The offset register value can be shifted left by 0, 1, 2, or 3 bits. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (t1) { @half 0 1 0 1 1 1 1 Rm(3) Rn(3) Rt(3) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessOffset(reg_N, reg_M) - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, true, true, false) + } + + @asm ldrsh reg_T maccess } @@ -46,15 +56,19 @@ @word 1 1 1 1 1 0 0 1 0 0 1 1 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) - @syntax ".W" <reg_T> <mem_access> + @syntax { + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = FixedShift(SRType_LSL, imm2) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(0, imm2) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, true, true, false) + @asm ldrsh.w reg_T maccess } @@ -64,23 +78,87 @@ @word cond(4) 0 0 0 P(1) U(1) 0 W(1) 1 Rn(4) Rt(4) 0 0 0 0 1 1 1 1 Rm(4) - @syntax <reg_T> <mem_access> + @syntax { + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessOffset(reg_N, reg_M) + + } + + @asm ldrsh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @assert { + + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPreIndexed(reg_N, reg_M) + + } + + @asm ldrsh reg_T maccess + + @rules { - @conv { + check g_arm_instruction_set_cond(cond) - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, index, add, wback) + } } - @rules { + @syntax { + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(reg_N, reg_M) + + } + + @asm ldrsh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldrsht_A8891.d b/plugins/arm/v7/opdefs/ldrsht_A8891.d index 355178b..2a00b3a 100644 --- a/plugins/arm/v7/opdefs/ldrsht_A8891.d +++ b/plugins/arm/v7/opdefs/ldrsht_A8891.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title LDRSHT -@desc Load Register Signed Halfword Unprivileged loads a halfword from memory, sign-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. LDRSHT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or a register value. +@id 90 + +@desc { + + Load Register Signed Halfword Unprivileged loads a halfword from memory, sign-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. LDRSHT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or a register value. + +} @encoding (T1) { @word 1 1 1 1 1 0 0 1 0 0 1 1 Rn(4) Rt(4) 1 1 1 0 imm8(8) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + @asm ldrsht reg_T maccess } @@ -46,21 +56,24 @@ @word cond(4) 0 0 0 0 U(1) 1 1 1 Rn(4) Rt(4) imm4H(4) 1 1 1 1 imm4L(4) - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_N = Register(Rn) - add = (U == '1') - imm32 = ZeroExtend(imm4H:imm4L, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, false, add, false) + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) - } + } + + @asm ldrsht reg_T maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } @@ -70,21 +83,24 @@ @word cond(4) 0 0 0 0 U(1) 0 1 1 Rn(4) Rt(4) 0 0 0 0 1 1 1 1 Rm(4) - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - add = (U == '1') - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, false, add, false) + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(reg_N, reg_M) - } + } + + @asm ldrsht reg_T maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldrt_A8892.d b/plugins/arm/v7/opdefs/ldrt_A8892.d index e13f0e7..aa92cad 100644 --- a/plugins/arm/v7/opdefs/ldrt_A8892.d +++ b/plugins/arm/v7/opdefs/ldrt_A8892.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title LDRT -@desc Load Register Unprivileged loads a word from memory, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. LDRT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or an optionally-shifted register value. +@id 91 + +@desc { + + Load Register Unprivileged loads a word from memory, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. LDRT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or an optionally-shifted register value. + +} @encoding (T1) { @word 1 1 1 1 1 0 0 0 0 1 0 1 Rn(4) Rt(4) 1 1 1 0 imm8(8) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + @asm ldrt reg_T maccess } @@ -46,21 +56,24 @@ @word cond(4) 0 1 0 0 U(1) 0 1 1 Rn(4) Rt(4) imm12(12) - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_N = Register(Rn) - add = (U == '1') - imm32 = ZeroExtend(imm12, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, false, add, false) + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) - } + } + + @asm ldrt reg_T maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } @@ -70,22 +83,25 @@ @word cond(4) 0 1 1 0 U(1) 0 1 1 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - add = (U == '1') - shift = DecodeImmShift(type, imm5) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, false, add, false) + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessPostIndexedExtended(reg_N, reg_M, shift) - } + } + + @asm ldrt reg_T maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/lsl_A8894.d b/plugins/arm/v7/opdefs/lsl_A8894.d index 89924c6..e5e8dc8 100644 --- a/plugins/arm/v7/opdefs/lsl_A8894.d +++ b/plugins/arm/v7/opdefs/lsl_A8894.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title LSL (immediate) -@desc Logical Shift Left (immediate) shifts a register value left by an immediate number of bits, shifting in zeros, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 93 + +@desc { + + Logical Shift Left (immediate) shifts a register value left by an immediate number of bits, shifting in zeros, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (t1) { @half 0 0 0 0 0 imm5(5) Rm(3) Rd(3) - @syntax "lsls" <reg_D> <reg_M> <shift_imm> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('00', imm5) - reg_D = Register(Rd) - reg_M = Register(Rm) - shift_imm = DecodeImmShift('00', imm5) + } + + @asm lsl ?reg_D reg_M shift_n } @@ -45,21 +55,43 @@ @word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm2(2) 0 0 Rm(4) - @syntax <reg_D> <reg_M> <shift_imm> + @syntax { + + @assert { + + S == 0 + + } - @conv { + @conv { - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - shift_imm = DecodeImmShift('00', imm3:imm2) + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('00', imm3:imm2) + + } + + @asm lsl.w ?reg_D reg_M shift_n } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('00', imm3:imm2) + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @asm lsls.w ?reg_D reg_M shift_n } @@ -69,21 +101,55 @@ @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) imm5(5) 0 0 0 Rm(4) - @syntax <reg_D> <reg_M> <shift_imm> + @syntax { - @conv { + @assert { - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - shift_imm = DecodeImmShift('00', imm5) + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('00', imm5) + + } + + @asm lsl ?reg_D reg_M shift_n + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('00', imm5) + + } + + @asm lsls ?reg_D reg_M shift_n + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/lsl_A8895.d b/plugins/arm/v7/opdefs/lsl_A8895.d index 4ac5ab6..8a7da49 100644 --- a/plugins/arm/v7/opdefs/lsl_A8895.d +++ b/plugins/arm/v7/opdefs/lsl_A8895.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,29 @@ @title LSL (register) -@desc Logical Shift Left (register) shifts a register value left by a variable number of bits, shifting in zeros, and writes the result to the destination register. The variable number of bits is read from the bottom byte of a register. It can optionally update the condition flags based on the result. +@id 94 + +@desc { + + Logical Shift Left (register) shifts a register value left by a variable number of bits, shifting in zeros, and writes the result to the destination register. The variable number of bits is read from the bottom byte of a register. It can optionally update the condition flags based on the result. + +} @encoding (t1) { @half 0 1 0 0 0 0 0 0 1 0 Rm(3) Rdn(3) - @syntax "lsls" <reg_DN> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rdn) + reg_N = Register(Rdn) + reg_M = Register(Rm) - reg_DN = Register(Rdn) - reg_M = Register(Rm) + } + + @asm lsl ?reg_D reg_N reg_M } @@ -44,21 +55,43 @@ @word 1 1 1 1 1 0 1 0 0 0 0 S(1) Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @assert { + + S == 0 + + } - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm lsl.w ?reg_D reg_N reg_M } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @asm lsls.w ?reg_D reg_N reg_M } @@ -68,21 +101,55 @@ @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) Rm(4) 0 0 0 1 Rn(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @assert { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm lsl ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm lsls ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/lsr_A8896.d b/plugins/arm/v7/opdefs/lsr_A8896.d index acb9e25..3ee0473 100644 --- a/plugins/arm/v7/opdefs/lsr_A8896.d +++ b/plugins/arm/v7/opdefs/lsr_A8896.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title LSR (immediate) -@desc Logical Shift Right (immediate) shifts a register value right by an immediate number of bits, shifting in zeros, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 95 + +@desc { + + Logical Shift Right (immediate) shifts a register value right by an immediate number of bits, shifting in zeros, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (t1) { @half 0 0 0 0 1 imm5(5) Rm(3) Rd(3) - @syntax "lsrs" <reg_D> <reg_M> <shift_imm> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('01', imm5) - reg_D = Register(Rd) - reg_M = Register(Rm) - shift_imm = DecodeImmShift('01', imm5) + } + + @asm lsr ?reg_D reg_M shift_n } @@ -45,21 +55,43 @@ @word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm2(2) 0 1 Rm(4) - @syntax <reg_D> <reg_M> <shift_imm> + @syntax { + + @assert { + + S == 0 + + } - @conv { + @conv { - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - shift_imm = DecodeImmShift('01', imm3:imm2) + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('01', imm3:imm2) + + } + + @asm lsr.w ?reg_D reg_M shift_n } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('01', imm3:imm2) + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @asm lsrs.w ?reg_D reg_M shift_n } @@ -69,21 +101,55 @@ @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) imm5(5) 0 1 0 Rm(4) - @syntax <reg_D> <reg_M> <shift_imm> + @syntax { - @conv { + @assert { - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - shift_imm = DecodeImmShift('01', imm5) + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('01', imm5) + + } + + @asm lsr ?reg_D reg_M shift_n + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('01', imm5) + + } + + @asm lsrs ?reg_D reg_M shift_n + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/lsr_A8897.d b/plugins/arm/v7/opdefs/lsr_A8897.d index 070a152..fa112ec 100644 --- a/plugins/arm/v7/opdefs/lsr_A8897.d +++ b/plugins/arm/v7/opdefs/lsr_A8897.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,29 @@ @title LSR (register) -@desc Logical Shift Right (register) shifts a register value right by a variable number of bits, shifting in zeros, and writes the result to the destination register. The variable number of bits is read from the bottom byte of a register. It can optionally update the condition flags based on the result. +@id 96 + +@desc { + + Logical Shift Right (register) shifts a register value right by a variable number of bits, shifting in zeros, and writes the result to the destination register. The variable number of bits is read from the bottom byte of a register. It can optionally update the condition flags based on the result. + +} @encoding (t1) { @half 0 1 0 0 0 0 0 0 1 1 Rm(3) Rdn(3) - @syntax "lsrs" <reg_DN> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rdn) + reg_N = Register(Rdn) + reg_M = Register(Rm) - reg_DN = Register(Rdn) - reg_M = Register(Rm) + } + + @asm lsr ?reg_D reg_N reg_M } @@ -44,21 +55,43 @@ @word 1 1 1 1 1 0 1 0 0 0 1 S(1) Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @assert { + + S == 0 + + } - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm lsr.w ?reg_D reg_N reg_M } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @asm lsrs.w ?reg_D reg_N reg_M } @@ -68,21 +101,55 @@ @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) Rm(4) 0 0 1 1 Rn(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @assert { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm lsr ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm lsrs ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/mcr_A8898.d b/plugins/arm/v7/opdefs/mcr_A8898.d index f710d5d..b0ece52 100644 --- a/plugins/arm/v7/opdefs/mcr_A8898.d +++ b/plugins/arm/v7/opdefs/mcr_A8898.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,22 +23,32 @@ @title MCR, MCR2 -@desc Move to Coprocessor from ARM core register passes the value of an ARM core register to a coprocessor. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the opc1, opc2, CRn, and CRm fields. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid MCR and MCR2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. In an implementation that includes the Virtualization Extensions, MCR accesses to system control registers can be trapped to Hyp mode, meaning that an attempt to execute an MCR instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see Traps to the hypervisor on page B1-1247. Note Because of the range of possible traps to Hyp mode, the MCR pseudocode does not show these possible traps. +@id 97 + +@desc { + + Move to Coprocessor from ARM core register passes the value of an ARM core register to a coprocessor. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the opc1, opc2, CRn, and CRm fields. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid MCR and MCR2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. In an implementation that includes the Virtualization Extensions, MCR accesses to system control registers can be trapped to Hyp mode, meaning that an attempt to execute an MCR instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see Traps to the hypervisor on page B1-1247. Note Because of the range of possible traps to Hyp mode, the MCR pseudocode does not show these possible traps. + +} @encoding (T1) { @word 1 1 1 0 1 1 1 0 opc1(3) 0 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) - @syntax <cp> <undef_opc1> <reg_T> <creg_N> <creg_M> <?undef_opc2> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - cp = CoProcessor(coproc) - undef_opc1 = RawValue(opc1) - creg_N = CRegister(CRn) - creg_M = CRegister(CRm) - undef_opc2 = RawValue(opc2) + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + reg_T = Register(Rt) + direct_CRn = UInt(CRn) + direct_CRm = UInt(CRm) + direct_opc2 = UInt(opc2) + + } + + @asm mcr cp direct_opc1 reg_T direct_CRn direct_CRm ?direct_opc2 } @@ -46,24 +56,22 @@ @encoding (A1) { - @word cond(4) 1 1 1 0 opc1(3) 0 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) - - @syntax <cp> <undef_opc1> <reg_T> <creg_N> <creg_M> <?undef_opc2> + @word 1 1 1 0 1 1 1 0 opc1(3) 0 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) - @conv { + @syntax { - reg_T = Register(Rt) - cp = CoProcessor(coproc) - undef_opc1 = RawValue(opc1) - creg_N = CRegister(CRn) - creg_M = CRegister(CRm) - undef_opc2 = RawValue(opc2) + @conv { - } + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + reg_T = Register(Rt) + direct_CRn = UInt(CRn) + direct_CRm = UInt(CRm) + direct_opc2 = UInt(opc2) - @rules { + } - chk_call StoreCondition(cond) + @asm mcr cp direct_opc1 reg_T direct_CRn direct_CRm ?direct_opc2 } @@ -73,16 +81,20 @@ @word 1 1 1 1 1 1 1 0 opc1(3) 0 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) - @syntax "mcr2" <cp> <undef_opc1> <reg_T> <creg_N> <creg_M> <?undef_opc2> + @syntax { + + @conv { - @conv { + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + reg_T = Register(Rt) + direct_CRn = UInt(CRn) + direct_CRm = UInt(CRm) + direct_opc2 = UInt(opc2) - reg_T = Register(Rt) - cp = CoProcessor(coproc) - undef_opc1 = RawValue(opc1) - creg_N = CRegister(CRn) - creg_M = CRegister(CRm) - undef_opc2 = RawValue(opc2) + } + + @asm mcr cp direct_opc1 reg_T direct_CRn direct_CRm ?direct_opc2 } @@ -92,16 +104,20 @@ @word 1 1 1 1 1 1 1 0 opc1(3) 0 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) - @syntax "mcr2" <cp> <undef_opc1> <reg_T> <creg_N> <creg_M> <?undef_opc2> + @syntax { + + @conv { + + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + reg_T = Register(Rt) + direct_CRn = UInt(CRn) + direct_CRm = UInt(CRm) + direct_opc2 = UInt(opc2) - @conv { + } - reg_T = Register(Rt) - cp = CoProcessor(coproc) - undef_opc1 = RawValue(opc1) - creg_N = CRegister(CRn) - creg_M = CRegister(CRm) - undef_opc2 = RawValue(opc2) + @asm mcr cp direct_opc1 reg_T direct_CRn direct_CRm ?direct_opc2 } diff --git a/plugins/arm/v7/opdefs/mcrr_A8899.d b/plugins/arm/v7/opdefs/mcrr_A8899.d index f643826..31e0f34 100644 --- a/plugins/arm/v7/opdefs/mcrr_A8899.d +++ b/plugins/arm/v7/opdefs/mcrr_A8899.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,21 +23,31 @@ @title MCRR, MCRR2 -@desc Move to Coprocessor from two ARM core registers passes the values of two ARM core registers to a coprocessor. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the opc1 and CRm fields. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid MCRR and MCRR2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. In an implementation that includes the Virtualization Extensions, MCRR accesses to system control registers can be trapped to Hyp mode, meaning that an attempt to execute an MCRR instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see Traps to the hypervisor on page B1-1247. Note Because of the range of possible traps to Hyp mode, the MCRR pseudocode does not show these possible traps. +@id 98 + +@desc { + + Move to Coprocessor from two ARM core registers passes the values of two ARM core registers to a coprocessor. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the opc1 and CRm fields. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid MCRR and MCRR2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. In an implementation that includes the Virtualization Extensions, MCRR accesses to system control registers can be trapped to Hyp mode, meaning that an attempt to execute an MCRR instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see Traps to the hypervisor on page B1-1247. Note Because of the range of possible traps to Hyp mode, the MCRR pseudocode does not show these possible traps. + +} @encoding (T1) { @word 1 1 1 0 1 1 0 0 0 1 0 0 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) - @syntax <cp> <undef_opc1> <reg_T> <reg_T2> <creg_M> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - cp = CoProcessor(coproc) - undef_opc1 = RawValue(opc1) - creg_M = CRegister(CRm) + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + direct_CRm = UInt(CRm) + + } + + @asm mcrr cp direct_opc1 reg_T reg_T2 direct_CRm } @@ -45,23 +55,21 @@ @encoding (A1) { - @word cond(4) 1 1 0 0 0 1 0 0 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) - - @syntax <cp> <undef_opc1> <reg_T> <reg_T2> <creg_M> + @word 1 1 1 0 1 1 0 0 0 1 0 0 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) - @conv { + @syntax { - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - cp = CoProcessor(coproc) - undef_opc1 = RawValue(opc1) - creg_M = CRegister(CRm) + @conv { - } + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + direct_CRm = UInt(CRm) - @rules { + } - chk_call StoreCondition(cond) + @asm mcrr cp direct_opc1 reg_T reg_T2 direct_CRm } @@ -71,15 +79,19 @@ @word 1 1 1 1 1 1 0 0 0 1 0 0 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) - @syntax "mcrr2" <cp> <undef_opc1> <reg_T> <reg_T2> <creg_M> + @syntax { + + @conv { - @conv { + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + direct_CRm = UInt(CRm) - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - cp = CoProcessor(coproc) - undef_opc1 = RawValue(opc1) - creg_M = CRegister(CRm) + } + + @asm mcrr cp direct_opc1 reg_T reg_T2 direct_CRm } @@ -89,15 +101,19 @@ @word 1 1 1 1 1 1 0 0 0 1 0 0 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) - @syntax "mcrr2" <cp> <undef_opc1> <reg_T> <reg_T2> <creg_M> + @syntax { + + @conv { + + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + direct_CRm = UInt(CRm) - @conv { + } - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - cp = CoProcessor(coproc) - undef_opc1 = RawValue(opc1) - creg_M = CRegister(CRm) + @asm mcrr cp direct_opc1 reg_T reg_T2 direct_CRm } diff --git a/plugins/arm/v7/opdefs/mla_A88100.d b/plugins/arm/v7/opdefs/mla_A88100.d index 5d4b4e4..654ae37 100644 --- a/plugins/arm/v7/opdefs/mla_A88100.d +++ b/plugins/arm/v7/opdefs/mla_A88100.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title MLA -@desc Multiply Accumulate multiplies two register values, and adds a third register value. The least significant 32 bits of the result are written to the destination register. These 32 bits do not depend on whether the source register values are considered to be signed values or unsigned values. In an ARM instruction, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many processor implementations. +@id 99 + +@desc { + + Multiply Accumulate multiplies two register values, and adds a third register value. The least significant 32 bits of the result are written to the destination register. These 32 bits do not depend on whether the source register values are considered to be signed values or unsigned values. In an ARM instruction, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many processor implementations. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 1 0 0 0 0 Rn(4) Ra(4) Rd(4) 0 0 0 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <reg_A> + @syntax { + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) - @conv { + } - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) + @asm mla reg_D reg_N reg_M reg_A } @@ -46,22 +56,57 @@ @word cond(4) 0 0 0 0 0 0 1 S(1) Rd(4) Ra(4) Rm(4) 1 0 0 1 Rn(4) - @syntax <reg_D> <reg_N> <reg_M> <reg_A> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } - @conv { + @asm mla reg_D reg_N reg_M reg_A - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - setflags = (S == '1') + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm mlas reg_D reg_N reg_M reg_A + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/mls_A88101.d b/plugins/arm/v7/opdefs/mls_A88101.d index 4d10be8..bdb9073 100644 --- a/plugins/arm/v7/opdefs/mls_A88101.d +++ b/plugins/arm/v7/opdefs/mls_A88101.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title MLS -@desc Multiply and Subtract multiplies two register values, and subtracts the product from a third register value. The least significant 32 bits of the result are written to the destination register. These 32 bits do not depend on whether the source register values are considered to be signed values or unsigned values. +@id 100 + +@desc { + + Multiply and Subtract multiplies two register values, and subtracts the product from a third register value. The least significant 32 bits of the result are written to the destination register. These 32 bits do not depend on whether the source register values are considered to be signed values or unsigned values. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 1 0 0 0 0 Rn(4) Ra(4) Rd(4) 0 0 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <reg_A> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) + } + + @asm mls reg_D reg_N reg_M reg_A } @@ -46,20 +56,24 @@ @word cond(4) 0 0 0 0 0 1 1 0 Rd(4) Ra(4) Rm(4) 1 0 0 1 Rn(4) - @syntax <reg_D> <reg_N> <reg_M> <reg_A> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) - } + } + + @asm mls reg_D reg_N reg_M reg_A + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/mov_A88102.d b/plugins/arm/v7/opdefs/mov_A88102.d index d96baab..e38442b 100644 --- a/plugins/arm/v7/opdefs/mov_A88102.d +++ b/plugins/arm/v7/opdefs/mov_A88102.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title MOV (immediate) -@desc Move (immediate) writes an immediate value to the destination register. It can optionally update the condition flags based on the value. +@id 101 + +@desc { + + Move (immediate) writes an immediate value to the destination register. It can optionally update the condition flags based on the value. + +} @encoding (t1) { @half 0 0 1 0 0 Rd(3) imm8(8) - @syntax "movs" <reg_D> <imm32> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + imm32 = ZeroExtend(imm8, 32) - reg_D = Register(Rd) - imm32 = ZeroExtend(imm8, 32) + } + + @asm mov reg_D imm32 } @@ -44,20 +54,41 @@ @word 1 1 1 1 0 i(1) 0 0 0 1 0 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm8(8) - @syntax <reg_D> <imm32> + @syntax { + + @assert { + + S == 0 + + } + + @conv { - @conv { + reg_D = Register(Rd) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) - reg_D = Register(Rd) - setflags = (S == '1') - imm32 = ThumbExpandImm_C(i:imm3:imm8, 0) + } + + @asm mov.w reg_D const } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + reg_D = Register(Rd) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) + + } + + @asm movs.w reg_D const } @@ -67,12 +98,16 @@ @word 1 1 1 1 0 i(1) 1 0 0 1 0 0 imm4(4) 0 imm3(3) Rd(4) imm8(8) - @syntax "movw" <reg_D> <imm32> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + imm32 = ZeroExtend(imm4:i:imm3:imm8, 32) - reg_D = Register(Rd) - imm32 = ZeroExtend(imm4:i:imm3:imm8, 32) + } + + @asm movw reg_D imm32 } @@ -82,20 +117,53 @@ @word cond(4) 0 0 1 1 1 0 1 S(1) 0 0 0 0 Rd(4) imm12(12) - @syntax <reg_D> <imm32> + @syntax { + + @assert { - @conv { + S == 0 - reg_D = Register(Rd) - setflags = (S == '1') - imm32 = ARMExpandImm_C(imm12, 0) + } + + @conv { + + reg_D = Register(Rd) + const = ARMExpandImm_C(imm12, APSR_C) + + } + + @asm mov reg_D const + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + @conv { + + reg_D = Register(Rd) + const = ARMExpandImm_C(imm12, APSR_C) + + } + + @asm movs reg_D const + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } @@ -105,18 +173,22 @@ @word cond(4) 0 0 1 1 0 0 0 0 imm4(4) Rd(4) imm12(12) - @syntax "movw" <reg_D> <imm32> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - imm32 = ZeroExtend(imm4:imm12, 32) + reg_D = Register(Rd) + imm32 = ZeroExtend(imm4:imm12, 32) - } + } + + @asm movw reg_D imm32 + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/mov_A88103.d b/plugins/arm/v7/opdefs/mov_A88103.d index cd3d75a..8a25367 100644 --- a/plugins/arm/v7/opdefs/mov_A88103.d +++ b/plugins/arm/v7/opdefs/mov_A88103.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title MOV (register, Thumb) -@desc Move (register) copies a value from a register to the destination register. It can optionally update the condition flags based on the value. +@id 102 + +@desc { + + Move (register) copies a value from a register to the destination register. It can optionally update the condition flags based on the value. + +} @encoding (t1) { @half 0 1 0 0 0 1 1 0 D(1) Rm(4) Rd(3) - @syntax <reg_D> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(D:Rd) + reg_M = Register(Rm) - reg_D = Register(D:Rd) - reg_M = Register(Rm) + } + + @asm mov reg_D reg_M } @@ -44,12 +54,16 @@ @half 0 0 0 0 0 0 0 0 0 0 Rm(3) Rd(3) - @syntax "movs" <reg_D> <reg_M> + @syntax { + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) - @conv { + } - reg_D = Register(Rd) - reg_M = Register(Rm) + @asm movs reg_D reg_M } @@ -59,20 +73,41 @@ @word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 0 0 0 Rd(4) 0 0 0 0 Rm(4) - @syntax <reg_D> <reg_M> + @syntax { + + @assert { + + S == 0 - @conv { + } - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + + @asm mov.w reg_D reg_M } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @asm movs.w reg_D reg_M } diff --git a/plugins/arm/v7/opdefs/mov_A88104.d b/plugins/arm/v7/opdefs/mov_A88104.d index d164983..9335076 100644 --- a/plugins/arm/v7/opdefs/mov_A88104.d +++ b/plugins/arm/v7/opdefs/mov_A88104.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,26 +23,65 @@ @title MOV (register, ARM) -@desc Move (register) copies a value from a register to the destination register. It can optionally update the condition flags based on the value. +@id 103 + +@desc { + + Move (register) copies a value from a register to the destination register. It can optionally update the condition flags based on the value. + +} @encoding (A1) { @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) 0 0 0 0 0 0 0 0 Rm(4) - @syntax <reg_D> <reg_M> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + + @asm mov reg_D reg_M - @conv { + @rules { - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + + @asm movs reg_D reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/movt_A88106.d b/plugins/arm/v7/opdefs/movt_A88106.d index 265d008..58ba83c 100644 --- a/plugins/arm/v7/opdefs/movt_A88106.d +++ b/plugins/arm/v7/opdefs/movt_A88106.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title MOVT -@desc Move Top writes an immediate value to the top halfword of the destination register. It does not affect the contents of the bottom halfword. +@id 105 + +@desc { + + Move Top writes an immediate value to the top halfword of the destination register. It does not affect the contents of the bottom halfword. + +} @encoding (T1) { @word 1 1 1 1 0 i(1) 1 0 1 1 0 0 imm4(4) 0 imm3(3) Rd(4) imm8(8) - @syntax <reg_D> <imm16> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + imm16 = UInt(imm4:i:imm3:imm8) - reg_D = Register(Rd) - imm16 = BuildImm16(imm4:i:imm3:imm8) + } + + @asm movt reg_D imm16 } @@ -44,18 +54,22 @@ @word cond(4) 0 0 1 1 0 1 0 0 imm4(4) Rd(4) imm12(12) - @syntax <reg_D> <imm16> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - imm16 = BuildImm16(imm4:imm12) + reg_D = Register(Rd) + imm16 = UInt(imm4:imm12) - } + } + + @asm movt reg_D imm16 + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/mrc_A88107.d b/plugins/arm/v7/opdefs/mrc_A88107.d index fb9714c..9faecaa 100644 --- a/plugins/arm/v7/opdefs/mrc_A88107.d +++ b/plugins/arm/v7/opdefs/mrc_A88107.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,22 +23,32 @@ @title MRC, MRC2 -@desc Move to ARM core register from Coprocessor causes a coprocessor to transfer a value to an ARM core register or to the condition flags. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the opc1, opc2, CRn, and CRm fields. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid MRC and MRC2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. In an implementation that includes the Virtualization Extensions, MRC accesses to system control registers can be trapped to Hyp mode, meaning that an attempt to execute an MRC instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see Traps to the hypervisor on page B1-1247. Note Because of the range of possible traps to Hyp mode, the MRC pseudocode does not show these possible traps. +@id 106 + +@desc { + + Move to ARM core register from Coprocessor causes a coprocessor to transfer a value to an ARM core register or to the condition flags. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the opc1, opc2, CRn, and CRm fields. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid MRC and MRC2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. In an implementation that includes the Virtualization Extensions, MRC accesses to system control registers can be trapped to Hyp mode, meaning that an attempt to execute an MRC instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see Traps to the hypervisor on page B1-1247. Note Because of the range of possible traps to Hyp mode, the MRC pseudocode does not show these possible traps. + +} @encoding (T1) { @word 1 1 1 0 1 1 1 0 opc1(3) 1 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) - @syntax <cp> <undef_opc1> <reg_T> <creg_N> <creg_M> <?undef_opc2> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - cp = CoProcessor(coproc) - undef_opc1 = RawValue(opc1) - creg_N = CRegister(CRn) - creg_M = CRegister(CRm) - undef_opc2 = RawValue(opc2) + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + reg_T = Register(Rt) + direct_CRn = UInt(CRn) + direct_CRm = UInt(CRm) + direct_opc2 = UInt(opc2) + + } + + @asm mrc cp direct_opc1 reg_T direct_CRn direct_CRm ?direct_opc2 } @@ -46,24 +56,22 @@ @encoding (A1) { - @word cond(4) 1 1 1 0 opc1(3) 1 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) - - @syntax <cp> <undef_opc1> <reg_T> <creg_N> <creg_M> <?undef_opc2> + @word 1 1 1 0 1 1 1 0 opc1(3) 1 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) - @conv { + @syntax { - reg_T = Register(Rt) - cp = CoProcessor(coproc) - undef_opc1 = RawValue(opc1) - creg_N = CRegister(CRn) - creg_M = CRegister(CRm) - undef_opc2 = RawValue(opc2) + @conv { - } + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + reg_T = Register(Rt) + direct_CRn = UInt(CRn) + direct_CRm = UInt(CRm) + direct_opc2 = UInt(opc2) - @rules { + } - chk_call StoreCondition(cond) + @asm mrc cp direct_opc1 reg_T direct_CRn direct_CRm ?direct_opc2 } @@ -73,16 +81,20 @@ @word 1 1 1 1 1 1 1 0 opc1(3) 1 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) - @syntax "mrc2" <cp> <undef_opc1> <reg_T> <creg_N> <creg_M> <?undef_opc2> + @syntax { + + @conv { - @conv { + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + reg_T = Register(Rt) + direct_CRn = UInt(CRn) + direct_CRm = UInt(CRm) + direct_opc2 = UInt(opc2) - reg_T = Register(Rt) - cp = CoProcessor(coproc) - undef_opc1 = RawValue(opc1) - creg_N = CRegister(CRn) - creg_M = CRegister(CRm) - undef_opc2 = RawValue(opc2) + } + + @asm mrc cp direct_opc1 reg_T direct_CRn direct_CRm ?direct_opc2 } @@ -92,16 +104,20 @@ @word 1 1 1 1 1 1 1 0 opc1(3) 1 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) - @syntax "mrc2" <cp> <undef_opc1> <reg_T> <creg_N> <creg_M> <?undef_opc2> + @syntax { + + @conv { + + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + reg_T = Register(Rt) + direct_CRn = UInt(CRn) + direct_CRm = UInt(CRm) + direct_opc2 = UInt(opc2) - @conv { + } - reg_T = Register(Rt) - cp = CoProcessor(coproc) - undef_opc1 = RawValue(opc1) - creg_N = CRegister(CRn) - creg_M = CRegister(CRm) - undef_opc2 = RawValue(opc2) + @asm mrc cp direct_opc1 reg_T direct_CRn direct_CRm ?direct_opc2 } diff --git a/plugins/arm/v7/opdefs/mrrc_A88108.d b/plugins/arm/v7/opdefs/mrrc_A88108.d index 026c0ef..d981e93 100644 --- a/plugins/arm/v7/opdefs/mrrc_A88108.d +++ b/plugins/arm/v7/opdefs/mrrc_A88108.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,21 +23,31 @@ @title MRRC, MRRC2 -@desc Move to two ARM core registers from Coprocessor causes a coprocessor to transfer values to two ARM core registers. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the opc1 and CRm fields. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid MRRC and MRRC2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. In an implementation that includes the Virtualization Extensions, MRRC accesses to system control registers can be trapped to Hyp mode, meaning that an attempt to execute an MRRC instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see Traps to the hypervisor on page B1-1247. Note Because of the range of possible traps to Hyp mode, the MRRC pseudocode does not show these possible traps. +@id 107 + +@desc { + + Move to two ARM core registers from Coprocessor causes a coprocessor to transfer values to two ARM core registers. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the opc1 and CRm fields. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid MRRC and MRRC2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. In an implementation that includes the Virtualization Extensions, MRRC accesses to system control registers can be trapped to Hyp mode, meaning that an attempt to execute an MRRC instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see Traps to the hypervisor on page B1-1247. Note Because of the range of possible traps to Hyp mode, the MRRC pseudocode does not show these possible traps. + +} @encoding (T1) { @word 1 1 1 0 1 1 0 0 0 1 0 1 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) - @syntax <cp> <opc> <reg_T> <reg_T2> <creg_M> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - cp = CoProcessor(coproc) - opc = RawValue(opc1) - creg_M = CRegister(CRm) + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + direct_CRm = UInt(CRm) + + } + + @asm mrrc cp direct_opc1 reg_T reg_T2 direct_CRm } @@ -45,23 +55,21 @@ @encoding (A1) { - @word cond(4) 1 1 0 0 0 1 0 1 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) - - @syntax <cp> <opc> <reg_T> <reg_T2> <creg_M> + @word 1 1 1 0 1 1 0 0 0 1 0 1 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) - @conv { + @syntax { - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - cp = CoProcessor(coproc) - opc = RawValue(opc1) - creg_M = CRegister(CRm) + @conv { - } + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + direct_CRm = UInt(CRm) - @rules { + } - chk_call StoreCondition(cond) + @asm mrrc cp direct_opc1 reg_T reg_T2 direct_CRm } @@ -71,15 +79,19 @@ @word 1 1 1 1 1 1 0 0 0 1 0 1 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) - @syntax "mrrc2" <cp> <opc> <reg_T> <reg_T2> <creg_M> + @syntax { + + @conv { - @conv { + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + direct_CRm = UInt(CRm) - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - cp = CoProcessor(coproc) - opc = RawValue(opc1) - creg_M = CRegister(CRm) + } + + @asm mrrc cp direct_opc1 reg_T reg_T2 direct_CRm } @@ -89,15 +101,19 @@ @word 1 1 1 1 1 1 0 0 0 1 0 1 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) - @syntax "mrrc2" <cp> <opc> <reg_T> <reg_T2> <creg_M> + @syntax { + + @conv { + + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + direct_CRm = UInt(CRm) - @conv { + } - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - cp = CoProcessor(coproc) - opc = RawValue(opc1) - creg_M = CRegister(CRm) + @asm mrrc cp direct_opc1 reg_T reg_T2 direct_CRm } diff --git a/plugins/arm/v7/opdefs/mul_A88114.d b/plugins/arm/v7/opdefs/mul_A88114.d index fa250b7..25e6736 100644 --- a/plugins/arm/v7/opdefs/mul_A88114.d +++ b/plugins/arm/v7/opdefs/mul_A88114.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title MUL -@desc Multiply multiplies two register values. The least significant 32 bits of the result are written to the destination register. These 32 bits do not depend on whether the source register values are considered to be signed values or unsigned values. Optionally, it can update the condition flags based on the result. In the Thumb instruction set, this option is limited to only a few forms of the instruction. Use of this option adversely affects performance on many processor implementations. +@id 113 + +@desc { + + Multiply multiplies two register values. The least significant 32 bits of the result are written to the destination register. These 32 bits do not depend on whether the source register values are considered to be signed values or unsigned values. Optionally, it can update the condition flags based on the result. In the Thumb instruction set, this option is limited to only a few forms of the instruction. Use of this option adversely affects performance on many processor implementations. + +} @encoding (t1) { @half 0 1 0 0 0 0 1 1 0 1 Rn(3) Rdm(3) - @syntax "muls" <reg_DM_1> <reg_N> <reg_DM_2> + @syntax { - @conv { + @conv { - reg_N = Register(Rn) - reg_DM_1 = Register(Rdm) - reg_DM_2 = Register(Rdm) + reg_D = Register(Rdm) + reg_N = Register(Rn) + reg_M = Register(Rdm) + + } + + @asm mul reg_D reg_N ?reg_M } @@ -45,13 +55,17 @@ @word 1 1 1 1 1 0 1 1 0 0 0 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm mul reg_D reg_N ?reg_M } @@ -61,21 +75,55 @@ @word cond(4) 0 0 0 0 0 0 0 S(1) Rd(4) 0 0 0 0 Rm(4) 1 0 0 1 Rn(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - @conv { + } - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') + @asm mul reg_D reg_N ?reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm muls reg_D reg_N ?reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/mvn_A88115.d b/plugins/arm/v7/opdefs/mvn_A88115.d index 2955439..c27b3a5 100644 --- a/plugins/arm/v7/opdefs/mvn_A88115.d +++ b/plugins/arm/v7/opdefs/mvn_A88115.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,25 +23,53 @@ @title MVN (immediate) -@desc Bitwise NOT (immediate) writes the bitwise inverse of an immediate value to the destination register. It can optionally update the condition flags based on the value. +@id 114 + +@desc { + + Bitwise NOT (immediate) writes the bitwise inverse of an immediate value to the destination register. It can optionally update the condition flags based on the value. + +} @encoding (T1) { @word 1 1 1 1 0 i(1) 0 0 0 1 1 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm8(8) - @syntax <reg_D> <imm32> + @syntax { + + @assert { + + S == 0 + + } + + @conv { - @conv { + reg_D = Register(Rd) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) - reg_D = Register(Rd) - setflags = (S == '1') - imm32 = ThumbExpandImm_C(i:imm3:imm8, 0) + } + + @asm mvn reg_D const } - @rules { + @syntax { + + @assert { + + S == 1 + + } - if (setflags); chk_call ExtendKeyword("s") + @conv { + + reg_D = Register(Rd) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) + + } + + @asm mvns reg_D const } @@ -51,20 +79,53 @@ @word cond(4) 0 0 1 1 1 1 1 S(1) 0 0 0 0 Rd(4) imm12(12) - @syntax <reg_D> <imm32> + @syntax { + + @assert { - @conv { + S == 0 - reg_D = Register(Rd) - setflags = (S == '1') - imm32 = ARMExpandImm_C(imm12, 0) + } + + @conv { + + reg_D = Register(Rd) + const = ARMExpandImm_C(imm12, APSR_C) + + } + + @asm mvn reg_D const + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + const = ARMExpandImm_C(imm12, APSR_C) + + } + + @asm mvns reg_D const + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/mvn_A88116.d b/plugins/arm/v7/opdefs/mvn_A88116.d index 1f3f390..38ef06e 100644 --- a/plugins/arm/v7/opdefs/mvn_A88116.d +++ b/plugins/arm/v7/opdefs/mvn_A88116.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title MVN (register) -@desc Bitwise NOT (register) writes the bitwise inverse of a register value to the destination register. It can optionally update the condition flags based on the result. +@id 115 + +@desc { + + Bitwise NOT (register) writes the bitwise inverse of a register value to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (t1) { @half 0 1 0 0 0 0 1 1 1 1 Rm(3) Rd(3) - @syntax "mvns" <reg_D> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_M = Register(Rm) + } + + @asm mvn reg_D reg_M } @@ -44,21 +54,43 @@ @word 1 1 1 0 1 0 1 0 0 1 1 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - @syntax <reg_D> <reg_M> <?shift> + @syntax { + + @assert { + + S == 0 + + } - @conv { + @conv { - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm3:imm2) + reg_D = Register(Rd) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm mvn.w reg_D reg_M ?shift } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @asm mvns.w reg_D reg_M ?shift } @@ -68,21 +100,55 @@ @word cond(4) 0 0 0 1 1 1 1 S(1) 0 0 0 0 Rd(4) imm5(5) type(2) 0 Rm(4) - @syntax <reg_D> <reg_M> <?shift> + @syntax { - @conv { + @assert { - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm5) + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm mvn reg_D reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm mvns reg_D reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/mvn_A88117.d b/plugins/arm/v7/opdefs/mvn_A88117.d index cc6ef16..6556020 100644 --- a/plugins/arm/v7/opdefs/mvn_A88117.d +++ b/plugins/arm/v7/opdefs/mvn_A88117.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,27 +23,71 @@ @title MVN (register-shifted register) -@desc Bitwise NOT (register-shifted register) writes the bitwise inverse of a register-shifted register value to the destination register. It can optionally update the condition flags based on the result. +@id 116 + +@desc { + + Bitwise NOT (register-shifted register) writes the bitwise inverse of a register-shifted register value to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (A1) { @word cond(4) 0 0 0 1 1 1 1 S(1) 0 0 0 0 Rd(4) Rs(4) 0 type(2) 1 Rm(4) - @syntax <reg_D> <reg_M> <reg_shift> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm mvn reg_D reg_M shift - @conv { + @rules { - reg_shift = RegisterShift(type, Rs) - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm mvns reg_D reg_M shift + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/nop_A88119.d b/plugins/arm/v7/opdefs/nop_A88119.d index 84c495a..1f9b82f 100644 --- a/plugins/arm/v7/opdefs/nop_A88119.d +++ b/plugins/arm/v7/opdefs/nop_A88119.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,35 @@ @title NOP -@desc No Operation does nothing. This instruction can be used for instruction alignment purposes. See Pre-UAL pseudo-instruction NOP on page AppxH-2472 for details of NOP before the introduction of UAL and the ARMv6K and ARMv6T2 architecture variants. Note The timing effects of including a NOP instruction in a program are not guaranteed. It can increase execution time, leave it unchanged, or even reduce it. Therefore, NOP instructions are not suitable for timing loops. +@id 118 + +@desc { + + No Operation does nothing. This instruction can be used for instruction alignment purposes. See Pre-UAL pseudo-instruction NOP on page AppxH-2472 for details of NOP before the introduction of UAL and the ARMv6K and ARMv6T2 architecture variants. Note The timing effects of including a NOP instruction in a program are not guaranteed. It can increase execution time, leave it unchanged, or even reduce it. Therefore, NOP instructions are not suitable for timing loops. + +} @encoding (t1) { @half 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 + @syntax { + + @asm nop + + } + } @encoding (T2) { @word 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - @syntax ".W" + @syntax { + + @asm nop.w + + } } @@ -43,9 +59,15 @@ @word cond(4) 0 0 1 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 - @rules { + @syntax { + + @asm nop + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/orn_A88120.d b/plugins/arm/v7/opdefs/orn_A88120.d index b823b6c..339dd5d 100644 --- a/plugins/arm/v7/opdefs/orn_A88120.d +++ b/plugins/arm/v7/opdefs/orn_A88120.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,26 +23,55 @@ @title ORN (immediate) -@desc Bitwise OR NOT (immediate) performs a bitwise (inclusive) OR of a register value and the complement of an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 119 + +@desc { + + Bitwise OR NOT (immediate) performs a bitwise (inclusive) OR of a register value and the complement of an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (T1) { @word 1 1 1 1 0 i(1) 0 0 0 1 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - @syntax <reg_D> <reg_N> <imm32> + @syntax { + + @assert { + + S == 0 + + } + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ThumbExpandImm_C(i:imm3:imm8, 0) + } + + @asm orn ?reg_D reg_N const } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) + + } - if (setflags); chk_call ExtendKeyword("s") + @asm orns ?reg_D reg_N const } diff --git a/plugins/arm/v7/opdefs/orn_A88121.d b/plugins/arm/v7/opdefs/orn_A88121.d index f1523ec..5b32f94 100644 --- a/plugins/arm/v7/opdefs/orn_A88121.d +++ b/plugins/arm/v7/opdefs/orn_A88121.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,27 +23,57 @@ @title ORN (register) -@desc Bitwise OR NOT (register) performs a bitwise (inclusive) OR of a register value and the complement of an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 120 + +@desc { + + Bitwise OR NOT (register) performs a bitwise (inclusive) OR of a register value and the complement of an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (T1) { @word 1 1 1 0 1 0 1 0 0 1 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?shift> + @syntax { + + @assert { + + S == 0 + + } + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm3:imm2) + } + + @asm orn ?reg_D reg_N reg_M ?shift } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } - if (setflags); chk_call ExtendKeyword("s") + @asm orns ?reg_D reg_N reg_M ?shift } diff --git a/plugins/arm/v7/opdefs/orr_A88122.d b/plugins/arm/v7/opdefs/orr_A88122.d index 766b5ee..8b159ad 100644 --- a/plugins/arm/v7/opdefs/orr_A88122.d +++ b/plugins/arm/v7/opdefs/orr_A88122.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,26 +23,55 @@ @title ORR (immediate) -@desc Bitwise OR (immediate) performs a bitwise (inclusive) OR of a register value and an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 121 + +@desc { + + Bitwise OR (immediate) performs a bitwise (inclusive) OR of a register value and an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (T1) { @word 1 1 1 1 0 i(1) 0 0 0 1 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - @syntax <reg_D> <reg_N> <imm32> + @syntax { + + @assert { + + S == 0 + + } + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ThumbExpandImm_C(i:imm3:imm8, 0) + } + + @asm orr ?reg_D reg_N const } - @rules { + @syntax { + + @assert { + + S == 1 + + } - if (setflags); chk_call ExtendKeyword("s") + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) + + } + + @asm orrs ?reg_D reg_N const } @@ -52,21 +81,55 @@ @word cond(4) 0 0 1 1 1 0 0 S(1) Rn(4) Rd(4) imm12(12) - @syntax <reg_D> <reg_N> <imm32> + @syntax { + + @assert { - @conv { + S == 0 - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ARMExpandImm_C(imm12, 0) + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ARMExpandImm_C(imm12, APSR_C) + + } + + @asm orr ?reg_D reg_N const + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ARMExpandImm_C(imm12, APSR_C) + + } + + @asm orrs ?reg_D reg_N const + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/orr_A88123.d b/plugins/arm/v7/opdefs/orr_A88123.d index 2395c89..1549d28 100644 --- a/plugins/arm/v7/opdefs/orr_A88123.d +++ b/plugins/arm/v7/opdefs/orr_A88123.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,29 @@ @title ORR (register) -@desc Bitwise OR (register) performs a bitwise (inclusive) OR of a register value and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 122 + +@desc { + + Bitwise OR (register) performs a bitwise (inclusive) OR of a register value and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (t1) { @half 0 1 0 0 0 0 1 1 0 0 Rm(3) Rdn(3) - @syntax "orrs" <reg_DN> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rdn) + reg_N = Register(Rdn) + reg_M = Register(Rm) - reg_DN = Register(Rdn) - reg_M = Register(Rm) + } + + @asm orr ?reg_D reg_N reg_M } @@ -44,22 +55,45 @@ @word 1 1 1 0 1 0 1 0 0 1 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?shift> + @syntax { + + @assert { + + S == 0 + + } - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm3:imm2) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm orr.w ?reg_D reg_N reg_M ?shift } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @asm orrs.w ?reg_D reg_N reg_M ?shift } @@ -69,22 +103,57 @@ @word cond(4) 0 0 0 1 1 0 0 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?shift> + @syntax { - @conv { + @assert { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm5) + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm orr ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm orrs ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/orr_A88124.d b/plugins/arm/v7/opdefs/orr_A88124.d index f4d78b9..85648ed 100644 --- a/plugins/arm/v7/opdefs/orr_A88124.d +++ b/plugins/arm/v7/opdefs/orr_A88124.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,28 +23,73 @@ @title ORR (register-shifted register) -@desc Bitwise OR (register-shifted register) performs a bitwise (inclusive) OR of a register value and a register-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 123 + +@desc { + + Bitwise OR (register-shifted register) performs a bitwise (inclusive) OR of a register value and a register-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (A1) { @word cond(4) 0 0 0 1 1 0 0 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <reg_shift> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm orr ?reg_D reg_N reg_M shift - @conv { + @rules { - reg_shift = RegisterShift(type, Rs) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm orrs ?reg_D reg_N reg_M shift + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/pop_A88131.d b/plugins/arm/v7/opdefs/pop_A88131.d index 2dee09a..1169729 100644 --- a/plugins/arm/v7/opdefs/pop_A88131.d +++ b/plugins/arm/v7/opdefs/pop_A88131.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,17 +23,27 @@ @title POP (Thumb) -@desc Pop Multiple Registers loads multiple registers from the stack, loading from consecutive memory locations starting at the address in SP, and updates SP to point just above the loaded data. +@id 130 + +@desc { + + Pop Multiple Registers loads multiple registers from the stack, loading from consecutive memory locations starting at the address in SP, and updates SP to point just above the loaded data. + +} @encoding (t1) { @half 1 0 1 1 1 1 0 P(1) register_list(8) - @syntax <registers> + @syntax { + + @conv { - @conv { + registers = RegList(P:'0000000':register_list) - registers = RegistersList(P:'0000000':register_list) + } + + @asm pop registers } @@ -49,11 +59,15 @@ @word 1 1 1 0 1 0 0 0 1 0 1 1 1 1 0 1 P(1) M(1) 0 register_list(13) - @syntax ".W" <registers> + @syntax { + + @conv { + + registers = RegList(P:M:'0':register_list) - @conv { + } - registers = RegistersList(P:M:'0':register_list) + @asm pop.w registers } @@ -69,11 +83,15 @@ @word 1 1 1 1 1 0 0 0 0 1 0 1 1 1 0 1 Rt(4) 1 0 1 1 0 0 0 0 0 1 0 0 - @syntax ".W" <registers> + @syntax { + + @conv { + + registers = SingleRegList(Rt) - @conv { + } - registers = RegistersList(1 << Rt) + @asm pop.w registers } diff --git a/plugins/arm/v7/opdefs/pop_A88132.d b/plugins/arm/v7/opdefs/pop_A88132.d index 27bbf3b..276bad4 100644 --- a/plugins/arm/v7/opdefs/pop_A88132.d +++ b/plugins/arm/v7/opdefs/pop_A88132.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,23 +23,33 @@ @title POP (ARM) -@desc Pop Multiple Registers loads multiple registers from the stack, loading from consecutive memory locations starting at the address in SP, and updates SP to point just above the loaded data. +@id 131 + +@desc { + + Pop Multiple Registers loads multiple registers from the stack, loading from consecutive memory locations starting at the address in SP, and updates SP to point just above the loaded data. + +} @encoding (A1) { @word cond(4) 1 0 0 0 1 0 1 1 1 1 0 1 register_list(16) - @syntax <registers> + @syntax { - @conv { + @conv { - registers = RegistersList(register_list) + registers = RegList(register_list) - } + } - @rules { + @asm pop registers - chk_call StoreCondition(cond) + @rules { + + check g_arm_instruction_set_cond(cond) + + } } @@ -55,17 +65,21 @@ @word cond(4) 0 1 0 0 1 0 0 1 1 1 0 1 Rt(4) 0 0 0 0 0 0 0 0 0 1 0 0 - @syntax <registers> + @syntax { - @conv { + @conv { - registers = RegistersList(1 << Rt) + registers = SingleRegList(Rt) - } + } + + @asm pop registers + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/push_A88133.d b/plugins/arm/v7/opdefs/push_A88133.d index 14fc3e9..aa7fe56 100644 --- a/plugins/arm/v7/opdefs/push_A88133.d +++ b/plugins/arm/v7/opdefs/push_A88133.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,17 +23,27 @@ @title PUSH -@desc Push Multiple Registers stores multiple registers to the stack, storing to consecutive memory locations ending just below the address in SP, and updates SP to point to the start of the stored data. +@id 132 + +@desc { + + Push Multiple Registers stores multiple registers to the stack, storing to consecutive memory locations ending just below the address in SP, and updates SP to point to the start of the stored data. + +} @encoding (t1) { @half 1 0 1 1 0 1 0 M(1) register_list(8) - @syntax <registers> + @syntax { - @conv { + @conv { - registers = RegistersList('0':M:'000000':register_list) + registers = RegList('0':M:'000000':register_list) + + } + + @asm push registers } @@ -43,11 +53,15 @@ @word 1 1 1 0 1 0 0 1 0 0 1 0 1 1 0 1 0 M(1) 0 register_list(13) - @syntax ".W" <registers> + @syntax { + + @conv { + + registers = RegList('0':M:'0':register_list) - @conv { + } - registers = RegistersList('0':M:'0':register_list) + @asm push.w registers } @@ -57,11 +71,15 @@ @word 1 1 1 1 1 0 0 0 0 1 0 0 1 1 0 1 Rt(4) 1 1 0 1 0 0 0 0 0 1 0 0 - @syntax ".W" <registers> + @syntax { - @conv { + @conv { - registers = Zeros(16) + registers = SingleRegList(Rt) + + } + + @asm push.w registers } @@ -71,17 +89,21 @@ @word cond(4) 1 0 0 1 0 0 1 0 1 1 0 1 register_list(16) - @syntax <registers> + @syntax { - @conv { + @conv { - registers = RegistersList(register_list) + registers = RegList(register_list) - } + } + + @asm push registers - @rules { + @rules { - chk_call StoreCondition(cond) + check g_arm_instruction_set_cond(cond) + + } } @@ -91,17 +113,21 @@ @word cond(4) 0 1 0 1 0 0 1 0 1 1 0 1 Rt(4) 0 0 0 0 0 0 0 0 0 1 0 0 - @syntax <registers> + @syntax { - @conv { + @conv { - registers = Zeros(16) + registers = SingleRegList(Rt) - } + } + + @asm push registers + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/qadd16_A88135.d b/plugins/arm/v7/opdefs/qadd16_A88135.d index 15af29d..bc7366e 100644 --- a/plugins/arm/v7/opdefs/qadd16_A88135.d +++ b/plugins/arm/v7/opdefs/qadd16_A88135.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title QADD16 -@desc Saturating Add 16 performs two 16-bit integer additions, saturates the results to the 16-bit signed integer range –215 ≤ x ≤ 215 – 1, and writes the results to the destination register. +@id 134 + +@desc { + + Saturating Add 16 performs two 16-bit integer additions, saturates the results to the 16-bit signed integer range –215 ≤ x ≤ 215 – 1, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 0 1 Rn(4) 1 1 1 1 Rd(4) 0 0 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm qadd16 ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 0 1 0 Rn(4) Rd(4) 1 1 1 1 0 0 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm qadd16 ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/qadd8_A88136.d b/plugins/arm/v7/opdefs/qadd8_A88136.d index a71b251..2128a39 100644 --- a/plugins/arm/v7/opdefs/qadd8_A88136.d +++ b/plugins/arm/v7/opdefs/qadd8_A88136.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title QADD8 -@desc Saturating Add 8 performs four 8-bit integer additions, saturates the results to the 8-bit signed integer range –27 ≤ x ≤ 27 – 1, and writes the results to the destination register. +@id 135 + +@desc { + + Saturating Add 8 performs four 8-bit integer additions, saturates the results to the 8-bit signed integer range –27 ≤ x ≤ 27 – 1, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm qadd8 ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 0 1 0 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm qadd8 ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/qadd_A88134.d b/plugins/arm/v7/opdefs/qadd_A88134.d index f932983..37a22ba 100644 --- a/plugins/arm/v7/opdefs/qadd_A88134.d +++ b/plugins/arm/v7/opdefs/qadd_A88134.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title QADD -@desc Saturating Add adds two register values, saturates the result to the 32-bit signed integer range –231 to (231 – 1), and writes the result to the destination register. If saturation occurs, it sets the Q flag in the APSR. +@id 133 + +@desc { + + Saturating Add adds two register values, saturates the result to the 32-bit signed integer range –231 to (231 – 1), and writes the result to the destination register. If saturation occurs, it sets the Q flag in the APSR. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 1 0 0 0 Rm(4) - @syntax <reg_D> <reg_M> <reg_N> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_M = Register(Rm) + reg_N = Register(Rn) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm qadd ?reg_D reg_M reg_N } @@ -45,19 +55,23 @@ @word cond(4) 0 0 0 1 0 0 0 0 Rn(4) Rd(4) 0 0 0 0 0 1 0 1 Rm(4) - @syntax <reg_D> <reg_M> <reg_N> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_M = Register(Rm) + reg_N = Register(Rn) - } + } + + @asm qadd ?reg_D reg_M reg_N + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/qasx_A88137.d b/plugins/arm/v7/opdefs/qasx_A88137.d index 68251ca..5063f8e 100644 --- a/plugins/arm/v7/opdefs/qasx_A88137.d +++ b/plugins/arm/v7/opdefs/qasx_A88137.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title QASX -@desc Saturating Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one 16-bit integer addition and one 16-bit subtraction, saturates the results to the 16-bit signed integer range –215 ≤ x ≤ 215 – 1, and writes the results to the destination register. +@id 136 + +@desc { + + Saturating Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one 16-bit integer addition and one 16-bit subtraction, saturates the results to the 16-bit signed integer range –215 ≤ x ≤ 215 – 1, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 1 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm qasx ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 0 1 0 Rn(4) Rd(4) 1 1 1 1 0 0 1 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm qasx ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/qdadd_A88138.d b/plugins/arm/v7/opdefs/qdadd_A88138.d index c40cdcd..1f915b8 100644 --- a/plugins/arm/v7/opdefs/qdadd_A88138.d +++ b/plugins/arm/v7/opdefs/qdadd_A88138.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title QDADD -@desc Saturating Double and Add adds a doubled register value to another register value, and writes the result to the destination register. Both the doubling and the addition have their results saturated to the 32-bit signed integer range –231 ≤ x ≤ 231 – 1. If saturation occurs in either operation, it sets the Q flag in the APSR. +@id 137 + +@desc { + + Saturating Double and Add adds a doubled register value to another register value, and writes the result to the destination register. Both the doubling and the addition have their results saturated to the 32-bit signed integer range –231 ≤ x ≤ 231 – 1. If saturation occurs in either operation, it sets the Q flag in the APSR. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 1 0 0 1 Rm(4) - @syntax <reg_D> <reg_M> <reg_N> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_M = Register(Rm) + reg_N = Register(Rn) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm qdadd ?reg_D reg_M reg_N } @@ -45,19 +55,23 @@ @word cond(4) 0 0 0 1 0 1 0 0 Rn(4) Rd(4) 0 0 0 0 0 1 0 1 Rm(4) - @syntax <reg_D> <reg_M> <reg_N> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_M = Register(Rm) + reg_N = Register(Rn) - } + } + + @asm qdadd ?reg_D reg_M reg_N + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/qdsub_A88139.d b/plugins/arm/v7/opdefs/qdsub_A88139.d index 87bd083..b726b6d 100644 --- a/plugins/arm/v7/opdefs/qdsub_A88139.d +++ b/plugins/arm/v7/opdefs/qdsub_A88139.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title QDSUB -@desc Saturating Double and Subtract subtracts a doubled register value from another register value, and writes the result to the destination register. Both the doubling and the subtraction have their results saturated to the 32-bit signed integer range –231 ≤ x ≤ 231 – 1. If saturation occurs in either operation, it sets the Q flag in the APSR. +@id 138 + +@desc { + + Saturating Double and Subtract subtracts a doubled register value from another register value, and writes the result to the destination register. Both the doubling and the subtraction have their results saturated to the 32-bit signed integer range –231 ≤ x ≤ 231 – 1. If saturation occurs in either operation, it sets the Q flag in the APSR. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 1 0 1 1 Rm(4) - @syntax <reg_D> <reg_M> <reg_N> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_M = Register(Rm) + reg_N = Register(Rn) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm qdsub ?reg_D reg_M reg_N } @@ -45,19 +55,23 @@ @word cond(4) 0 0 0 1 0 1 1 0 Rn(4) Rd(4) 0 0 0 0 0 1 0 1 Rm(4) - @syntax <reg_D> <reg_M> <reg_N> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_M = Register(Rm) + reg_N = Register(Rn) - } + } + + @asm qdsub ?reg_D reg_M reg_N + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/qsax_A88140.d b/plugins/arm/v7/opdefs/qsax_A88140.d index df24cf8..1a9d204 100644 --- a/plugins/arm/v7/opdefs/qsax_A88140.d +++ b/plugins/arm/v7/opdefs/qsax_A88140.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title QSAX -@desc Saturating Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one 16-bit integer subtraction and one 16-bit addition, saturates the results to the 16-bit signed integer range –215 ≤ x ≤ 215 – 1, and writes the results to the destination register. +@id 139 + +@desc { + + Saturating Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one 16-bit integer subtraction and one 16-bit addition, saturates the results to the 16-bit signed integer range –215 ≤ x ≤ 215 – 1, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 1 1 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm qsax ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 0 1 0 Rn(4) Rd(4) 1 1 1 1 0 1 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm qsax ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/qsub16_A88142.d b/plugins/arm/v7/opdefs/qsub16_A88142.d index 5b2c96b..ca28003 100644 --- a/plugins/arm/v7/opdefs/qsub16_A88142.d +++ b/plugins/arm/v7/opdefs/qsub16_A88142.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title QSUB16 -@desc Saturating Subtract 16 performs two 16-bit integer subtractions, saturates the results to the 16-bit signed integer range –215 ≤ x ≤ 215 – 1, and writes the results to the destination register. +@id 141 + +@desc { + + Saturating Subtract 16 performs two 16-bit integer subtractions, saturates the results to the 16-bit signed integer range –215 ≤ x ≤ 215 – 1, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 1 0 1 Rn(4) 1 1 1 1 Rd(4) 0 0 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm qsub16 ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 0 1 0 Rn(4) Rd(4) 1 1 1 1 0 1 1 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm qsub16 ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/qsub8_A88143.d b/plugins/arm/v7/opdefs/qsub8_A88143.d index 270a99d..8ec9a11 100644 --- a/plugins/arm/v7/opdefs/qsub8_A88143.d +++ b/plugins/arm/v7/opdefs/qsub8_A88143.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title QSUB8 -@desc Saturating Subtract 8 performs four 8-bit integer subtractions, saturates the results to the 8-bit signed integer range –27 ≤ x ≤ 27 – 1, and writes the results to the destination register. +@id 142 + +@desc { + + Saturating Subtract 8 performs four 8-bit integer subtractions, saturates the results to the 8-bit signed integer range –27 ≤ x ≤ 27 – 1, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 1 0 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm qsub8 ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 0 1 0 Rn(4) Rd(4) 1 1 1 1 1 1 1 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm qsub8 ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/qsub_A88141.d b/plugins/arm/v7/opdefs/qsub_A88141.d index c60ec57..6a3b19f 100644 --- a/plugins/arm/v7/opdefs/qsub_A88141.d +++ b/plugins/arm/v7/opdefs/qsub_A88141.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title QSUB -@desc Saturating Subtract subtracts one register value from another register value, saturates the result to the 32-bit signed integer range –231 ≤ x ≤ 231 – 1, and writes the result to the destination register. If saturation occurs, it sets the Q flag in the APSR. +@id 140 + +@desc { + + Saturating Subtract subtracts one register value from another register value, saturates the result to the 32-bit signed integer range –231 ≤ x ≤ 231 – 1, and writes the result to the destination register. If saturation occurs, it sets the Q flag in the APSR. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 1 0 1 0 Rm(4) - @syntax <reg_D> <reg_M> <reg_N> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_M = Register(Rm) + reg_N = Register(Rn) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm qsub ?reg_D reg_M reg_N } @@ -45,19 +55,23 @@ @word cond(4) 0 0 0 1 0 0 1 0 Rn(4) Rd(4) 0 0 0 0 0 1 0 1 Rm(4) - @syntax <reg_D> <reg_M> <reg_N> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_M = Register(Rm) + reg_N = Register(Rn) - } + } + + @asm qsub ?reg_D reg_M reg_N + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/rbit_A88144.d b/plugins/arm/v7/opdefs/rbit_A88144.d index 7f2bdb6..9d1c149 100644 --- a/plugins/arm/v7/opdefs/rbit_A88144.d +++ b/plugins/arm/v7/opdefs/rbit_A88144.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title RBIT -@desc Reverse Bits reverses the bit order in a 32-bit register. +@id 143 + +@desc { + + Reverse Bits reverses the bit order in a 32-bit register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 0 1 Rm(4) 1 1 1 1 Rd(4) 1 0 1 0 Rm(4) - @syntax <reg_D> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_M = Register(Rm) + } + + @asm rbit reg_D reg_M } @@ -44,18 +54,22 @@ @word cond(4) 0 1 1 0 1 1 1 1 1 1 1 1 Rd(4) 1 1 1 1 0 0 1 1 Rm(4) - @syntax <reg_D> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_M = Register(Rm) - } + } + + @asm rbit reg_D reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/rev16_A88146.d b/plugins/arm/v7/opdefs/rev16_A88146.d index 53b9a82..3bf8266 100644 --- a/plugins/arm/v7/opdefs/rev16_A88146.d +++ b/plugins/arm/v7/opdefs/rev16_A88146.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title REV16 -@desc Byte-Reverse Packed Halfword reverses the byte order in each16-bit halfword of a 32-bit register. +@id 145 + +@desc { + + Byte-Reverse Packed Halfword reverses the byte order in each16-bit halfword of a 32-bit register. + +} @encoding (t1) { @half 1 0 1 1 1 0 1 0 0 1 Rm(3) Rd(3) - @syntax <reg_D> <reg_M> + @syntax { + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) - @conv { + } - reg_D = Register(Rd) - reg_M = Register(Rm) + @asm rev16 reg_D reg_M } @@ -44,12 +54,16 @@ @word 1 1 1 1 1 0 1 0 1 0 0 1 Rm(4) 1 1 1 1 Rd(4) 1 0 0 1 Rm(4) - @syntax ".W" <reg_D> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + + @asm rev16.w reg_D reg_M } @@ -59,18 +73,22 @@ @word cond(4) 0 1 1 0 1 0 1 1 1 1 1 1 Rd(4) 1 1 1 1 1 0 1 1 Rm(4) - @syntax <reg_D> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_M = Register(Rm) - } + } + + @asm rev16 reg_D reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/rev_A88145.d b/plugins/arm/v7/opdefs/rev_A88145.d index 2fe305d..0a96df9 100644 --- a/plugins/arm/v7/opdefs/rev_A88145.d +++ b/plugins/arm/v7/opdefs/rev_A88145.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title REV -@desc Byte-Reverse Word reverses the byte order in a 32-bit register. +@id 144 + +@desc { + + Byte-Reverse Word reverses the byte order in a 32-bit register. + +} @encoding (t1) { @half 1 0 1 1 1 0 1 0 0 0 Rm(3) Rd(3) - @syntax <reg_D> <reg_M> + @syntax { + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) - @conv { + } - reg_D = Register(Rd) - reg_M = Register(Rm) + @asm rev reg_D reg_M } @@ -44,12 +54,16 @@ @word 1 1 1 1 1 0 1 0 1 0 0 1 Rm(4) 1 1 1 1 Rd(4) 1 0 0 0 Rm(4) - @syntax ".W" <reg_D> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + + @asm rev.w reg_D reg_M } @@ -59,18 +73,22 @@ @word cond(4) 0 1 1 0 1 0 1 1 1 1 1 1 Rd(4) 1 1 1 1 0 0 1 1 Rm(4) - @syntax <reg_D> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_M = Register(Rm) - } + } + + @asm rev reg_D reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/revsh_A88147.d b/plugins/arm/v7/opdefs/revsh_A88147.d index 551582c..bd290cc 100644 --- a/plugins/arm/v7/opdefs/revsh_A88147.d +++ b/plugins/arm/v7/opdefs/revsh_A88147.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title REVSH -@desc Byte-Reverse Signed Halfword reverses the byte order in the lower 16-bit halfword of a 32-bit register, and sign-extends the result to 32 bits. +@id 146 + +@desc { + + Byte-Reverse Signed Halfword reverses the byte order in the lower 16-bit halfword of a 32-bit register, and sign-extends the result to 32 bits. + +} @encoding (t1) { @half 1 0 1 1 1 0 1 0 1 1 Rm(3) Rd(3) - @syntax <reg_D> <reg_M> + @syntax { + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) - @conv { + } - reg_D = Register(Rd) - reg_M = Register(Rm) + @asm revsh reg_D reg_M } @@ -44,12 +54,16 @@ @word 1 1 1 1 1 0 1 0 1 0 0 1 Rm(4) 1 1 1 1 Rd(4) 1 0 1 1 Rm(4) - @syntax ".W" <reg_D> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + + @asm revsh.w reg_D reg_M } @@ -59,18 +73,22 @@ @word cond(4) 0 1 1 0 1 1 1 1 1 1 1 1 Rd(4) 1 1 1 1 1 0 1 1 Rm(4) - @syntax <reg_D> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_M = Register(Rm) - } + } + + @asm revsh reg_D reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ror_A88149.d b/plugins/arm/v7/opdefs/ror_A88149.d index 7e061c6..0717a95 100644 --- a/plugins/arm/v7/opdefs/ror_A88149.d +++ b/plugins/arm/v7/opdefs/ror_A88149.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,26 +23,55 @@ @title ROR (immediate) -@desc Rotate Right (immediate) provides the value of the contents of a register rotated by a constant value. The bits that are rotated off the right end are inserted into the vacated bit positions on the left. It can optionally update the condition flags based on the result. +@id 148 + +@desc { + + Rotate Right (immediate) provides the value of the contents of a register rotated by a constant value. The bits that are rotated off the right end are inserted into the vacated bit positions on the left. It can optionally update the condition flags based on the result. + +} @encoding (T1) { @word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm2(2) 1 1 Rm(4) - @syntax <reg_D> <reg_M> <shift_imm> + @syntax { + + @assert { + + S == 0 + + } + + @conv { - @conv { + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('11', imm3:imm2) - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - shift_imm = DecodeImmShift('11', imm3:imm2) + } + + @asm ror ?reg_D reg_M shift_n } - @rules { + @syntax { + + @assert { + + S == 1 + + } - if (setflags); chk_call ExtendKeyword("s") + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('11', imm3:imm2) + + } + + @asm rors ?reg_D reg_M shift_n } @@ -52,21 +81,55 @@ @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) imm5(5) 1 1 0 Rm(4) - @syntax <reg_D> <reg_M> <shift_imm> + @syntax { + + @assert { - @conv { + S == 0 - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - shift_imm = DecodeImmShift('11', imm5) + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('11', imm5) + + } + + @asm ror ?reg_D reg_M shift_n + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('11', imm5) + + } + + @asm rors ?reg_D reg_M shift_n + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ror_A88150.d b/plugins/arm/v7/opdefs/ror_A88150.d index c046bf7..57bbbb7 100644 --- a/plugins/arm/v7/opdefs/ror_A88150.d +++ b/plugins/arm/v7/opdefs/ror_A88150.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,29 @@ @title ROR (register) -@desc Rotate Right (register) provides the value of the contents of a register rotated by a variable number of bits. The bits that are rotated off the right end are inserted into the vacated bit positions on the left. The variable number of bits is read from the bottom byte of a register. It can optionally update the condition flags based on the result. +@id 149 + +@desc { + + Rotate Right (register) provides the value of the contents of a register rotated by a variable number of bits. The bits that are rotated off the right end are inserted into the vacated bit positions on the left. The variable number of bits is read from the bottom byte of a register. It can optionally update the condition flags based on the result. + +} @encoding (t1) { @half 0 1 0 0 0 0 0 1 1 1 Rm(3) Rdn(3) - @syntax "rors" <reg_DN> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rdn) + reg_N = Register(Rdn) + reg_M = Register(Rm) - reg_DN = Register(Rdn) - reg_M = Register(Rm) + } + + @asm ror ?reg_D reg_N reg_M } @@ -44,21 +55,43 @@ @word 1 1 1 1 1 0 1 0 0 1 1 S(1) Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @assert { + + S == 0 + + } - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm ror.w ?reg_D reg_N reg_M } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @asm rors.w ?reg_D reg_N reg_M } @@ -68,21 +101,55 @@ @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) Rm(4) 0 1 1 1 Rn(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @assert { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm ror ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm rors ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/rrx_A88151.d b/plugins/arm/v7/opdefs/rrx_A88151.d index 4debd42..d73570b 100644 --- a/plugins/arm/v7/opdefs/rrx_A88151.d +++ b/plugins/arm/v7/opdefs/rrx_A88151.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,25 +23,53 @@ @title RRX -@desc Rotate Right with Extend provides the value of the contents of a register shifted right by one place, with the Carry flag shifted into bit[31]. RRX can optionally update the condition flags based on the result. In that case, bit[0] is shifted into the Carry flag. +@id 150 + +@desc { + + Rotate Right with Extend provides the value of the contents of a register shifted right by one place, with the Carry flag shifted into bit[31]. RRX can optionally update the condition flags based on the result. In that case, bit[0] is shifted into the Carry flag. + +} @encoding (T1) { @word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 0 0 0 Rd(4) 0 0 1 1 Rm(4) - @syntax <reg_D> <reg_M> + @syntax { + + @assert { + + S == 0 + + } + + @conv { - @conv { + reg_D = Register(Rd) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') + } + + @asm rrx ?reg_D reg_M } - @rules { + @syntax { + + @assert { + + S == 1 + + } - if (setflags); chk_call ExtendKeyword("s") + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + + @asm rrxs ?reg_D reg_M } @@ -51,20 +79,53 @@ @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) 0 0 0 0 0 1 1 0 Rm(4) - @syntax <reg_D> <reg_M> + @syntax { + + @assert { - @conv { + S == 0 - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + + @asm rrx ?reg_D reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + + @asm rrxs ?reg_D reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/rsb_A88152.d b/plugins/arm/v7/opdefs/rsb_A88152.d index ea53373..0bf4eee 100644 --- a/plugins/arm/v7/opdefs/rsb_A88152.d +++ b/plugins/arm/v7/opdefs/rsb_A88152.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title RSB (immediate) -@desc Reverse Subtract (immediate) subtracts a register value from an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 151 + +@desc { + + Reverse Subtract (immediate) subtracts a register value from an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (t1) { @half 0 1 0 0 0 0 1 0 0 1 Rn(3) Rd(3) - @syntax "rsbs" <reg_D> <reg_N> <imm32> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = Zeros(32) - reg_D = Register(Rd) - reg_N = Register(Rn) - imm32 = Zeros(32) + } + + @asm rsb ?reg_D reg_N imm32 } @@ -45,21 +55,43 @@ @word 1 1 1 1 0 i(1) 0 1 1 1 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - @syntax <reg_D> <reg_N> <imm32> + @syntax { + + @assert { + + S == 0 + + } - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ThumbExpandImm(i:imm3:imm8) + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + + @asm rsb.w ?reg_D reg_N imm32 } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @asm rsbs.w ?reg_D reg_N imm32 } @@ -69,21 +101,55 @@ @word cond(4) 0 0 1 0 0 1 1 S(1) Rn(4) Rd(4) imm12(12) - @syntax <reg_D> <reg_N> <imm32> + @syntax { - @conv { + @assert { - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ARMExpandImm(imm12) + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ARMExpandImm(imm12) + + } + + @asm rsb ?reg_D reg_N imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ARMExpandImm(imm12) + + } + + @asm rsbs ?reg_D reg_N imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/rsb_A88153.d b/plugins/arm/v7/opdefs/rsb_A88153.d index f4a6d61..3f13bfa 100644 --- a/plugins/arm/v7/opdefs/rsb_A88153.d +++ b/plugins/arm/v7/opdefs/rsb_A88153.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,27 +23,57 @@ @title RSB (register) -@desc Reverse Subtract (register) subtracts a register value from an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 152 + +@desc { + + Reverse Subtract (register) subtracts a register value from an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (T1) { @word 1 1 1 0 1 0 1 1 1 1 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?shift> + @syntax { + + @assert { + + S == 0 + + } + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm3:imm2) + } + + @asm rsb ?reg_D reg_N reg_M ?shift } - @rules { + @syntax { + + @assert { + + S == 1 + + } - if (setflags); chk_call ExtendKeyword("s") + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm rsbs ?reg_D reg_N reg_M ?shift } @@ -53,22 +83,57 @@ @word cond(4) 0 0 0 0 0 1 1 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?shift> + @syntax { + + @assert { - @conv { + S == 0 - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm5) + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm rsb ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm rsbs ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/rsb_A88154.d b/plugins/arm/v7/opdefs/rsb_A88154.d index 9ccf559..74f084e 100644 --- a/plugins/arm/v7/opdefs/rsb_A88154.d +++ b/plugins/arm/v7/opdefs/rsb_A88154.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,28 +23,73 @@ @title RSB (register-shifted register) -@desc Reverse Subtract (register-shifted register) subtracts a register value from a register-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 153 + +@desc { + + Reverse Subtract (register-shifted register) subtracts a register value from a register-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (A1) { @word cond(4) 0 0 0 0 0 1 1 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <reg_shift> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm rsb ?reg_D reg_N reg_M shift - @conv { + @rules { - reg_shift = RegisterShift(type, Rs) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm rsbs ?reg_D reg_N reg_M shift + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/rsc_A88155.d b/plugins/arm/v7/opdefs/rsc_A88155.d index fc5f8b6..dd8954c 100644 --- a/plugins/arm/v7/opdefs/rsc_A88155.d +++ b/plugins/arm/v7/opdefs/rsc_A88155.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,27 +23,67 @@ @title RSC (immediate) -@desc Reverse Subtract with Carry (immediate) subtracts a register value and the value of NOT (Carry flag) from an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 154 + +@desc { + + Reverse Subtract with Carry (immediate) subtracts a register value and the value of NOT (Carry flag) from an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (A1) { @word cond(4) 0 0 1 0 1 1 1 S(1) Rn(4) Rd(4) imm12(12) - @syntax <reg_D> <reg_N> <imm32> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ARMExpandImm(imm12) + + } + + @asm rsc ?reg_D reg_N imm32 - @conv { + @rules { - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ARMExpandImm(imm12) + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ARMExpandImm(imm12) + + } + + @asm rscs ?reg_D reg_N imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/rsc_A88156.d b/plugins/arm/v7/opdefs/rsc_A88156.d index 70829cd..615aa99 100644 --- a/plugins/arm/v7/opdefs/rsc_A88156.d +++ b/plugins/arm/v7/opdefs/rsc_A88156.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,28 +23,69 @@ @title RSC (register) -@desc Reverse Subtract with Carry (register) subtracts a register value and the value of NOT (Carry flag) from an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 155 + +@desc { + + Reverse Subtract with Carry (register) subtracts a register value and the value of NOT (Carry flag) from an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (A1) { @word cond(4) 0 0 0 0 1 1 1 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?shift> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm rsc ?reg_D reg_N reg_M ?shift - @conv { + @rules { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm5) + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm rscs ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/rsc_A88157.d b/plugins/arm/v7/opdefs/rsc_A88157.d index 4fa276d..d95992b 100644 --- a/plugins/arm/v7/opdefs/rsc_A88157.d +++ b/plugins/arm/v7/opdefs/rsc_A88157.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,28 +23,73 @@ @title RSC (register-shifted register) -@desc Reverse Subtract (register-shifted register) subtracts a register value and the value of NOT (Carry flag) from a register-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 156 + +@desc { + + Reverse Subtract (register-shifted register) subtracts a register value and the value of NOT (Carry flag) from a register-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (A1) { @word cond(4) 0 0 0 0 1 1 1 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <reg_shift> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm rsc ?reg_D reg_N reg_M shift - @conv { + @rules { - reg_shift = RegisterShift(type, Rs) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm rscs ?reg_D reg_N reg_M shift + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/sadd16_A88158.d b/plugins/arm/v7/opdefs/sadd16_A88158.d index 51ad948..ee8d6d3 100644 --- a/plugins/arm/v7/opdefs/sadd16_A88158.d +++ b/plugins/arm/v7/opdefs/sadd16_A88158.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title SADD16 -@desc Signed Add 16 performs two 16-bit signed integer additions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the additions. +@id 157 + +@desc { + + Signed Add 16 performs two 16-bit signed integer additions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the additions. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 0 1 Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm sadd16 ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 0 0 1 Rn(4) Rd(4) 1 1 1 1 0 0 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm sadd16 ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/sadd8_A88159.d b/plugins/arm/v7/opdefs/sadd8_A88159.d index 463c968..6c6c4a6 100644 --- a/plugins/arm/v7/opdefs/sadd8_A88159.d +++ b/plugins/arm/v7/opdefs/sadd8_A88159.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title SADD8 -@desc Signed Add 8 performs four 8-bit signed integer additions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the additions. +@id 158 + +@desc { + + Signed Add 8 performs four 8-bit signed integer additions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the additions. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm sadd8 ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 0 0 1 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm sadd8 ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/sasx_A88160.d b/plugins/arm/v7/opdefs/sasx_A88160.d index a0529cb..d655002 100644 --- a/plugins/arm/v7/opdefs/sasx_A88160.d +++ b/plugins/arm/v7/opdefs/sasx_A88160.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title SASX -@desc Signed Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one 16-bit integer addition and one 16-bit subtraction, and writes the results to the destination register. It sets the APSR.GE bits according to the results. +@id 159 + +@desc { + + Signed Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one 16-bit integer addition and one 16-bit subtraction, and writes the results to the destination register. It sets the APSR.GE bits according to the results. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 1 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm sasx ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 0 0 1 Rn(4) Rd(4) 1 1 1 1 0 0 1 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm sasx ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/sbc_A88161.d b/plugins/arm/v7/opdefs/sbc_A88161.d index 4ea776a..d085e28 100644 --- a/plugins/arm/v7/opdefs/sbc_A88161.d +++ b/plugins/arm/v7/opdefs/sbc_A88161.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,26 +23,55 @@ @title SBC (immediate) -@desc Subtract with Carry (immediate) subtracts an immediate value and the value of NOT (Carry flag) from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 160 + +@desc { + + Subtract with Carry (immediate) subtracts an immediate value and the value of NOT (Carry flag) from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (T1) { @word 1 1 1 1 0 i(1) 0 1 0 1 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - @syntax <reg_D> <reg_N> <imm32> + @syntax { + + @assert { + + S == 0 + + } + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ThumbExpandImm(i:imm3:imm8) - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ThumbExpandImm(i:imm3:imm8) + } + + @asm sbc ?reg_D reg_N imm32 } - @rules { + @syntax { + + @assert { + + S == 1 + + } - if (setflags); chk_call ExtendKeyword("s") + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + + @asm sbcs ?reg_D reg_N imm32 } @@ -52,21 +81,55 @@ @word cond(4) 0 0 1 0 1 1 0 S(1) Rn(4) Rd(4) imm12(12) - @syntax <reg_D> <reg_N> <imm32> + @syntax { + + @assert { - @conv { + S == 0 - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ARMExpandImm(imm12) + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ARMExpandImm(imm12) + + } + + @asm sbc ?reg_D reg_N imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ARMExpandImm(imm12) + + } + + @asm sbcs ?reg_D reg_N imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/sbc_A88162.d b/plugins/arm/v7/opdefs/sbc_A88162.d index b6e660a..1ba7592 100644 --- a/plugins/arm/v7/opdefs/sbc_A88162.d +++ b/plugins/arm/v7/opdefs/sbc_A88162.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,29 @@ @title SBC (register) -@desc Subtract with Carry (register) subtracts an optionally-shifted register value and the value of NOT (Carry flag) from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 161 + +@desc { + + Subtract with Carry (register) subtracts an optionally-shifted register value and the value of NOT (Carry flag) from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (t1) { @half 0 1 0 0 0 0 0 1 1 0 Rm(3) Rdn(3) - @syntax "sbcs" <reg_DN> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rdn) + reg_N = Register(Rdn) + reg_M = Register(Rm) - reg_DN = Register(Rdn) - reg_M = Register(Rm) + } + + @asm sbc ?reg_D reg_N reg_M } @@ -44,22 +55,45 @@ @word 1 1 1 0 1 0 1 1 0 1 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?shift> + @syntax { + + @assert { + + S == 0 + + } - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm3:imm2) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm sbc.w ?reg_D reg_N reg_M ?shift } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @asm sbcs.w ?reg_D reg_N reg_M ?shift } @@ -69,22 +103,57 @@ @word cond(4) 0 0 0 0 1 1 0 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?shift> + @syntax { - @conv { + @assert { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm5) + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm sbc ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm sbcs ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/sbc_A88163.d b/plugins/arm/v7/opdefs/sbc_A88163.d index 0500edc..d534ed5 100644 --- a/plugins/arm/v7/opdefs/sbc_A88163.d +++ b/plugins/arm/v7/opdefs/sbc_A88163.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,28 +23,73 @@ @title SBC (register-shifted register) -@desc Subtract with Carry (register-shifted register) subtracts a register-shifted register value and the value of NOT (Carry flag) from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 162 + +@desc { + + Subtract with Carry (register-shifted register) subtracts a register-shifted register value and the value of NOT (Carry flag) from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (A1) { @word cond(4) 0 0 0 0 1 1 0 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <reg_shift> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm sbc ?reg_D reg_N reg_M shift - @conv { + @rules { - reg_shift = RegisterShift(type, Rs) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm sbcs ?reg_D reg_N reg_M shift + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/sbfx_A88164.d b/plugins/arm/v7/opdefs/sbfx_A88164.d index 486db3c..d834bca 100644 --- a/plugins/arm/v7/opdefs/sbfx_A88164.d +++ b/plugins/arm/v7/opdefs/sbfx_A88164.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,31 @@ @title SBFX -@desc Signed Bit Field Extract extracts any number of adjacent bits at any position from a register, sign-extends them to 32 bits, and writes the result to the destination register. +@id 163 + +@desc { + + Signed Bit Field Extract extracts any number of adjacent bits at any position from a register, sign-extends them to 32 bits, and writes the result to the destination register. + +} @encoding (T1) { @word 1 1 1 1 0 0 1 1 0 1 0 0 Rn(4) 0 imm3(3) Rd(4) imm2(2) 0 widthm1(5) - @syntax <reg_D> <reg_N> <lsbit> <width> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + lsbit = UInt(imm3:imm2) + widthminus1 = UInt(widthm1) + width = MinusBitDiff(widthminus1, lsbit) - reg_D = Register(Rd) - reg_N = Register(Rn) - lsbit = UInt(imm3:imm2) - width = IncWidth(widthm1) + } + + @asm sbfx reg_D reg_N lsbit width } @@ -46,20 +57,25 @@ @word cond(4) 0 1 1 1 1 0 1 widthm1(5) Rd(4) lsb(5) 1 0 1 Rn(4) - @syntax <reg_D> <reg_N> <lsbit> <width> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - lsbit = UInt(lsb) - width = IncWidth(widthm1) + reg_D = Register(Rd) + reg_N = Register(Rn) + lsbit = UInt(lsb) + widthminus1 = UInt(widthm1) + width = MinusBitDiff(widthminus1, lsbit) - } + } + + @asm sbfx reg_D reg_N lsbit width + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/sdiv_A88165.d b/plugins/arm/v7/opdefs/sdiv_A88165.d index 19ebfa9..762b49a 100644 --- a/plugins/arm/v7/opdefs/sdiv_A88165.d +++ b/plugins/arm/v7/opdefs/sdiv_A88165.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title SDIV -@desc Signed Divide divides a 32-bit signed integer register value by a 32-bit signed integer register value, and writes the result to the destination register. The condition flags are not affected. See ARMv7 implementation requirements and options for the divide instructions on page A4-172 for more information about this instruction. +@id 164 + +@desc { + + Signed Divide divides a 32-bit signed integer register value by a 32-bit signed integer register value, and writes the result to the destination register. The condition flags are not affected. See ARMv7 implementation requirements and options for the divide instructions on page A4-172 for more information about this instruction. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 1 1 0 0 1 Rn(4) 1 1 1 1 Rd(4) 1 1 1 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm sdiv ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 1 0 0 0 1 Rd(4) 1 1 1 1 Rm(4) 0 0 0 1 Rn(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm sdiv ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/sel_A88166.d b/plugins/arm/v7/opdefs/sel_A88166.d index cb32ed6..0239ee6 100644 --- a/plugins/arm/v7/opdefs/sel_A88166.d +++ b/plugins/arm/v7/opdefs/sel_A88166.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title SEL -@desc Select Bytes selects each byte of its result from either its first operand or its second operand, according to the values of the GE flags. +@id 165 + +@desc { + + Select Bytes selects each byte of its result from either its first operand or its second operand, according to the values of the GE flags. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 1 0 Rn(4) 1 1 1 1 Rd(4) 1 0 0 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm sel ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 1 0 0 0 Rn(4) Rd(4) 1 1 1 1 1 0 1 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm sel ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/setend_A88167.d b/plugins/arm/v7/opdefs/setend_A88167.d index e549c50..ee07bd9 100644 --- a/plugins/arm/v7/opdefs/setend_A88167.d +++ b/plugins/arm/v7/opdefs/setend_A88167.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,17 +23,27 @@ @title SETEND -@desc Set Endianness writes a new value to ENDIANSTATE. +@id 166 + +@desc { + + Set Endianness writes a new value to ENDIANSTATE. + +} @encoding (t1) { @half 1 0 1 1 0 1 1 0 0 1 0 1 E(1) 0 0 0 - @syntax <set_bigend> + @syntax { - @conv { + @conv { - set_bigend = EndianState(E == '1') + endian_specifier = Endian(E) + + } + + @asm setend endian_specifier } @@ -43,11 +53,15 @@ @word 1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 E(1) 0 0 0 0 0 0 0 0 0 - @syntax <set_bigend> + @syntax { + + @conv { + + endian_specifier = Endian(E) - @conv { + } - set_bigend = EndianState(E == '1') + @asm setend endian_specifier } diff --git a/plugins/arm/v7/opdefs/sev_A88168.d b/plugins/arm/v7/opdefs/sev_A88168.d index 2bd9af4..cfbebe0 100644 --- a/plugins/arm/v7/opdefs/sev_A88168.d +++ b/plugins/arm/v7/opdefs/sev_A88168.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,35 @@ @title SEV -@desc Send Event is a hint instruction. It causes an event to be signaled to all processors in the multiprocessor system. For more information, see Wait For Event and Send Event on page B1-1199. +@id 167 + +@desc { + + Send Event is a hint instruction. It causes an event to be signaled to all processors in the multiprocessor system. For more information, see Wait For Event and Send Event on page B1-1199. + +} @encoding (t1) { @half 1 0 1 1 1 1 1 1 0 1 0 0 0 0 0 0 + @syntax { + + @asm sev + + } + } @encoding (T2) { @word 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 - @syntax ".W" + @syntax { + + @asm sev.w + + } } @@ -43,9 +59,15 @@ @word cond(4) 0 0 1 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 - @rules { + @syntax { + + @asm sev + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/shadd16_A88169.d b/plugins/arm/v7/opdefs/shadd16_A88169.d index 22baa05..8453f4b 100644 --- a/plugins/arm/v7/opdefs/shadd16_A88169.d +++ b/plugins/arm/v7/opdefs/shadd16_A88169.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title SHADD16 -@desc Signed Halving Add 16 performs two signed 16-bit integer additions, halves the results, and writes the results to the destination register. +@id 168 + +@desc { + + Signed Halving Add 16 performs two signed 16-bit integer additions, halves the results, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 0 1 Rn(4) 1 1 1 1 Rd(4) 0 0 1 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm shadd16 ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 0 1 1 Rn(4) Rd(4) 1 1 1 1 0 0 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm shadd16 ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/shadd8_A88170.d b/plugins/arm/v7/opdefs/shadd8_A88170.d index bfc3031..8623ac9 100644 --- a/plugins/arm/v7/opdefs/shadd8_A88170.d +++ b/plugins/arm/v7/opdefs/shadd8_A88170.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title SHADD8 -@desc Signed Halving Add 8 performs four signed 8-bit integer additions, halves the results, and writes the results to the destination register. +@id 169 + +@desc { + + Signed Halving Add 8 performs four signed 8-bit integer additions, halves the results, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 0 0 1 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm shadd8 ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 0 1 1 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm shadd8 ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/shasx_A88171.d b/plugins/arm/v7/opdefs/shasx_A88171.d index 71d241b..9a931cb 100644 --- a/plugins/arm/v7/opdefs/shasx_A88171.d +++ b/plugins/arm/v7/opdefs/shasx_A88171.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title SHASX -@desc Signed Halving Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one signed 16-bit integer addition and one signed 16-bit subtraction, halves the results, and writes the results to the destination register. +@id 170 + +@desc { + + Signed Halving Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one signed 16-bit integer addition and one signed 16-bit subtraction, halves the results, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 1 0 Rn(4) 1 1 1 1 Rd(4) 0 0 1 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm shasx ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 0 1 1 Rn(4) Rd(4) 1 1 1 1 0 0 1 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm shasx ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/shsax_A88172.d b/plugins/arm/v7/opdefs/shsax_A88172.d index 8794738..69369d5 100644 --- a/plugins/arm/v7/opdefs/shsax_A88172.d +++ b/plugins/arm/v7/opdefs/shsax_A88172.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title SHSAX -@desc Signed Halving Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one signed 16-bit integer subtraction and one signed 16-bit addition, halves the results, and writes the results to the destination register. +@id 171 + +@desc { + + Signed Halving Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one signed 16-bit integer subtraction and one signed 16-bit addition, halves the results, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 1 1 0 Rn(4) 1 1 1 1 Rd(4) 0 0 1 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm shsax ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 0 1 1 Rn(4) Rd(4) 1 1 1 1 0 1 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm shsax ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/shsub16_A88173.d b/plugins/arm/v7/opdefs/shsub16_A88173.d index f7099f2..db35320 100644 --- a/plugins/arm/v7/opdefs/shsub16_A88173.d +++ b/plugins/arm/v7/opdefs/shsub16_A88173.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title SHSUB16 -@desc Signed Halving Subtract 16 performs two signed 16-bit integer subtractions, halves the results, and writes the results to the destination register. +@id 172 + +@desc { + + Signed Halving Subtract 16 performs two signed 16-bit integer subtractions, halves the results, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 1 0 1 Rn(4) 1 1 1 1 Rd(4) 0 0 1 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm shsub16 ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 0 1 1 Rn(4) Rd(4) 1 1 1 1 0 1 1 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm shsub16 ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/shsub8_A88174.d b/plugins/arm/v7/opdefs/shsub8_A88174.d index 99af65d..0d1b93c 100644 --- a/plugins/arm/v7/opdefs/shsub8_A88174.d +++ b/plugins/arm/v7/opdefs/shsub8_A88174.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title SHSUB8 -@desc Signed Halving Subtract 8 performs four signed 8-bit integer subtractions, halves the results, and writes the results to the destination register. +@id 173 + +@desc { + + Signed Halving Subtract 8 performs four signed 8-bit integer subtractions, halves the results, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 1 0 0 Rn(4) 1 1 1 1 Rd(4) 0 0 1 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm shsub8 ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 0 1 1 Rn(4) Rd(4) 1 1 1 1 1 1 1 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm shsub8 ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/smlad_A88177.d b/plugins/arm/v7/opdefs/smlad_A88177.d index 3eabaa9..da02029 100644 --- a/plugins/arm/v7/opdefs/smlad_A88177.d +++ b/plugins/arm/v7/opdefs/smlad_A88177.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,27 +23,57 @@ @title SMLAD -@desc Signed Multiply Accumulate Dual performs two signed 16 × 16-bit multiplications. It adds the products to a 32-bit accumulate operand. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. This instruction sets the Q flag if the accumulate operation overflows. Overflow cannot occur during the multiplications. +@id 176 + +@desc { + + Signed Multiply Accumulate Dual performs two signed 16 × 16-bit multiplications. It adds the products to a 32-bit accumulate operand. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. This instruction sets the Q flag if the accumulate operation overflows. Overflow cannot occur during the multiplications. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 1 0 0 1 0 Rn(4) Ra(4) Rd(4) 0 0 0 M(1) Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <reg_A> + @syntax { + + @assert { + + M == 0 + + } + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - m_swap = (M == '1') + } + + @asm smlad reg_D reg_N reg_M reg_A } - @rules { + @syntax { + + @assert { + + M == 1 + + } - if (m_swap); chk_call ExtendKeyword("x") + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smladx reg_D reg_N reg_M reg_A } @@ -53,22 +83,57 @@ @word cond(4) 0 1 1 1 0 0 0 0 Rd(4) Ra(4) Rm(4) 0 0 M(1) 1 Rn(4) - @syntax <reg_D> <reg_N> <reg_M> <reg_A> + @syntax { + + @assert { - @conv { + M == 0 - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - m_swap = (M == '1') + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smlad reg_D reg_N reg_M reg_A + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + M == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smladx reg_D reg_N reg_M reg_A + + @rules { + + check g_arm_instruction_set_cond(cond) - if (m_swap); chk_call ExtendKeyword("x") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/smlal_A88178.d b/plugins/arm/v7/opdefs/smlal_A88178.d index 03da53c..0b79de9 100644 --- a/plugins/arm/v7/opdefs/smlal_A88178.d +++ b/plugins/arm/v7/opdefs/smlal_A88178.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title SMLAL -@desc Signed Multiply Accumulate Long multiplies two signed 32-bit values to produce a 64-bit value, and accumulates this with a 64-bit value. In ARM instructions, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many processor implementations. +@id 177 + +@desc { + + Signed Multiply Accumulate Long multiplies two signed 32-bit values to produce a 64-bit value, and accumulates this with a 64-bit value. In ARM instructions, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many processor implementations. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 1 1 1 0 0 Rn(4) RdLo(4) RdHi(4) 0 0 0 0 Rm(4) - @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> + @syntax { + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) - @conv { + } - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) + @asm smlal reg_DLO reg_DHI reg_N reg_M } @@ -46,22 +56,57 @@ @word cond(4) 0 0 0 0 1 1 1 S(1) RdHi(4) RdLo(4) Rm(4) 1 0 0 1 Rn(4) - @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } - @conv { + @asm smlal reg_DLO reg_DHI reg_N reg_M - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smlals reg_DLO reg_DHI reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/smlald_A88180.d b/plugins/arm/v7/opdefs/smlald_A88180.d index fa6a473..16353d2 100644 --- a/plugins/arm/v7/opdefs/smlald_A88180.d +++ b/plugins/arm/v7/opdefs/smlald_A88180.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,27 +23,57 @@ @title SMLALD -@desc Signed Multiply Accumulate Long Dual performs two signed 16 × 16-bit multiplications. It adds the products to a 64-bit accumulate operand. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. Overflow is possible during this instruction, but only as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo 264. +@id 179 + +@desc { + + Signed Multiply Accumulate Long Dual performs two signed 16 × 16-bit multiplications. It adds the products to a 64-bit accumulate operand. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. Overflow is possible during this instruction, but only as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo 264. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 1 1 1 0 0 Rn(4) RdLo(4) RdHi(4) 1 1 0 M(1) Rm(4) - @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> + @syntax { + + @assert { + + M == 0 + + } + + @conv { - @conv { + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - m_swap = (M == '1') + } + + @asm smlald reg_DLO reg_DHI reg_N reg_M } - @rules { + @syntax { + + @assert { + + M == 1 + + } - if (m_swap); chk_call ExtendKeyword("x") + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smlaldx reg_DLO reg_DHI reg_N reg_M } @@ -53,22 +83,57 @@ @word cond(4) 0 1 1 1 0 1 0 0 RdHi(4) RdLo(4) Rm(4) 0 0 M(1) 1 Rn(4) - @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> + @syntax { + + @assert { - @conv { + M == 0 - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - m_swap = (M == '1') + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smlald reg_DLO reg_DHI reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + M == 1 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smlaldx reg_DLO reg_DHI reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) - if (m_swap); chk_call ExtendKeyword("x") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/smlsd_A88182.d b/plugins/arm/v7/opdefs/smlsd_A88182.d index d458fa8..5808518 100644 --- a/plugins/arm/v7/opdefs/smlsd_A88182.d +++ b/plugins/arm/v7/opdefs/smlsd_A88182.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,27 +23,57 @@ @title SMLSD -@desc Signed Multiply Subtract Dual performs two signed 16 × 16-bit multiplications. It adds the difference of the products to a 32-bit accumulate operand. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. This instruction sets the Q flag if the accumulate operation overflows. Overflow cannot occur during the multiplications or subtraction. +@id 181 + +@desc { + + Signed Multiply Subtract Dual performs two signed 16 × 16-bit multiplications. It adds the difference of the products to a 32-bit accumulate operand. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. This instruction sets the Q flag if the accumulate operation overflows. Overflow cannot occur during the multiplications or subtraction. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 1 0 1 0 0 Rn(4) Ra(4) Rd(4) 0 0 0 M(1) Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <reg_A> + @syntax { + + @assert { + + M == 0 + + } + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - m_swap = (M == '1') + } + + @asm smlsd reg_D reg_N reg_M reg_A } - @rules { + @syntax { + + @assert { + + M == 1 + + } - if (m_swap); chk_call ExtendKeyword("x") + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smlsdx reg_D reg_N reg_M reg_A } @@ -53,22 +83,57 @@ @word cond(4) 0 1 1 1 0 0 0 0 Rd(4) Ra(4) Rm(4) 0 1 M(1) 1 Rn(4) - @syntax <reg_D> <reg_N> <reg_M> <reg_A> + @syntax { + + @assert { - @conv { + M == 0 - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - m_swap = (M == '1') + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smlsd reg_D reg_N reg_M reg_A + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + M == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smlsdx reg_D reg_N reg_M reg_A + + @rules { + + check g_arm_instruction_set_cond(cond) - if (m_swap); chk_call ExtendKeyword("x") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/smlsld_A88183.d b/plugins/arm/v7/opdefs/smlsld_A88183.d index 9f64eed..995fb6f 100644 --- a/plugins/arm/v7/opdefs/smlsld_A88183.d +++ b/plugins/arm/v7/opdefs/smlsld_A88183.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,27 +23,57 @@ @title SMLSLD -@desc Signed Multiply Subtract Long Dual performs two signed 16 × 16-bit multiplications. It adds the difference of the products to a 64-bit accumulate operand. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. Overflow is possible during this instruction, but only as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo 264. +@id 182 + +@desc { + + Signed Multiply Subtract Long Dual performs two signed 16 × 16-bit multiplications. It adds the difference of the products to a 64-bit accumulate operand. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. Overflow is possible during this instruction, but only as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo 264. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 1 1 1 0 1 Rn(4) RdLo(4) RdHi(4) 1 1 0 M(1) Rm(4) - @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> + @syntax { + + @assert { + + M == 0 + + } + + @conv { - @conv { + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - m_swap = (M == '1') + } + + @asm smlsld reg_DLO reg_DHI reg_N reg_M } - @rules { + @syntax { + + @assert { + + M == 1 + + } - if (m_swap); chk_call ExtendKeyword("x") + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smlsldx reg_DLO reg_DHI reg_N reg_M } @@ -53,22 +83,57 @@ @word cond(4) 0 1 1 1 0 1 0 0 RdHi(4) RdLo(4) Rm(4) 0 1 M(1) 1 Rn(4) - @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> + @syntax { + + @assert { - @conv { + M == 0 - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - m_swap = (M == '1') + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smlsld reg_DLO reg_DHI reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + M == 1 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smlsldx reg_DLO reg_DHI reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) - if (m_swap); chk_call ExtendKeyword("x") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/smmla_A88184.d b/plugins/arm/v7/opdefs/smmla_A88184.d index a4d29b8..40bd005 100644 --- a/plugins/arm/v7/opdefs/smmla_A88184.d +++ b/plugins/arm/v7/opdefs/smmla_A88184.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,27 +23,57 @@ @title SMMLA -@desc Signed Most Significant Word Multiply Accumulate multiplies two signed 32-bit values, extracts the most significant 32 bits of the result, and adds an accumulate value. Optionally, the instruction can specify that the result is rounded instead of being truncated. In this case, the constant 0x80000000 is added to the product before the high word is extracted. +@id 183 + +@desc { + + Signed Most Significant Word Multiply Accumulate multiplies two signed 32-bit values, extracts the most significant 32 bits of the result, and adds an accumulate value. Optionally, the instruction can specify that the result is rounded instead of being truncated. In this case, the constant 0x80000000 is added to the product before the high word is extracted. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 1 0 1 0 1 Rn(4) Ra(4) Rd(4) 0 0 0 R(1) Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <reg_A> + @syntax { + + @assert { + + R == 0 + + } + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - round = (R == '1') + } + + @asm smmla reg_D reg_N reg_M reg_A } - @rules { + @syntax { + + @assert { + + R == 1 + + } - if (round); chk_call ExtendKeyword("r") + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smmlar reg_D reg_N reg_M reg_A } @@ -53,22 +83,57 @@ @word cond(4) 0 1 1 1 0 1 0 1 Rd(4) Ra(4) Rm(4) 0 0 R(1) 1 Rn(4) - @syntax <reg_D> <reg_N> <reg_M> <reg_A> + @syntax { + + @assert { - @conv { + R == 0 - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - round = (R == '1') + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smmla reg_D reg_N reg_M reg_A + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + R == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smmlar reg_D reg_N reg_M reg_A + + @rules { + + check g_arm_instruction_set_cond(cond) - if (round); chk_call ExtendKeyword("r") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/smmls_A88185.d b/plugins/arm/v7/opdefs/smmls_A88185.d index d59617b..9bc5396 100644 --- a/plugins/arm/v7/opdefs/smmls_A88185.d +++ b/plugins/arm/v7/opdefs/smmls_A88185.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,27 +23,57 @@ @title SMMLS -@desc Signed Most Significant Word Multiply Subtract multiplies two signed 32-bit values, subtracts the result from a 32-bit accumulate value that is shifted left by 32 bits, and extracts the most significant 32 bits of the result of that subtraction. Optionally, the instruction can specify that the result of the instruction is rounded instead of being truncated. In this case, the constant 0x80000000 is added to the result of the subtraction before the high word is extracted. +@id 184 + +@desc { + + Signed Most Significant Word Multiply Subtract multiplies two signed 32-bit values, subtracts the result from a 32-bit accumulate value that is shifted left by 32 bits, and extracts the most significant 32 bits of the result of that subtraction. Optionally, the instruction can specify that the result of the instruction is rounded instead of being truncated. In this case, the constant 0x80000000 is added to the result of the subtraction before the high word is extracted. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 1 0 1 1 0 Rn(4) Ra(4) Rd(4) 0 0 0 R(1) Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <reg_A> + @syntax { + + @assert { + + R == 0 + + } + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - round = (R == '1') + } + + @asm smmls reg_D reg_N reg_M reg_A } - @rules { + @syntax { + + @assert { + + R == 1 + + } - if (round); chk_call ExtendKeyword("r") + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smmlsr reg_D reg_N reg_M reg_A } @@ -53,22 +83,57 @@ @word cond(4) 0 1 1 1 0 1 0 1 Rd(4) Ra(4) Rm(4) 1 1 R(1) 1 Rn(4) - @syntax <reg_D> <reg_N> <reg_M> <reg_A> + @syntax { + + @assert { - @conv { + R == 0 - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - round = (R == '1') + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smmls reg_D reg_N reg_M reg_A + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + R == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smmlsr reg_D reg_N reg_M reg_A + + @rules { + + check g_arm_instruction_set_cond(cond) - if (round); chk_call ExtendKeyword("r") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/smmul_A88186.d b/plugins/arm/v7/opdefs/smmul_A88186.d index e02ca52..44a8b9b 100644 --- a/plugins/arm/v7/opdefs/smmul_A88186.d +++ b/plugins/arm/v7/opdefs/smmul_A88186.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,26 +23,55 @@ @title SMMUL -@desc Signed Most Significant Word Multiply multiplies two signed 32-bit values, extracts the most significant 32 bits of the result, and writes those bits to the destination register. Optionally, the instruction can specify that the result is rounded instead of being truncated. In this case, the constant 0x80000000 is added to the product before the high word is extracted. +@id 185 + +@desc { + + Signed Most Significant Word Multiply multiplies two signed 32-bit values, extracts the most significant 32 bits of the result, and writes those bits to the destination register. Optionally, the instruction can specify that the result is rounded instead of being truncated. In this case, the constant 0x80000000 is added to the product before the high word is extracted. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 1 0 1 0 1 Rn(4) 1 1 1 1 Rd(4) 0 0 0 R(1) Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @assert { + + R == 0 + + } + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - round = (R == '1') + } + + @asm smmul ?reg_D reg_N reg_M } - @rules { + @syntax { + + @assert { + + R == 1 + + } - if (round); chk_call ExtendKeyword("r") + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smmulr ?reg_D reg_N reg_M } @@ -52,21 +81,55 @@ @word cond(4) 0 1 1 1 0 1 0 1 Rd(4) 1 1 1 1 Rm(4) 0 0 R(1) 1 Rn(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @assert { - @conv { + R == 0 - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - round = (R == '1') + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smmul ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + R == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smmulr ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) - if (round); chk_call ExtendKeyword("r") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/smuad_A88187.d b/plugins/arm/v7/opdefs/smuad_A88187.d index 324e257..a10c279 100644 --- a/plugins/arm/v7/opdefs/smuad_A88187.d +++ b/plugins/arm/v7/opdefs/smuad_A88187.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,26 +23,55 @@ @title SMUAD -@desc Signed Dual Multiply Add performs two signed 16 × 16-bit multiplications. It adds the products together, and writes the result to the destination register. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. This instruction sets the Q flag if the addition overflows. The multiplications cannot overflow. +@id 186 + +@desc { + + Signed Dual Multiply Add performs two signed 16 × 16-bit multiplications. It adds the products together, and writes the result to the destination register. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. This instruction sets the Q flag if the addition overflows. The multiplications cannot overflow. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 1 0 0 1 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 M(1) Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @assert { + + M == 0 + + } + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - m_swap = (M == '1') + } + + @asm smuad ?reg_D reg_N reg_M } - @rules { + @syntax { + + @assert { + + M == 1 + + } - if (m_swap); chk_call ExtendKeyword("x") + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smuadx ?reg_D reg_N reg_M } @@ -52,21 +81,55 @@ @word cond(4) 0 1 1 1 0 0 0 0 Rd(4) 1 1 1 1 Rm(4) 0 0 M(1) 1 Rn(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @assert { - @conv { + M == 0 - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - m_swap = (M == '1') + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smuad ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + M == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smuadx ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) - if (m_swap); chk_call ExtendKeyword("x") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/smull_A88189.d b/plugins/arm/v7/opdefs/smull_A88189.d index 5ab1c54..c0a186e 100644 --- a/plugins/arm/v7/opdefs/smull_A88189.d +++ b/plugins/arm/v7/opdefs/smull_A88189.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title SMULL -@desc Signed Multiply Long multiplies two 32-bit signed values to produce a 64-bit result. In ARM instructions, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many processor implementations. +@id 188 + +@desc { + + Signed Multiply Long multiplies two 32-bit signed values to produce a 64-bit result. In ARM instructions, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many processor implementations. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 1 1 0 0 0 Rn(4) RdLo(4) RdHi(4) 0 0 0 0 Rm(4) - @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> + @syntax { + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) - @conv { + } - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) + @asm smull reg_DLO reg_DHI reg_N reg_M } @@ -46,22 +56,57 @@ @word cond(4) 0 0 0 0 1 1 0 S(1) RdHi(4) RdLo(4) Rm(4) 1 0 0 1 Rn(4) - @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } - @conv { + @asm smull reg_DLO reg_DHI reg_N reg_M - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smulls reg_DLO reg_DHI reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/str_A88203.d b/plugins/arm/v7/opdefs/str_A88203.d index e3feaf7..f8b4958 100644 --- a/plugins/arm/v7/opdefs/str_A88203.d +++ b/plugins/arm/v7/opdefs/str_A88203.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title STR (immediate, Thumb) -@desc Store Register (immediate) calculates an address from a base register value and an immediate offset, and stores a word from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. +@id 202 + +@desc { + + Store Register (immediate) calculates an address from a base register value and an immediate offset, and stores a word from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (t1) { @half 0 1 1 0 0 imm5(5) Rn(3) Rt(3) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm5:'00', 32) + maccess = MemAccessOffset(reg_N, imm32) - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm5:'00', 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + } + + @asm str reg_T maccess } @@ -46,14 +56,18 @@ @half 1 0 0 1 0 Rt(3) imm8(8) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(13) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessOffset(reg_N, imm32) - reg_T = Register(Rt) - imm32 = ZeroExtend(imm8:'00', 32) - SP = Register(13) - mem_access = MakeMemoryAccess(SP, imm32, NULL, true, true, false) + } + + @asm str reg_T maccess } @@ -63,14 +77,18 @@ @word 1 1 1 1 1 0 0 0 1 1 0 0 Rn(4) Rt(4) imm12(12) - @syntax ".W" <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessOffset(reg_N, imm32) - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + } + + @asm str.w reg_T maccess } @@ -80,17 +98,69 @@ @word 1 1 1 1 1 0 0 0 0 1 0 0 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) - @syntax <reg_T> <mem_access> + @syntax { + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm str reg_T maccess + + } + + @syntax { + + @assert { + + P == 1 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm str reg_T maccess + + } + + @syntax { + + @assert { + + P == 0 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - index = (P == '1') - add = (U == '1') - wback = (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + @asm str reg_T maccess } diff --git a/plugins/arm/v7/opdefs/str_A88204.d b/plugins/arm/v7/opdefs/str_A88204.d index d780ae3..0818631 100644 --- a/plugins/arm/v7/opdefs/str_A88204.d +++ b/plugins/arm/v7/opdefs/str_A88204.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,29 +23,99 @@ @title STR (immediate, ARM) -@desc Store Register (immediate) calculates an address from a base register value and an immediate offset, and stores a word from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. +@id 203 + +@desc { + + Store Register (immediate) calculates an address from a base register value and an immediate offset, and stores a word from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (A1) { @word cond(4) 0 1 0 P(1) U(1) 0 W(1) 0 Rn(4) Rt(4) imm12(12) - @syntax <reg_T> <mem_access> + @syntax { + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm str reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { - @conv { + @assert { - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm str reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm str reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/str_A88205.d b/plugins/arm/v7/opdefs/str_A88205.d index 55f154c..e4eb6fb 100644 --- a/plugins/arm/v7/opdefs/str_A88205.d +++ b/plugins/arm/v7/opdefs/str_A88205.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title STR (register) -@desc Store Register (register) calculates an address from a base register value and an offset register value, stores a word from a register to memory. The offset register value can optionally be shifted. For information about memory accesses see Memory accesses on page A8-294. +@id 204 + +@desc { + + Store Register (register) calculates an address from a base register value and an offset register value, stores a word from a register to memory. The offset register value can optionally be shifted. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (t1) { @half 0 1 0 1 0 0 0 Rm(3) Rn(3) Rt(3) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessOffset(reg_N, reg_M) - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, true, true, false) + } + + @asm str reg_T maccess } @@ -46,15 +56,19 @@ @word 1 1 1 1 1 0 0 0 0 1 0 0 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) - @syntax ".W" <reg_T> <mem_access> + @syntax { + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = FixedShift(SRType_LSL, imm2) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(0, imm2) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, true, true, false) + @asm str.w reg_T maccess } @@ -64,24 +78,90 @@ @word cond(4) 0 1 1 P(1) U(1) 0 W(1) 0 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) - @syntax <reg_T> <mem_access> + @syntax { + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) + + } + + @asm str reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @assert { + + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessPreIndexedExtended(reg_N, reg_M, shift) + + } + + @asm str reg_T maccess + + @rules { - @conv { + check g_arm_instruction_set_cond(cond) - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - shift = DecodeImmShift(type, imm5) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, index, add, wback) + } } - @rules { + @syntax { + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessPostIndexedExtended(reg_N, reg_M, shift) + + } + + @asm str reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/strb_A88206.d b/plugins/arm/v7/opdefs/strb_A88206.d index 2caf94c..ed21cc9 100644 --- a/plugins/arm/v7/opdefs/strb_A88206.d +++ b/plugins/arm/v7/opdefs/strb_A88206.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title STRB (immediate, Thumb) -@desc Store Register Byte (immediate) calculates an address from a base register value and an immediate offset, and stores a byte from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. +@id 205 + +@desc { + + Store Register Byte (immediate) calculates an address from a base register value and an immediate offset, and stores a byte from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (t1) { @half 0 1 1 1 0 imm5(5) Rn(3) Rt(3) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm5, 32) + maccess = MemAccessOffset(reg_N, imm32) - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm5, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + } + + @asm strb reg_T maccess } @@ -46,14 +56,18 @@ @word 1 1 1 1 1 0 0 0 1 0 0 0 Rn(4) Rt(4) imm12(12) - @syntax ".W" <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessOffset(reg_N, imm32) - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + } + + @asm strb.w reg_T maccess } @@ -63,17 +77,69 @@ @word 1 1 1 1 1 0 0 0 0 0 0 0 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) - @syntax <reg_T> <mem_access> + @syntax { + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm strb reg_T maccess + + } + + @syntax { + + @assert { + + P == 1 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm strb reg_T maccess + + } + + @syntax { + + @assert { + + P == 0 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - index = (P == '1') - add = (U == '1') - wback = (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + @asm strb reg_T maccess } diff --git a/plugins/arm/v7/opdefs/strb_A88207.d b/plugins/arm/v7/opdefs/strb_A88207.d index 4e893fb..e495ea8 100644 --- a/plugins/arm/v7/opdefs/strb_A88207.d +++ b/plugins/arm/v7/opdefs/strb_A88207.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,29 +23,99 @@ @title STRB (immediate, ARM) -@desc Store Register Byte (immediate) calculates an address from a base register value and an immediate offset, and stores a byte from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. +@id 206 + +@desc { + + Store Register Byte (immediate) calculates an address from a base register value and an immediate offset, and stores a byte from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (A1) { @word cond(4) 0 1 0 P(1) U(1) 1 W(1) 0 Rn(4) Rt(4) imm12(12) - @syntax <reg_T> <mem_access> + @syntax { + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm strb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { - @conv { + @assert { - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm strb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm strb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/strb_A88208.d b/plugins/arm/v7/opdefs/strb_A88208.d index 36f6134..11d5931 100644 --- a/plugins/arm/v7/opdefs/strb_A88208.d +++ b/plugins/arm/v7/opdefs/strb_A88208.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title STRB (register) -@desc Store Register Byte (register) calculates an address from a base register value and an offset register value, and stores a byte from a register to memory. The offset register value can optionally be shifted. For information about memory accesses see Memory accesses on page A8-294. +@id 207 + +@desc { + + Store Register Byte (register) calculates an address from a base register value and an offset register value, and stores a byte from a register to memory. The offset register value can optionally be shifted. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (t1) { @half 0 1 0 1 0 1 0 Rm(3) Rn(3) Rt(3) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessOffset(reg_N, reg_M) - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, true, true, false) + } + + @asm strb reg_T maccess } @@ -46,15 +56,19 @@ @word 1 1 1 1 1 0 0 0 0 0 0 0 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) - @syntax ".W" <reg_T> <mem_access> + @syntax { + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = FixedShift(SRType_LSL, imm2) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(0, imm2) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, true, true, false) + @asm strb.w reg_T maccess } @@ -64,24 +78,90 @@ @word cond(4) 0 1 1 P(1) U(1) 1 W(1) 0 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) - @syntax <reg_T> <mem_access> + @syntax { + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) + + } + + @asm strb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @assert { + + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessPreIndexedExtended(reg_N, reg_M, shift) + + } + + @asm strb reg_T maccess + + @rules { - @conv { + check g_arm_instruction_set_cond(cond) - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - shift = DecodeImmShift(type, imm5) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, index, add, wback) + } } - @rules { + @syntax { + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessPostIndexedExtended(reg_N, reg_M, shift) + + } + + @asm strb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/strbt_A88209.d b/plugins/arm/v7/opdefs/strbt_A88209.d index 2bcb260..034b4ad 100644 --- a/plugins/arm/v7/opdefs/strbt_A88209.d +++ b/plugins/arm/v7/opdefs/strbt_A88209.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title STRBT -@desc Store Register Byte Unprivileged stores a byte from a register to memory. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. STRBT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or an optionally-shifted register value. +@id 208 + +@desc { + + Store Register Byte Unprivileged stores a byte from a register to memory. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. STRBT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or an optionally-shifted register value. + +} @encoding (T1) { @word 1 1 1 1 1 0 0 0 0 0 0 0 Rn(4) Rt(4) 1 1 1 0 imm8(8) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + @asm strbt reg_T maccess } @@ -46,21 +56,24 @@ @word cond(4) 0 1 0 0 U(1) 1 1 0 Rn(4) Rt(4) imm12(12) - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_N = Register(Rn) - add = (U == '1') - imm32 = ZeroExtend(imm12, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, false, add, false) + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) - } + } + + @asm strbt reg_T maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } @@ -70,22 +83,25 @@ @word cond(4) 0 1 1 0 U(1) 1 1 0 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - add = (U == '1') - shift = DecodeImmShift(type, imm5) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, false, add, false) + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessPostIndexedExtended(reg_N, reg_M, shift) - } + } + + @asm strbt reg_T maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/strd_A88210.d b/plugins/arm/v7/opdefs/strd_A88210.d index 437bcb3..93608eb 100644 --- a/plugins/arm/v7/opdefs/strd_A88210.d +++ b/plugins/arm/v7/opdefs/strd_A88210.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,24 +23,84 @@ @title STRD (immediate) -@desc Store Register Dual (immediate) calculates an address from a base register value and an immediate offset, and stores two words from two registers to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. +@id 209 + +@desc { + + Store Register Dual (immediate) calculates an address from a base register value and an immediate offset, and stores two words from two registers to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (T1) { @word 1 1 1 0 1 0 0 P(1) U(1) 1 W(1) 0 Rn(4) Rt(4) Rt2(4) imm8(8) - @syntax <reg_T> <reg_T2> <mem_access> + @syntax { + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm strd reg_T reg_T2 maccess + + } + + @syntax { + + @assert { - @conv { + P == 1 + W == 1 - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8:'00', 32) - index = (P == '1') - add = (U == '1') - wback = (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm strd reg_T reg_T2 maccess + + } + + @syntax { + + @assert { + + P == 0 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm strd reg_T reg_T2 maccess } @@ -50,24 +110,90 @@ @word cond(4) 0 0 0 P(1) U(1) 1 W(1) 0 Rn(4) Rt(4) imm4H(4) 1 1 1 1 imm4L(4) - @syntax <reg_T> <reg_T2> <mem_access> + @syntax { + + @assert { - @conv { + P == 1 + P == 1 && W == 0 - reg_T = Register(Rt) - reg_T2 = NextRegister(reg_T) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm4H:imm4L, 32) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = NextRegister(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm strd reg_T reg_T2 maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = NextRegister(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm strd reg_T reg_T2 maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = NextRegister(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm strd reg_T reg_T2 maccess + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/strd_A88211.d b/plugins/arm/v7/opdefs/strd_A88211.d index b30d4a5..1f0dc14 100644 --- a/plugins/arm/v7/opdefs/strd_A88211.d +++ b/plugins/arm/v7/opdefs/strd_A88211.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,30 +23,102 @@ @title STRD (register) -@desc Store Register Dual (register) calculates an address from a base register value and a register offset, and stores two words from two registers to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. +@id 210 + +@desc { + + Store Register Dual (register) calculates an address from a base register value and a register offset, and stores two words from two registers to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (A1) { @word cond(4) 0 0 0 P(1) U(1) 0 W(1) 0 Rn(4) Rt(4) 0 0 0 0 1 1 1 1 Rm(4) - @syntax <reg_T> <reg_T2> <mem_access> + @syntax { + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = NextRegister(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessOffset(reg_N, reg_M) + + } + + @asm strd reg_T reg_T2 maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { - @conv { + @assert { - reg_T = Register(Rt) - reg_T2 = NextRegister(reg_T) - reg_N = Register(Rn) - reg_M = Register(Rm) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, index, add, wback) + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = NextRegister(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPreIndexed(reg_N, reg_M) + + } + + @asm strd reg_T reg_T2 maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = NextRegister(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(reg_N, reg_M) + + } + + @asm strd reg_T reg_T2 maccess + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/strex_A88212.d b/plugins/arm/v7/opdefs/strex_A88212.d index 65a7dfe..0631064 100644 --- a/plugins/arm/v7/opdefs/strex_A88212.d +++ b/plugins/arm/v7/opdefs/strex_A88212.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,21 +23,31 @@ @title STREX -@desc Store Register Exclusive calculates an address from a base register value and an immediate offset, and stores a word from a register to memory if the executing processor has exclusive access to the memory addressed. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. +@id 211 + +@desc { + + Store Register Exclusive calculates an address from a base register value and an immediate offset, and stores a word from a register to memory if the executing processor has exclusive access to the memory addressed. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (T1) { @word 1 1 1 0 1 0 0 0 0 1 0 0 Rn(4) Rt(4) Rd(4) imm8(8) - @syntax <reg_D> <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessOffset(reg_N, imm32) - reg_D = Register(Rd) - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8:'00', 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, false, false) + } + + @asm strex reg_D reg_T maccess } @@ -47,20 +57,25 @@ @word cond(4) 0 0 0 1 1 0 0 0 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rt(4) - @syntax <reg_D> <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_T = Register(Rt) - reg_N = Register(Rn) - mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + reg_D = Register(Rd) + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = Zeros(32) + maccess = MemAccessOffset(reg_N, imm32) - } + } + + @asm strex reg_D reg_T maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/strexb_A88213.d b/plugins/arm/v7/opdefs/strexb_A88213.d index 0197d6c..af0a005 100644 --- a/plugins/arm/v7/opdefs/strexb_A88213.d +++ b/plugins/arm/v7/opdefs/strexb_A88213.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title STREXB -@desc Store Register Exclusive Byte derives an address from a base register value, and stores a byte from a register to memory if the executing processor has exclusive access to the memory addressed. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. +@id 212 + +@desc { + + Store Register Exclusive Byte derives an address from a base register value, and stores a byte from a register to memory if the executing processor has exclusive access to the memory addressed. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (T1) { @word 1 1 1 0 1 0 0 0 1 1 0 0 Rn(4) Rt(4) 1 1 1 1 0 1 0 0 Rd(4) - @syntax <reg_D> <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_T = Register(Rt) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) - reg_D = Register(Rd) - reg_T = Register(Rt) - reg_N = Register(Rn) - mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + } + + @asm strexb reg_D reg_T maccess } @@ -46,20 +56,24 @@ @word cond(4) 0 0 0 1 1 1 0 0 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rt(4) - @syntax <reg_D> <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_T = Register(Rt) - reg_N = Register(Rn) - mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + reg_D = Register(Rd) + reg_T = Register(Rt) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) - } + } + + @asm strexb reg_D reg_T maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/strexd_A88214.d b/plugins/arm/v7/opdefs/strexd_A88214.d index 2867cea..3da8f64 100644 --- a/plugins/arm/v7/opdefs/strexd_A88214.d +++ b/plugins/arm/v7/opdefs/strexd_A88214.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,21 +23,31 @@ @title STREXD -@desc Store Register Exclusive Doubleword derives an address from a base register value, and stores a 64-bit doubleword from two registers to memory if the executing processor has exclusive access to the memory addressed. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. +@id 213 + +@desc { + + Store Register Exclusive Doubleword derives an address from a base register value, and stores a 64-bit doubleword from two registers to memory if the executing processor has exclusive access to the memory addressed. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (T1) { @word 1 1 1 0 1 0 0 0 1 1 0 0 Rn(4) Rt(4) Rt2(4) 0 1 1 1 Rd(4) - @syntax <reg_D> <reg_T> <reg_T2> <mem_access> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) - reg_D = Register(Rd) - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - reg_N = Register(Rn) - mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + } + + @asm strexd reg_D reg_T reg_T2 maccess } @@ -47,21 +57,25 @@ @word cond(4) 0 0 0 1 1 0 1 0 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rt(4) - @syntax <reg_D> <reg_T> <reg_T2> <mem_access> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_T = Register(Rt) - reg_T2 = NextRegister(reg_T) - reg_N = Register(Rn) - mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + reg_D = Register(Rd) + reg_T = Register(Rt) + reg_T2 = NextRegister(Rt) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) - } + } + + @asm strexd reg_D reg_T reg_T2 maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/strexh_A88215.d b/plugins/arm/v7/opdefs/strexh_A88215.d index 4ca0b6f..4341851 100644 --- a/plugins/arm/v7/opdefs/strexh_A88215.d +++ b/plugins/arm/v7/opdefs/strexh_A88215.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title STREXH -@desc Store Register Exclusive Halfword derives an address from a base register value, and stores a halfword from a register to memory if the executing processor has exclusive access to the memory addressed. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. +@id 214 + +@desc { + + Store Register Exclusive Halfword derives an address from a base register value, and stores a halfword from a register to memory if the executing processor has exclusive access to the memory addressed. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (T1) { @word 1 1 1 0 1 0 0 0 1 1 0 0 Rn(4) Rt(4) 1 1 1 1 0 1 0 1 Rd(4) - @syntax <reg_D> <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_T = Register(Rt) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) - reg_D = Register(Rd) - reg_T = Register(Rt) - reg_N = Register(Rn) - mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + } + + @asm strexh reg_D reg_T maccess } @@ -46,20 +56,24 @@ @word cond(4) 0 0 0 1 1 1 1 0 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rt(4) - @syntax <reg_D> <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_T = Register(Rt) - reg_N = Register(Rn) - mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + reg_D = Register(Rd) + reg_T = Register(Rt) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) - } + } + + @asm strexh reg_D reg_T maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/strh_A88216.d b/plugins/arm/v7/opdefs/strh_A88216.d index 624b483..05b7b12 100644 --- a/plugins/arm/v7/opdefs/strh_A88216.d +++ b/plugins/arm/v7/opdefs/strh_A88216.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title STRH (immediate, Thumb) -@desc Store Register Halfword (immediate) calculates an address from a base register value and an immediate offset, and stores a halfword from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. +@id 215 + +@desc { + + Store Register Halfword (immediate) calculates an address from a base register value and an immediate offset, and stores a halfword from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (t1) { @half 1 0 0 0 0 imm5(5) Rn(3) Rt(3) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm5:'0', 32) + maccess = MemAccessOffset(reg_N, imm32) - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm5:'0', 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + } + + @asm strh reg_T maccess } @@ -46,14 +56,18 @@ @word 1 1 1 1 1 0 0 0 1 0 1 0 Rn(4) Rt(4) imm12(12) - @syntax ".W" <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessOffset(reg_N, imm32) - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + } + + @asm strh.w reg_T maccess } @@ -63,17 +77,69 @@ @word 1 1 1 1 1 0 0 0 0 0 1 0 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) - @syntax <reg_T> <mem_access> + @syntax { + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm strh reg_T maccess + + } + + @syntax { + + @assert { + + P == 1 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm strh reg_T maccess + + } + + @syntax { + + @assert { + + P == 0 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - index = (P == '1') - add = (U == '1') - wback = (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + @asm strh reg_T maccess } diff --git a/plugins/arm/v7/opdefs/strh_A88217.d b/plugins/arm/v7/opdefs/strh_A88217.d index 3b5f97c..5b7fa38 100644 --- a/plugins/arm/v7/opdefs/strh_A88217.d +++ b/plugins/arm/v7/opdefs/strh_A88217.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,29 +23,99 @@ @title STRH (immediate, ARM) -@desc Store Register Halfword (immediate) calculates an address from a base register value and an immediate offset, and stores a halfword from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. +@id 216 + +@desc { + + Store Register Halfword (immediate) calculates an address from a base register value and an immediate offset, and stores a halfword from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (A1) { @word cond(4) 0 0 0 P(1) U(1) 1 W(1) 0 Rn(4) Rt(4) imm4H(4) 1 0 1 1 imm4L(4) - @syntax <reg_T> <mem_access> + @syntax { + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm strh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { - @conv { + @assert { - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm4H:imm4L, 32) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm strh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm strh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/strh_A88218.d b/plugins/arm/v7/opdefs/strh_A88218.d index 1e9dc1f..149ba8d 100644 --- a/plugins/arm/v7/opdefs/strh_A88218.d +++ b/plugins/arm/v7/opdefs/strh_A88218.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title STRH (register) -@desc Store Register Halfword (register) calculates an address from a base register value and an offset register value, and stores a halfword from a register to memory. The offset register value can be shifted left by 0, 1, 2, or 3 bits. For information about memory accesses see Memory accesses on page A8-294. +@id 217 + +@desc { + + Store Register Halfword (register) calculates an address from a base register value and an offset register value, and stores a halfword from a register to memory. The offset register value can be shifted left by 0, 1, 2, or 3 bits. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (t1) { @half 0 1 0 1 0 0 1 Rm(3) Rn(3) Rt(3) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessOffset(reg_N, reg_M) - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, true, true, false) + } + + @asm strh reg_T maccess } @@ -46,15 +56,19 @@ @word 1 1 1 1 1 0 0 0 0 0 1 0 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) - @syntax ".W" <reg_T> <mem_access> + @syntax { + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = FixedShift(SRType_LSL, imm2) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(0, imm2) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, true, true, false) + @asm strh.w reg_T maccess } @@ -64,23 +78,87 @@ @word cond(4) 0 0 0 P(1) U(1) 0 W(1) 0 Rn(4) Rt(4) 0 0 0 0 1 0 1 1 Rm(4) - @syntax <reg_T> <mem_access> + @syntax { + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessOffset(reg_N, reg_M) + + } + + @asm strh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @assert { + + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPreIndexed(reg_N, reg_M) + + } + + @asm strh reg_T maccess + + @rules { - @conv { + check g_arm_instruction_set_cond(cond) - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, index, add, wback) + } } - @rules { + @syntax { + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(reg_N, reg_M) + + } + + @asm strh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/strht_A88219.d b/plugins/arm/v7/opdefs/strht_A88219.d index 3811572..f7fb37f 100644 --- a/plugins/arm/v7/opdefs/strht_A88219.d +++ b/plugins/arm/v7/opdefs/strht_A88219.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title STRHT -@desc Store Register Halfword Unprivileged stores a halfword from a register to memory. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. STRHT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or a register value. +@id 218 + +@desc { + + Store Register Halfword Unprivileged stores a halfword from a register to memory. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. STRHT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or a register value. + +} @encoding (T1) { @word 1 1 1 1 1 0 0 0 0 0 1 0 Rn(4) Rt(4) 1 1 1 0 imm8(8) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + @asm strht reg_T maccess } @@ -46,21 +56,24 @@ @word cond(4) 0 0 0 0 U(1) 1 1 0 Rn(4) Rt(4) imm4H(4) 1 0 1 1 imm4L(4) - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_N = Register(Rn) - add = (U == '1') - imm32 = ZeroExtend(imm4H:imm4L, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, false, add, false) + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) - } + } + + @asm strht reg_T maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } @@ -70,21 +83,24 @@ @word cond(4) 0 0 0 0 U(1) 0 1 0 Rn(4) Rt(4) 0 0 0 0 1 0 1 1 Rm(4) - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - add = (U == '1') - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, false, add, false) + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(reg_N, reg_M) - } + } + + @asm strht reg_T maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/strt_A88220.d b/plugins/arm/v7/opdefs/strt_A88220.d index 794a0fa..dd1c03a 100644 --- a/plugins/arm/v7/opdefs/strt_A88220.d +++ b/plugins/arm/v7/opdefs/strt_A88220.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title STRT -@desc Store Register Unprivileged stores a word from a register to memory. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. STRT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or an optionally-shifted register value. +@id 219 + +@desc { + + Store Register Unprivileged stores a word from a register to memory. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. STRT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or an optionally-shifted register value. + +} @encoding (T1) { @word 1 1 1 1 1 0 0 0 0 1 0 0 Rn(4) Rt(4) 1 1 1 0 imm8(8) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + @asm strt reg_T maccess } @@ -46,21 +56,24 @@ @word cond(4) 0 1 0 0 U(1) 0 1 0 Rn(4) Rt(4) imm12(12) - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_N = Register(Rn) - add = (U == '1') - imm32 = ZeroExtend(imm12, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, false, add, false) + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) - } + } + + @asm strt reg_T maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } @@ -70,22 +83,25 @@ @word cond(4) 0 1 1 0 U(1) 0 1 0 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - add = (U == '1') - shift = DecodeImmShift(type, imm5) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, false, add, false) + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessPostIndexedExtended(reg_N, reg_M, shift) - } + } + + @asm strt reg_T maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/sub_A88221.d b/plugins/arm/v7/opdefs/sub_A88221.d index 41ce6b3..365943c 100644 --- a/plugins/arm/v7/opdefs/sub_A88221.d +++ b/plugins/arm/v7/opdefs/sub_A88221.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title SUB (immediate, Thumb) -@desc This instruction subtracts an immediate value from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 220 + +@desc { + + This instruction subtracts an immediate value from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (t1) { @half 0 0 0 1 1 1 1 imm3(3) Rn(3) Rd(3) - @syntax "subs" <reg_D> <reg_N> <imm32> + @syntax { + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm3, 32) - @conv { + } - reg_D = Register(Rd) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm3, 32) + @asm sub ?reg_D reg_N imm32 } @@ -45,12 +55,17 @@ @half 0 0 1 1 1 Rdn(3) imm8(8) - @syntax "subs" <reg_DN> <imm32> + @syntax { - @conv { + @conv { - reg_DN = Register(Rdn) - imm32 = ZeroExtend(imm8, 32) + reg_D = Register(Rdn) + reg_N = Register(Rdn) + imm32 = ZeroExtend(imm8, 32) + + } + + @asm sub ?reg_D reg_N imm32 } @@ -60,21 +75,43 @@ @word 1 1 1 1 0 i(1) 0 1 1 0 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - @syntax <reg_D> <reg_N> <imm32> + @syntax { + + @assert { + + S == 0 + + } - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ThumbExpandImm(i:imm3:imm8) + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + + @asm sub.w ?reg_D reg_N imm32 } - @rules { + @syntax { + + @assert { + + S == 1 + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + + @asm subs.w ?reg_D reg_N imm32 } @@ -84,13 +121,17 @@ @word 1 1 1 1 0 i(1) 1 0 1 0 1 0 Rn(4) 0 imm3(3) Rd(4) imm8(8) - @syntax "subw" <reg_D> <reg_N> <imm32> + @syntax { + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ZeroExtend(i:imm3:imm8, 32) - @conv { + } - reg_D = Register(Rd) - reg_N = Register(Rn) - imm32 = ZeroExtend(i:imm3:imm8, 32) + @asm subw ?reg_D reg_N imm32 } diff --git a/plugins/arm/v7/opdefs/sub_A88222.d b/plugins/arm/v7/opdefs/sub_A88222.d index ef326b8..289d045 100644 --- a/plugins/arm/v7/opdefs/sub_A88222.d +++ b/plugins/arm/v7/opdefs/sub_A88222.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,27 +23,67 @@ @title SUB (immediate, ARM) -@desc This instruction subtracts an immediate value from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 221 + +@desc { + + This instruction subtracts an immediate value from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (A1) { @word cond(4) 0 0 1 0 0 1 0 S(1) Rn(4) Rd(4) imm12(12) - @syntax <reg_D> <reg_N> <imm32> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ARMExpandImm(imm12) + + } + + @asm sub ?reg_D reg_N imm32 - @conv { + @rules { - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ARMExpandImm(imm12) + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ARMExpandImm(imm12) + + } + + @asm subs ?reg_D reg_N imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/sub_A88223.d b/plugins/arm/v7/opdefs/sub_A88223.d index a629250..b3b9ef6 100644 --- a/plugins/arm/v7/opdefs/sub_A88223.d +++ b/plugins/arm/v7/opdefs/sub_A88223.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title SUB (register) -@desc This instruction subtracts an optionally-shifted register value from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 222 + +@desc { + + This instruction subtracts an optionally-shifted register value from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (t1) { @half 0 0 0 1 1 0 1 Rm(3) Rn(3) Rd(3) - @syntax "subs" <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm sub ?reg_D reg_N reg_M } @@ -45,22 +55,45 @@ @word 1 1 1 0 1 0 1 1 1 0 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?shift> + @syntax { + + @assert { + + S == 0 + + } - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm3:imm2) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm sub.w ?reg_D reg_N reg_M ?shift } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @asm subs.w ?reg_D reg_N reg_M ?shift } @@ -70,22 +103,57 @@ @word cond(4) 0 0 0 0 0 1 0 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?shift> + @syntax { - @conv { + @assert { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm5) + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm sub ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm subs ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/sub_A88224.d b/plugins/arm/v7/opdefs/sub_A88224.d deleted file mode 100644 index 5ef4e4d..0000000 --- a/plugins/arm/v7/opdefs/sub_A88224.d +++ /dev/null @@ -1,52 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title SUB (register-shifted register) - -@desc This instruction subtracts a register-shifted register value from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -@encoding (A1) { - - @word cond(4) 0 0 0 0 0 1 0 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> <reg_shift> - - @conv { - - reg_shift = RegisterShift(type, Rs) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/plugins/arm/v7/opdefs/sub_A88225.d b/plugins/arm/v7/opdefs/sub_A88225.d index dc54c6b..96708b9 100644 --- a/plugins/arm/v7/opdefs/sub_A88225.d +++ b/plugins/arm/v7/opdefs/sub_A88225.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title SUB (SP minus immediate) -@desc This instruction subtracts an immediate value from the SP value, and writes the result to the destination register. +@id 224 + +@desc { + + This instruction subtracts an immediate value from the SP value, and writes the result to the destination register. + +} @encoding (t1) { @half 1 0 1 1 0 0 0 0 1 imm7(7) - @syntax <SP_0> <SP_1> <imm32> + @syntax { + + @conv { - @conv { + reg_D = Register(13) + reg_SP = Register(13) + imm32 = ZeroExtend(imm7:'00', 32) - imm32 = ZeroExtend(imm7:'00', 32) - SP_0 = Register(13) - SP_1 = Register(13) + } + + @asm sub ?reg_D reg_SP imm32 } @@ -45,21 +55,43 @@ @word 1 1 1 1 0 i(1) 0 1 1 0 1 S(1) 1 1 0 1 0 imm3(3) Rd(4) imm8(8) - @syntax <reg_D> <SP> <imm32> + @syntax { + + @assert { + + S == 0 + + } - @conv { + @conv { - reg_D = Register(Rd) - setflags = (S == '1') - imm32 = ThumbExpandImm(i:imm3:imm8) - SP = Register(13) + reg_D = Register(Rd) + reg_SP = Register(13) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + + @asm sub.w ?reg_D reg_SP imm32 } - @rules { + @syntax { + + @assert { + + S == 1 + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + + @asm subs.w ?reg_D reg_SP imm32 } @@ -69,13 +101,17 @@ @word 1 1 1 1 0 i(1) 1 0 1 0 1 0 1 1 0 1 0 imm3(3) Rd(4) imm8(8) - @syntax "subw" <reg_D> <SP> <imm32> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_SP = Register(13) + imm32 = ZeroExtend(i:imm3:imm8, 32) - reg_D = Register(Rd) - imm32 = ZeroExtend(i:imm3:imm8, 32) - SP = Register(13) + } + + @asm subw ?reg_D reg_SP imm32 } @@ -85,21 +121,55 @@ @word cond(4) 0 0 1 0 0 1 0 S(1) 1 1 0 1 Rd(4) imm12(12) - @syntax <reg_D> <SP> <imm32> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + imm32 = ARMExpandImm(imm12) + + } + + @asm sub ?reg_D reg_SP imm32 + + @rules { - @conv { + check g_arm_instruction_set_cond(cond) - reg_D = Register(Rd) - setflags = (S == '1') - imm32 = ARMExpandImm(imm12) - SP = Register(13) + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + imm32 = ARMExpandImm(imm12) + + } + + @asm subs ?reg_D reg_SP imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/sub_A88226.d b/plugins/arm/v7/opdefs/sub_A88226.d deleted file mode 100644 index 02ecada..0000000 --- a/plugins/arm/v7/opdefs/sub_A88226.d +++ /dev/null @@ -1,76 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title SUB (SP minus register) - -@desc This instruction subtracts an optionally-shifted register value from the SP value, and writes the result to the destination register. - -@encoding (T1) { - - @word 1 1 1 0 1 0 1 1 1 0 1 S(1) 1 1 0 1 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - - @syntax <reg_D> <SP> <reg_M> <?shift> - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm3:imm2) - SP = Register(13) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 0 1 0 S(1) 1 1 0 1 Rd(4) imm5(5) type(2) 0 Rm(4) - - @syntax <reg_D> <SP> <reg_M> <?shift> - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm5) - SP = Register(13) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/plugins/arm/v7/opdefs/subs_B9320.d b/plugins/arm/v7/opdefs/subs_B9320.d deleted file mode 100644 index 335e614..0000000 --- a/plugins/arm/v7/opdefs/subs_B9320.d +++ /dev/null @@ -1,44 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2014 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title SUBS PC, LR and related instructions (ARM) - -@encoding(A1) { - - @word cond(4) 0 0 1 opcode(4) 1 Rn(4) 1 1 1 1 imm12(12) - - @syntax {c} <Rn> <#const> - - @conv { - - c = Condition(cond) - Rn = Register(Rn) - const = ExpandImmC32(imm12) - - } - - @rules { - - } - -} diff --git a/plugins/arm/v7/opdefs/svc_A88228.d b/plugins/arm/v7/opdefs/svc_A88228.d index be48545..0ddc95f 100644 --- a/plugins/arm/v7/opdefs/svc_A88228.d +++ b/plugins/arm/v7/opdefs/svc_A88228.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,17 +23,27 @@ @title SVC (previously SWI) -@desc Supervisor Call, previously called Software Interrupt, causes a Supervisor Call exception. For more information, see Supervisor Call (SVC) exception on page B1-1209. Software can use this instruction as a call to an operating system to provide a service. In the following cases, the Supervisor Call exception generated by the SVC instruction is taken to Hyp mode: • If the SVC is executed in Hyp mode. • If HCR.TGE is set to 1, and the SVC is executed in Non-secure User mode. For more information, see Supervisor Call exception, when HCR.TGE is set to 1 on page B1-1191 In these cases, the HSR identifies that the exception entry was caused by a Supervisor Call exception, EC value 0x11, see Use of the HSR on page B3-1424. The immediate field in the HSR: • if the SVC is unconditional: — for the Thumb instruction, is the zero-extended value of the imm8 field — for the ARM instruction, is the least-significant 16 bits the imm24 field • if the SVC is conditional, is UNKNOWN. +@id 227 + +@desc { + + Supervisor Call, previously called Software Interrupt, causes a Supervisor Call exception. For more information, see Supervisor Call (SVC) exception on page B1-1209. Software can use this instruction as a call to an operating system to provide a service. In the following cases, the Supervisor Call exception generated by the SVC instruction is taken to Hyp mode: • If the SVC is executed in Hyp mode. • If HCR.TGE is set to 1, and the SVC is executed in Non-secure User mode. For more information, see Supervisor Call exception, when HCR.TGE is set to 1 on page B1-1191 In these cases, the HSR identifies that the exception entry was caused by a Supervisor Call exception, EC value 0x11, see Use of the HSR on page B3-1424. The immediate field in the HSR: • if the SVC is unconditional: — for the Thumb instruction, is the zero-extended value of the imm8 field — for the ARM instruction, is the least-significant 16 bits the imm24 field • if the SVC is conditional, is UNKNOWN. + +} @encoding (t1) { @half 1 1 0 1 1 1 1 1 imm8(8) - @syntax <imm32> + @syntax { + + @conv { - @conv { + imm32 = ZeroExtend(imm8, 32) - imm32 = ZeroExtend(imm8, 32) + } + + @asm svc imm32 } @@ -43,17 +53,21 @@ @word cond(4) 1 1 1 1 imm24(24) - @syntax <imm32> + @syntax { - @conv { + @conv { - imm32 = ZeroExtend(imm24, 32) + imm32 = ZeroExtend(imm24, 32) - } + } + + @asm svc imm32 + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/swp_A88229.d b/plugins/arm/v7/opdefs/swp_A88229.d index 2e39015..b901462 100644 --- a/plugins/arm/v7/opdefs/swp_A88229.d +++ b/plugins/arm/v7/opdefs/swp_A88229.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,28 +23,69 @@ @title SWP, SWPB -@desc SWP (Swap) swaps a word between registers and memory. SWP loads a word from the memory address given by the value of register <Rn>. The value of register <Rt2> is then stored to the memory address given by the value of <Rn>, and the original loaded value is written to register <Rt>. If the same register is specified for <Rt> and <Rt2>, this instruction swaps the value of the register and the value at the memory address. SWPB (Swap Byte) swaps a byte between registers and memory. SWPB loads a byte from the memory address given by the value of register <Rn>. The value of the least significant byte of register <Rt2> is stored to the memory address given by <Rn>, the original loaded value is zero-extended to a 32-bit word, and the word is written to register <Rt>. If the same register is specified for <Rt> and <Rt2>, this instruction swaps the value of the least significant byte of the register and the byte value at the memory address, and clears the most significant three bytes of the register. For both instructions, the memory system ensures that no other memory access can occur to the memory location between the load access and the store access. Note • The SWP and SWPB instructions rely on the properties of the system beyond the processor to ensure that no stores from other observers can occur between the load access and the store access, and this might not be implemented for all regions of memory on some system implementations. In all cases, SWP and SWPB do ensure that no stores from the processor that executed the SWP or SWPB instruction can occur between the load access and the store access of the SWP or SWPB. • ARM deprecates the use of SWP and SWPB, and strongly recommends that new software uses: LDREX/STREX in preference to SWP — LDREXB/STREXB in preference to SWPB. — • If the translation table entries that relate to a memory location accessed by the SWP or SWPB instruction change, or are seen to change by the executing processor as a result of TLB eviction, this might mean that the translation table attributes, permissions or addresses for the load are different to those for the store. In this case, the architecture makes no guarantee that no memory access occur to these memory locations between the load and store. The Virtualization Extensions make the SWP and SWPB instructions OPTIONAL and deprecated: • If an implementation does not include the SWP and SWPB instructions, the ID_ISAR0.Swap_instrs and ID_ISAR4.SWP_frac fields are zero, see About the Instruction Set Attribute registers on page B7-1950. • In an implementation that includes SWP and SWPB, both instructions are UNDEFINED in Hyp mode. +@id 228 + +@desc { + + SWP (Swap) swaps a word between registers and memory. SWP loads a word from the memory address given by the value of register <Rn>. The value of register <Rt2> is then stored to the memory address given by the value of <Rn>, and the original loaded value is written to register <Rt>. If the same register is specified for <Rt> and <Rt2>, this instruction swaps the value of the register and the value at the memory address. SWPB (Swap Byte) swaps a byte between registers and memory. SWPB loads a byte from the memory address given by the value of register <Rn>. The value of the least significant byte of register <Rt2> is stored to the memory address given by <Rn>, the original loaded value is zero-extended to a 32-bit word, and the word is written to register <Rt>. If the same register is specified for <Rt> and <Rt2>, this instruction swaps the value of the least significant byte of the register and the byte value at the memory address, and clears the most significant three bytes of the register. For both instructions, the memory system ensures that no other memory access can occur to the memory location between the load access and the store access. Note • The SWP and SWPB instructions rely on the properties of the system beyond the processor to ensure that no stores from other observers can occur between the load access and the store access, and this might not be implemented for all regions of memory on some system implementations. In all cases, SWP and SWPB do ensure that no stores from the processor that executed the SWP or SWPB instruction can occur between the load access and the store access of the SWP or SWPB. • ARM deprecates the use of SWP and SWPB, and strongly recommends that new software uses: LDREX/STREX in preference to SWP — — LDREXB/STREXB in preference to SWPB. • If the translation table entries that relate to a memory location accessed by the SWP or SWPB instruction change, or are seen to change by the executing processor as a result of TLB eviction, this might mean that the translation table attributes, permissions or addresses for the load are different to those for the store. In this case, the architecture makes no guarantee that no memory access occur to these memory locations between the load and store. The Virtualization Extensions make the SWP and SWPB instructions OPTIONAL and deprecated: • If an implementation does not include the SWP and SWPB instructions, the ID_ISAR0.Swap_instrs and ID_ISAR4.SWP_frac fields are zero, see About the Instruction Set Attribute registers on page B7-1950. • In an implementation that includes SWP and SWPB, both instructions are UNDEFINED in Hyp mode. + +} @encoding (A1) { @word cond(4) 0 0 0 1 0 B(1) 0 0 Rn(4) Rt(4) 0 0 0 0 1 0 0 1 Rt2(4) - @syntax <reg_T> <reg_T2> <mem_access> + @syntax { + + @assert { + + B == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) + + } + + @asm swp reg_T reg_T2 maccess - @conv { + @rules { - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - reg_N = Register(Rn) - size = (B != 4) - mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + B == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) + + } + + @asm swpb reg_T reg_T2 maccess + + @rules { + + check g_arm_instruction_set_cond(cond) - if (size); chk_call ExtendKeyword("b") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/teq_A88237.d b/plugins/arm/v7/opdefs/teq_A88237.d index 89073f6..7b431a3 100644 --- a/plugins/arm/v7/opdefs/teq_A88237.d +++ b/plugins/arm/v7/opdefs/teq_A88237.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title TEQ (immediate) -@desc Test Equivalence (immediate) performs a bitwise exclusive OR operation on a register value and an immediate value. It updates the condition flags based on the result, and discards the result. +@id 236 + +@desc { + + Test Equivalence (immediate) performs a bitwise exclusive OR operation on a register value and an immediate value. It updates the condition flags based on the result, and discards the result. + +} @encoding (T1) { @word 1 1 1 1 0 i(1) 0 0 1 0 0 1 Rn(4) 0 imm3(3) 1 1 1 1 imm8(8) - @syntax <reg_N> <imm32> + @syntax { + + @conv { - @conv { + reg_N = Register(Rn) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) - reg_N = Register(Rn) - imm32 = ThumbExpandImm_C(i:imm3:imm8, 0) + } + + @asm teq reg_N const } @@ -44,18 +54,22 @@ @word cond(4) 0 0 1 1 0 0 1 1 Rn(4) 0 0 0 0 imm12(12) - @syntax <reg_N> <imm32> + @syntax { - @conv { + @conv { - reg_N = Register(Rn) - imm32 = ARMExpandImm_C(imm12, 0) + reg_N = Register(Rn) + const = ARMExpandImm_C(imm12, APSR_C) - } + } + + @asm teq reg_N const + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/teq_A88238.d b/plugins/arm/v7/opdefs/teq_A88238.d index 8187d81..9e80034 100644 --- a/plugins/arm/v7/opdefs/teq_A88238.d +++ b/plugins/arm/v7/opdefs/teq_A88238.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title TEQ (register) -@desc Test Equivalence (register) performs a bitwise exclusive OR operation on a register value and an optionally-shifted register value. It updates the condition flags based on the result, and discards the result. +@id 237 + +@desc { + + Test Equivalence (register) performs a bitwise exclusive OR operation on a register value and an optionally-shifted register value. It updates the condition flags based on the result, and discards the result. + +} @encoding (T1) { @word 1 1 1 0 1 0 1 0 1 0 0 1 Rn(4) 0 imm3(3) 1 1 1 1 imm2(2) type(2) Rm(4) - @syntax <reg_N> <reg_M> <?shift> + @syntax { + + @conv { - @conv { + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) + } + + @asm teq reg_N reg_M ?shift } @@ -45,19 +55,23 @@ @word cond(4) 0 0 0 1 0 0 1 1 Rn(4) 0 0 0 0 imm5(5) type(2) 0 Rm(4) - @syntax <reg_N> <reg_M> <?shift> + @syntax { - @conv { + @conv { - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) - } + } + + @asm teq reg_N reg_M ?shift + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/teq_A88239.d b/plugins/arm/v7/opdefs/teq_A88239.d index 986a7f0..76e3062 100644 --- a/plugins/arm/v7/opdefs/teq_A88239.d +++ b/plugins/arm/v7/opdefs/teq_A88239.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,25 +23,37 @@ @title TEQ (register-shifted register) -@desc Test Equivalence (register-shifted register) performs a bitwise exclusive OR operation on a register value and a register-shifted register value. It updates the condition flags based on the result, and discards the result. +@id 238 + +@desc { + + Test Equivalence (register-shifted register) performs a bitwise exclusive OR operation on a register value and a register-shifted register value. It updates the condition flags based on the result, and discards the result. + +} @encoding (A1) { @word cond(4) 0 0 0 1 0 0 1 1 Rn(4) 0 0 0 0 Rs(4) 0 type(2) 1 Rm(4) - @syntax <reg_N> <reg_M> <reg_shift> + @syntax { - @conv { + @conv { - reg_shift = RegisterShift(type, Rs) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) - } + } + + @asm teq reg_N reg_M shift + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/tst_A88240.d b/plugins/arm/v7/opdefs/tst_A88240.d index 0ff5121..50c0507 100644 --- a/plugins/arm/v7/opdefs/tst_A88240.d +++ b/plugins/arm/v7/opdefs/tst_A88240.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title TST (immediate) -@desc Test (immediate) performs a bitwise AND operation on a register value and an immediate value. It updates the condition flags based on the result, and discards the result. +@id 239 + +@desc { + + Test (immediate) performs a bitwise AND operation on a register value and an immediate value. It updates the condition flags based on the result, and discards the result. + +} @encoding (T1) { @word 1 1 1 1 0 i(1) 0 0 0 0 0 1 Rn(4) 0 imm3(3) 1 1 1 1 imm8(8) - @syntax <reg_N> <imm32> + @syntax { + + @conv { - @conv { + reg_N = Register(Rn) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) - reg_N = Register(Rn) - imm32 = ThumbExpandImm_C(i:imm3:imm8, 0) + } + + @asm tst reg_N const } @@ -44,18 +54,22 @@ @word cond(4) 0 0 1 1 0 0 0 1 Rn(4) 0 0 0 0 imm12(12) - @syntax <reg_N> <imm32> + @syntax { - @conv { + @conv { - reg_N = Register(Rn) - imm32 = ARMExpandImm_C(imm12, 0) + reg_N = Register(Rn) + const = ARMExpandImm_C(imm12, APSR_C) - } + } + + @asm tst reg_N const + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/tst_A88241.d b/plugins/arm/v7/opdefs/tst_A88241.d index 8777d06..ac1d843 100644 --- a/plugins/arm/v7/opdefs/tst_A88241.d +++ b/plugins/arm/v7/opdefs/tst_A88241.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title TST (register) -@desc Test (register) performs a bitwise AND operation on a register value and an optionally-shifted register value. It updates the condition flags based on the result, and discards the result. +@id 240 + +@desc { + + Test (register) performs a bitwise AND operation on a register value and an optionally-shifted register value. It updates the condition flags based on the result, and discards the result. + +} @encoding (t1) { @half 0 1 0 0 0 0 1 0 0 0 Rm(3) Rn(3) - @syntax <reg_N> <reg_M> + @syntax { + + @conv { + + reg_N = Register(Rn) + reg_M = Register(Rm) - @conv { + } - reg_N = Register(Rn) - reg_M = Register(Rm) + @asm tst reg_N reg_M } @@ -44,13 +54,17 @@ @word 1 1 1 0 1 0 1 0 0 0 0 1 Rn(4) 0 imm3(3) 1 1 1 1 imm2(2) type(2) Rm(4) - @syntax ".W" <reg_N> <reg_M> <?shift> + @syntax { - @conv { + @conv { - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm tst.w reg_N reg_M ?shift } @@ -60,19 +74,23 @@ @word cond(4) 0 0 0 1 0 0 0 1 Rn(4) 0 0 0 0 imm5(5) type(2) 0 Rm(4) - @syntax <reg_N> <reg_M> <?shift> + @syntax { - @conv { + @conv { - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) - } + } + + @asm tst reg_N reg_M ?shift + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/tst_A88242.d b/plugins/arm/v7/opdefs/tst_A88242.d index d3fdd9c..7ffb302 100644 --- a/plugins/arm/v7/opdefs/tst_A88242.d +++ b/plugins/arm/v7/opdefs/tst_A88242.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,25 +23,37 @@ @title TST (register-shifted register) -@desc Test (register-shifted register) performs a bitwise AND operation on a register value and a register-shifted register value. It updates the condition flags based on the result, and discards the result. +@id 241 + +@desc { + + Test (register-shifted register) performs a bitwise AND operation on a register value and a register-shifted register value. It updates the condition flags based on the result, and discards the result. + +} @encoding (A1) { @word cond(4) 0 0 0 1 0 0 0 1 Rn(4) 0 0 0 0 Rs(4) 0 type(2) 1 Rm(4) - @syntax <reg_N> <reg_M> <reg_shift> + @syntax { - @conv { + @conv { - reg_shift = RegisterShift(type, Rs) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) - } + } + + @asm tst reg_N reg_M shift + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/uadd16_A88243.d b/plugins/arm/v7/opdefs/uadd16_A88243.d index fcaadee..9e6ec47 100644 --- a/plugins/arm/v7/opdefs/uadd16_A88243.d +++ b/plugins/arm/v7/opdefs/uadd16_A88243.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title UADD16 -@desc Unsigned Add 16 performs two 16-bit unsigned integer additions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the additions. +@id 242 + +@desc { + + Unsigned Add 16 performs two 16-bit unsigned integer additions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the additions. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 0 1 Rn(4) 1 1 1 1 Rd(4) 0 1 0 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm uadd16 ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 1 0 1 Rn(4) Rd(4) 1 1 1 1 0 0 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm uadd16 ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/uadd8_A88244.d b/plugins/arm/v7/opdefs/uadd8_A88244.d index 451ca79..1cd1b79 100644 --- a/plugins/arm/v7/opdefs/uadd8_A88244.d +++ b/plugins/arm/v7/opdefs/uadd8_A88244.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title UADD8 -@desc Unsigned Add 8 performs four unsigned 8-bit integer additions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the additions. +@id 243 + +@desc { + + Unsigned Add 8 performs four unsigned 8-bit integer additions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the additions. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm uadd8 ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 1 0 1 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm uadd8 ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/uasx_A88245.d b/plugins/arm/v7/opdefs/uasx_A88245.d index f968527..ada4b7a 100644 --- a/plugins/arm/v7/opdefs/uasx_A88245.d +++ b/plugins/arm/v7/opdefs/uasx_A88245.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title UASX -@desc Unsigned Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, and writes the results to the destination register. It sets the APSR.GE bits according to the results. +@id 244 + +@desc { + + Unsigned Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, and writes the results to the destination register. It sets the APSR.GE bits according to the results. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 1 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm uasx ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 1 0 1 Rn(4) Rd(4) 1 1 1 1 0 0 1 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm uasx ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ubfx_A88246.d b/plugins/arm/v7/opdefs/ubfx_A88246.d index 1f9488e..31c3f43 100644 --- a/plugins/arm/v7/opdefs/ubfx_A88246.d +++ b/plugins/arm/v7/opdefs/ubfx_A88246.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,31 @@ @title UBFX -@desc Unsigned Bit Field Extract extracts any number of adjacent bits at any position from a register, zero-extends them to 32 bits, and writes the result to the destination register. +@id 245 + +@desc { + + Unsigned Bit Field Extract extracts any number of adjacent bits at any position from a register, zero-extends them to 32 bits, and writes the result to the destination register. + +} @encoding (T1) { @word 1 1 1 1 0 0 1 1 1 1 0 0 Rn(4) 0 imm3(3) Rd(4) imm2(2) 0 widthm1(5) - @syntax <reg_D> <reg_N> <lsbit> <width> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + lsbit = UInt(imm3:imm2) + widthminus1 = UInt(widthm1) + width = MinusBitDiff(widthminus1, lsbit) - reg_D = Register(Rd) - reg_N = Register(Rn) - lsbit = UInt(imm3:imm2) - width = IncWidth(widthm1) + } + + @asm ubfx reg_D reg_N lsbit width } @@ -46,20 +57,25 @@ @word cond(4) 0 1 1 1 1 1 1 widthm1(5) Rd(4) lsb(5) 1 0 1 Rn(4) - @syntax <reg_D> <reg_N> <lsbit> <width> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - lsbit = UInt(lsb) - width = IncWidth(widthm1) + reg_D = Register(Rd) + reg_N = Register(Rn) + lsbit = UInt(lsb) + widthminus1 = UInt(widthm1) + width = MinusBitDiff(widthminus1, lsbit) - } + } + + @asm ubfx reg_D reg_N lsbit width + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/udf_A88247.d b/plugins/arm/v7/opdefs/udf_A88247.d index 38f818c..db8fc28 100644 --- a/plugins/arm/v7/opdefs/udf_A88247.d +++ b/plugins/arm/v7/opdefs/udf_A88247.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,17 +23,27 @@ @title UDF -@desc Permanently Undefined generates an Undefined Instruction exception. The encodings for UDF used in this section are defined as permanently UNDEFINED in the versions of the architecture specified in this section. Issue C.a of this manual first defines an assembler mnemonic for these encodings. However: • with the Thumb instruction set, ARM deprecates using the UDF instruction in an IT block • in the ARM instruction set, UDF is not conditional. +@id 246 + +@desc { + + Permanently Undefined generates an Undefined Instruction exception. The encodings for UDF used in this section are defined as permanently UNDEFINED in the versions of the architecture specified in this section. Issue C.a of this manual first defines an assembler mnemonic for these encodings. However: • with the Thumb instruction set, ARM deprecates using the UDF instruction in an IT block • in the ARM instruction set, UDF is not conditional. + +} @encoding (t1) { @half 1 1 0 1 1 1 1 0 imm8(8) - @syntax <imm32> + @syntax { + + @conv { - @conv { + imm32 = ZeroExtend(imm8, 32) - imm32 = ZeroExtend(imm8, 32) + } + + @asm udf imm32 } @@ -43,11 +53,15 @@ @word 1 1 1 1 0 1 1 1 1 1 1 1 imm4(4) 1 0 1 0 imm12(12) - @syntax ".W" <imm32> + @syntax { + + @conv { + + imm32 = ZeroExtend(imm4:imm12, 32) - @conv { + } - imm32 = ZeroExtend(imm4:imm12, 32) + @asm udf.w imm32 } @@ -57,11 +71,15 @@ @word 1 1 1 0 0 1 1 1 1 1 1 1 imm12(12) 1 1 1 1 imm4(4) - @syntax <imm32> + @syntax { + + @conv { + + imm32 = ZeroExtend(imm12:imm4, 32) - @conv { + } - imm32 = ZeroExtend(imm12:imm4, 32) + @asm udf imm32 } diff --git a/plugins/arm/v7/opdefs/udiv_A88248.d b/plugins/arm/v7/opdefs/udiv_A88248.d index eea7947..411e323 100644 --- a/plugins/arm/v7/opdefs/udiv_A88248.d +++ b/plugins/arm/v7/opdefs/udiv_A88248.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title UDIV -@desc Unsigned Divide divides a 32-bit unsigned integer register value by a 32-bit unsigned integer register value, and writes the result to the destination register. The condition flags are not affected. See ARMv7 implementation requirements and options for the divide instructions on page A4-172 for more information about this instruction. +@id 247 + +@desc { + + Unsigned Divide divides a 32-bit unsigned integer register value by a 32-bit unsigned integer register value, and writes the result to the destination register. The condition flags are not affected. See ARMv7 implementation requirements and options for the divide instructions on page A4-172 for more information about this instruction. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 1 1 0 1 1 Rn(4) 1 1 1 1 Rd(4) 1 1 1 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm udiv ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 1 0 0 1 1 Rd(4) 1 1 1 1 Rm(4) 0 0 0 1 Rn(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm udiv ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/uhadd16_A88249.d b/plugins/arm/v7/opdefs/uhadd16_A88249.d index 54da5b0..e335f3c 100644 --- a/plugins/arm/v7/opdefs/uhadd16_A88249.d +++ b/plugins/arm/v7/opdefs/uhadd16_A88249.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title UHADD16 -@desc Unsigned Halving Add 16 performs two unsigned 16-bit integer additions, halves the results, and writes the results to the destination register. +@id 248 + +@desc { + + Unsigned Halving Add 16 performs two unsigned 16-bit integer additions, halves the results, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 0 1 Rn(4) 1 1 1 1 Rd(4) 0 1 1 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm uhadd16 ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 1 1 1 Rn(4) Rd(4) 1 1 1 1 0 0 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm uhadd16 ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/uhadd8_A88250.d b/plugins/arm/v7/opdefs/uhadd8_A88250.d index 759a0a7..f392b5e 100644 --- a/plugins/arm/v7/opdefs/uhadd8_A88250.d +++ b/plugins/arm/v7/opdefs/uhadd8_A88250.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title UHADD8 -@desc Unsigned Halving Add 8 performs four unsigned 8-bit integer additions, halves the results, and writes the results to the destination register. +@id 249 + +@desc { + + Unsigned Halving Add 8 performs four unsigned 8-bit integer additions, halves the results, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 0 1 1 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm uhadd8 ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 1 1 1 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm uhadd8 ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/uhasx_A88251.d b/plugins/arm/v7/opdefs/uhasx_A88251.d index 3751394..b5c4153 100644 --- a/plugins/arm/v7/opdefs/uhasx_A88251.d +++ b/plugins/arm/v7/opdefs/uhasx_A88251.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title UHASX -@desc Unsigned Halving Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, halves the results, and writes the results to the destination register. +@id 250 + +@desc { + + Unsigned Halving Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, halves the results, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 1 0 Rn(4) 1 1 1 1 Rd(4) 0 1 1 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm uhasx ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 1 1 1 Rn(4) Rd(4) 1 1 1 1 0 0 1 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm uhasx ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/uhsax_A88252.d b/plugins/arm/v7/opdefs/uhsax_A88252.d index f06b2ba..7b793f4 100644 --- a/plugins/arm/v7/opdefs/uhsax_A88252.d +++ b/plugins/arm/v7/opdefs/uhsax_A88252.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title UHSAX -@desc Unsigned Halving Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, halves the results, and writes the results to the destination register. +@id 251 + +@desc { + + Unsigned Halving Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, halves the results, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 1 1 0 Rn(4) 1 1 1 1 Rd(4) 0 1 1 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm uhsax ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 1 1 1 Rn(4) Rd(4) 1 1 1 1 0 1 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm uhsax ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/uhsub16_A88253.d b/plugins/arm/v7/opdefs/uhsub16_A88253.d index 93f92f7..482ac1d 100644 --- a/plugins/arm/v7/opdefs/uhsub16_A88253.d +++ b/plugins/arm/v7/opdefs/uhsub16_A88253.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title UHSUB16 -@desc Unsigned Halving Subtract 16 performs two unsigned 16-bit integer subtractions, halves the results, and writes the results to the destination register. +@id 252 + +@desc { + + Unsigned Halving Subtract 16 performs two unsigned 16-bit integer subtractions, halves the results, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 1 0 1 Rn(4) 1 1 1 1 Rd(4) 0 1 1 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm uhsub16 ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 1 1 1 Rn(4) Rd(4) 1 1 1 1 0 1 1 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm uhsub16 ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/uhsub8_A88254.d b/plugins/arm/v7/opdefs/uhsub8_A88254.d index 198a095..c5349e4 100644 --- a/plugins/arm/v7/opdefs/uhsub8_A88254.d +++ b/plugins/arm/v7/opdefs/uhsub8_A88254.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title UHSUB8 -@desc Unsigned Halving Subtract 8 performs four unsigned 8-bit integer subtractions, halves the results, and writes the results to the destination register. +@id 253 + +@desc { + + Unsigned Halving Subtract 8 performs four unsigned 8-bit integer subtractions, halves the results, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 1 0 0 Rn(4) 1 1 1 1 Rd(4) 0 1 1 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm uhsub8 ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 1 1 1 Rn(4) Rd(4) 1 1 1 1 1 1 1 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm uhsub8 ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/umaal_A88255.d b/plugins/arm/v7/opdefs/umaal_A88255.d index 34cb707..10a823a 100644 --- a/plugins/arm/v7/opdefs/umaal_A88255.d +++ b/plugins/arm/v7/opdefs/umaal_A88255.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title UMAAL -@desc Unsigned Multiply Accumulate Accumulate Long multiplies two unsigned 32-bit values to produce a 64-bit value, adds two unsigned 32-bit values, and writes the 64-bit result to two registers. +@id 254 + +@desc { + + Unsigned Multiply Accumulate Accumulate Long multiplies two unsigned 32-bit values to produce a 64-bit value, adds two unsigned 32-bit values, and writes the 64-bit result to two registers. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 1 1 1 1 0 Rn(4) RdLo(4) RdHi(4) 0 1 1 0 Rm(4) - @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm umaal reg_DLO reg_DHI reg_N reg_M } @@ -46,20 +56,24 @@ @word cond(4) 0 0 0 0 0 1 0 0 RdHi(4) RdLo(4) Rm(4) 1 0 0 1 Rn(4) - @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm umaal reg_DLO reg_DHI reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/umlal_A88256.d b/plugins/arm/v7/opdefs/umlal_A88256.d index 00d1903..83af10c 100644 --- a/plugins/arm/v7/opdefs/umlal_A88256.d +++ b/plugins/arm/v7/opdefs/umlal_A88256.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title UMLAL -@desc Unsigned Multiply Accumulate Long multiplies two unsigned 32-bit values to produce a 64-bit value, and accumulates this with a 64-bit value. In ARM instructions, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many processor implementations. +@id 255 + +@desc { + + Unsigned Multiply Accumulate Long multiplies two unsigned 32-bit values to produce a 64-bit value, and accumulates this with a 64-bit value. In ARM instructions, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many processor implementations. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 1 1 1 1 0 Rn(4) RdLo(4) RdHi(4) 0 0 0 0 Rm(4) - @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> + @syntax { + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) - @conv { + } - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) + @asm umlal reg_DLO reg_DHI reg_N reg_M } @@ -46,22 +56,57 @@ @word cond(4) 0 0 0 0 1 0 1 S(1) RdHi(4) RdLo(4) Rm(4) 1 0 0 1 Rn(4) - @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } - @conv { + @asm umlal reg_DLO reg_DHI reg_N reg_M - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm umlals reg_DLO reg_DHI reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/umull_A88257.d b/plugins/arm/v7/opdefs/umull_A88257.d index d2cc321..2164bb4 100644 --- a/plugins/arm/v7/opdefs/umull_A88257.d +++ b/plugins/arm/v7/opdefs/umull_A88257.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title UMULL -@desc Unsigned Multiply Long multiplies two 32-bit unsigned values to produce a 64-bit result. In ARM instructions, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many processor implementations. +@id 256 + +@desc { + + Unsigned Multiply Long multiplies two 32-bit unsigned values to produce a 64-bit result. In ARM instructions, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many processor implementations. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 1 1 0 1 0 Rn(4) RdLo(4) RdHi(4) 0 0 0 0 Rm(4) - @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> + @syntax { + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) - @conv { + } - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) + @asm umull reg_DLO reg_DHI reg_N reg_M } @@ -46,22 +56,57 @@ @word cond(4) 0 0 0 0 1 0 0 S(1) RdHi(4) RdLo(4) Rm(4) 1 0 0 1 Rn(4) - @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } - @conv { + @asm umull reg_DLO reg_DHI reg_N reg_M - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm umulls reg_DLO reg_DHI reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/uqadd16_A88258.d b/plugins/arm/v7/opdefs/uqadd16_A88258.d index 14528c8..4e099ec 100644 --- a/plugins/arm/v7/opdefs/uqadd16_A88258.d +++ b/plugins/arm/v7/opdefs/uqadd16_A88258.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title UQADD16 -@desc Unsigned Saturating Add 16 performs two unsigned 16-bit integer additions, saturates the results to the 16-bit unsigned integer range 0 ≤ x ≤ 216 – 1, and writes the results to the destination register. +@id 257 + +@desc { + + Unsigned Saturating Add 16 performs two unsigned 16-bit integer additions, saturates the results to the 16-bit unsigned integer range 0 ≤ x ≤ 216 – 1, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 0 1 Rn(4) 1 1 1 1 Rd(4) 0 1 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm uqadd16 ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 1 1 0 Rn(4) Rd(4) 1 1 1 1 0 0 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm uqadd16 ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/uqadd8_A88259.d b/plugins/arm/v7/opdefs/uqadd8_A88259.d index 94b8e39..4ac517a 100644 --- a/plugins/arm/v7/opdefs/uqadd8_A88259.d +++ b/plugins/arm/v7/opdefs/uqadd8_A88259.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title UQADD8 -@desc Unsigned Saturating Add 8 performs four unsigned 8-bit integer additions, saturates the results to the 8-bit unsigned integer range 0 ≤ x ≤ 28 – 1, and writes the results to the destination register. +@id 258 + +@desc { + + Unsigned Saturating Add 8 performs four unsigned 8-bit integer additions, saturates the results to the 8-bit unsigned integer range 0 ≤ x ≤ 28 – 1, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm uqadd8 ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 1 1 0 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm uqadd8 ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/uqasx_A88260.d b/plugins/arm/v7/opdefs/uqasx_A88260.d index 174b08c..0b2047f 100644 --- a/plugins/arm/v7/opdefs/uqasx_A88260.d +++ b/plugins/arm/v7/opdefs/uqasx_A88260.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title UQASX -@desc Unsigned Saturating Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, saturates the results to the 16-bit unsigned integer range 0 ≤ x ≤ 216 – 1, and writes the results to the destination register. +@id 259 + +@desc { + + Unsigned Saturating Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, saturates the results to the 16-bit unsigned integer range 0 ≤ x ≤ 216 – 1, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 1 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm uqasx ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 1 1 0 Rn(4) Rd(4) 1 1 1 1 0 0 1 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm uqasx ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/uqsax_A88261.d b/plugins/arm/v7/opdefs/uqsax_A88261.d index 6092e51..57b1b3f 100644 --- a/plugins/arm/v7/opdefs/uqsax_A88261.d +++ b/plugins/arm/v7/opdefs/uqsax_A88261.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title UQSAX -@desc Unsigned Saturating Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, saturates the results to the 16-bit unsigned integer range 0 ≤ x ≤ 216 – 1, and writes the results to the destination register. +@id 260 + +@desc { + + Unsigned Saturating Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, saturates the results to the 16-bit unsigned integer range 0 ≤ x ≤ 216 – 1, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 1 1 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm uqsax ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 1 1 0 Rn(4) Rd(4) 1 1 1 1 0 1 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm uqsax ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/uqsub16_A88262.d b/plugins/arm/v7/opdefs/uqsub16_A88262.d index 1f458ff..23a4fb7 100644 --- a/plugins/arm/v7/opdefs/uqsub16_A88262.d +++ b/plugins/arm/v7/opdefs/uqsub16_A88262.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title UQSUB16 -@desc Unsigned Saturating Subtract 16 performs two unsigned 16-bit integer subtractions, saturates the results to the 16-bit unsigned integer range 0 ≤ x ≤ 216 – 1, and writes the results to the destination register. +@id 261 + +@desc { + + Unsigned Saturating Subtract 16 performs two unsigned 16-bit integer subtractions, saturates the results to the 16-bit unsigned integer range 0 ≤ x ≤ 216 – 1, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 1 0 1 Rn(4) 1 1 1 1 Rd(4) 0 1 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm uqsub16 ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 1 1 0 Rn(4) Rd(4) 1 1 1 1 0 1 1 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm uqsub16 ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/uqsub8_A88263.d b/plugins/arm/v7/opdefs/uqsub8_A88263.d index 37d96e7..4054ec5 100644 --- a/plugins/arm/v7/opdefs/uqsub8_A88263.d +++ b/plugins/arm/v7/opdefs/uqsub8_A88263.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title UQSUB8 -@desc Unsigned Saturating Subtract 8 performs four unsigned 8-bit integer subtractions, saturates the results to the 8-bit unsigned integer range 0 ≤ x ≤ 28 – 1, and writes the results to the destination register. +@id 262 + +@desc { + + Unsigned Saturating Subtract 8 performs four unsigned 8-bit integer subtractions, saturates the results to the 8-bit unsigned integer range 0 ≤ x ≤ 28 – 1, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 1 0 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm uqsub8 ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 1 1 0 Rn(4) Rd(4) 1 1 1 1 1 1 1 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm uqsub8 ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/usad8_A88264.d b/plugins/arm/v7/opdefs/usad8_A88264.d index 09d7ece..2927910 100644 --- a/plugins/arm/v7/opdefs/usad8_A88264.d +++ b/plugins/arm/v7/opdefs/usad8_A88264.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title USAD8 -@desc Unsigned Sum of Absolute Differences performs four unsigned 8-bit subtractions, and adds the absolute values of the differences together. +@id 263 + +@desc { + + Unsigned Sum of Absolute Differences performs four unsigned 8-bit subtractions, and adds the absolute values of the differences together. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 1 0 1 1 1 Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm usad8 ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 1 1 0 0 0 Rd(4) 1 1 1 1 Rm(4) 0 0 0 1 Rn(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm usad8 ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/usada8_A88265.d b/plugins/arm/v7/opdefs/usada8_A88265.d index dd1efdb..df1b7f4 100644 --- a/plugins/arm/v7/opdefs/usada8_A88265.d +++ b/plugins/arm/v7/opdefs/usada8_A88265.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title USADA8 -@desc Unsigned Sum of Absolute Differences and Accumulate performs four unsigned 8-bit subtractions, and adds the absolute values of the differences to a 32-bit accumulate operand. +@id 264 + +@desc { + + Unsigned Sum of Absolute Differences and Accumulate performs four unsigned 8-bit subtractions, and adds the absolute values of the differences to a 32-bit accumulate operand. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 1 0 1 1 1 Rn(4) Ra(4) Rd(4) 0 0 0 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <reg_A> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) + } + + @asm usada8 reg_D reg_N reg_M reg_A } @@ -46,20 +56,24 @@ @word cond(4) 0 1 1 1 1 0 0 0 Rd(4) Ra(4) Rm(4) 0 0 0 1 Rn(4) - @syntax <reg_D> <reg_N> <reg_M> <reg_A> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) - } + } + + @asm usada8 reg_D reg_N reg_M reg_A + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/usat16_A88267.d b/plugins/arm/v7/opdefs/usat16_A88267.d index c091dc6..056c0f2 100644 --- a/plugins/arm/v7/opdefs/usat16_A88267.d +++ b/plugins/arm/v7/opdefs/usat16_A88267.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title USAT16 -@desc Unsigned Saturate 16 saturates two signed 16-bit values to a selected unsigned range. The Q flag is set if the operation saturates. +@id 266 + +@desc { + + Unsigned Saturate 16 saturates two signed 16-bit values to a selected unsigned range. The Q flag is set if the operation saturates. + +} @encoding (T1) { @word 1 1 1 1 0 0 1 1 1 0 1 0 Rn(4) 0 0 0 0 Rd(4) 0 0 0 0 sat_imm(4) - @syntax <reg_D> <saturate_to> <reg_N> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + saturate_to = UInt(sat_imm) + reg_N = Register(Rn) - reg_D = Register(Rd) - reg_N = Register(Rn) - saturate_to = UInt(sat_imm) + } + + @asm usat16 reg_D saturate_to reg_N } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 1 1 1 0 sat_imm(4) Rd(4) 1 1 1 1 0 0 1 1 Rn(4) - @syntax <reg_D> <saturate_to> <reg_N> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - saturate_to = UInt(sat_imm) + reg_D = Register(Rd) + saturate_to = UInt(sat_imm) + reg_N = Register(Rn) - } + } + + @asm usat16 reg_D saturate_to reg_N + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/usat_A88266.d b/plugins/arm/v7/opdefs/usat_A88266.d index 55de21a..c89d083 100644 --- a/plugins/arm/v7/opdefs/usat_A88266.d +++ b/plugins/arm/v7/opdefs/usat_A88266.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title USAT -@desc Unsigned Saturate saturates an optionally-shifted signed value to a selected unsigned range. The Q flag is set if the operation saturates. +@id 265 + +@desc { + + Unsigned Saturate saturates an optionally-shifted signed value to a selected unsigned range. The Q flag is set if the operation saturates. + +} @encoding (T1) { @word 1 1 1 1 0 0 1 1 1 0 sh(1) 0 Rn(4) 0 imm3(3) Rd(4) imm2(2) 0 sat_imm(5) - @syntax <reg_D> <saturate_to> <reg_N> <?shift> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + saturate_to = UInt(sat_imm) + reg_N = Register(Rn) + shift = DecodeImmShift(sh:'0', imm3:imm2) - reg_D = Register(Rd) - reg_N = Register(Rn) - saturate_to = UInt(sat_imm) - shift = DecodeImmShift(sh:'0', imm3:imm2) + } + + @asm usat reg_D saturate_to reg_N ?shift } @@ -46,20 +56,24 @@ @word cond(4) 0 1 1 0 1 1 1 sat_imm(5) Rd(4) imm5(5) sh(1) 0 1 Rn(4) - @syntax <reg_D> <saturate_to> <reg_N> <?shift> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - saturate_to = UInt(sat_imm) - shift = DecodeImmShift(sh:'0', imm5) + reg_D = Register(Rd) + saturate_to = UInt(sat_imm) + reg_N = Register(Rn) + shift = DecodeImmShift(sh:'0', imm5) - } + } + + @asm usat reg_D saturate_to reg_N ?shift + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/usax_A88268.d b/plugins/arm/v7/opdefs/usax_A88268.d index 040eedc..d8c5305 100644 --- a/plugins/arm/v7/opdefs/usax_A88268.d +++ b/plugins/arm/v7/opdefs/usax_A88268.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title USAX -@desc Unsigned Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, and writes the results to the destination register. It sets the APSR.GE bits according to the results. +@id 267 + +@desc { + + Unsigned Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, and writes the results to the destination register. It sets the APSR.GE bits according to the results. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 1 1 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm usax ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 1 0 1 Rn(4) Rd(4) 1 1 1 1 0 1 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm usax ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/usub16_A88269.d b/plugins/arm/v7/opdefs/usub16_A88269.d index 31796d9..1209abf 100644 --- a/plugins/arm/v7/opdefs/usub16_A88269.d +++ b/plugins/arm/v7/opdefs/usub16_A88269.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title USUB16 -@desc Unsigned Subtract 16 performs two 16-bit unsigned integer subtractions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the subtractions. +@id 268 + +@desc { + + Unsigned Subtract 16 performs two 16-bit unsigned integer subtractions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the subtractions. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 1 0 1 Rn(4) 1 1 1 1 Rd(4) 0 1 0 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm usub16 ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 1 0 1 Rn(4) Rd(4) 1 1 1 1 0 1 1 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm usub16 ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/usub8_A88270.d b/plugins/arm/v7/opdefs/usub8_A88270.d index 576894c..659a0e0 100644 --- a/plugins/arm/v7/opdefs/usub8_A88270.d +++ b/plugins/arm/v7/opdefs/usub8_A88270.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title USUB8 -@desc Unsigned Subtract 8 performs four 8-bit unsigned integer subtractions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the subtractions. +@id 269 + +@desc { + + Unsigned Subtract 8 performs four 8-bit unsigned integer subtractions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the subtractions. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 1 0 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm usub8 ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 1 0 1 Rn(4) Rd(4) 1 1 1 1 1 1 1 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm usub8 ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/uxtab16_A88272.d b/plugins/arm/v7/opdefs/uxtab16_A88272.d index 4fc61d2..92109fb 100644 --- a/plugins/arm/v7/opdefs/uxtab16_A88272.d +++ b/plugins/arm/v7/opdefs/uxtab16_A88272.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title UXTAB16 -@desc Unsigned Extend and Add Byte 16 extracts two 8-bit values from a register, zero-extends them to 16 bits each, adds the results to two 16-bit values from another register, and writes the final results to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit values. +@id 271 + +@desc { + + Unsigned Extend and Add Byte 16 extracts two 8-bit values from a register, zero-extends them to 16 bits each, adds the results to two 16-bit values from another register, and writes the final results to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit values. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 0 0 1 1 Rn(4) 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?rotation> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') + } + + @asm uxtab16 ?reg_D reg_N reg_M ?rotation } @@ -46,20 +56,24 @@ @word cond(4) 0 1 1 0 1 1 0 0 Rn(4) Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?rotation> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') - } + } + + @asm uxtab16 ?reg_D reg_N reg_M ?rotation + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/uxtab_A88271.d b/plugins/arm/v7/opdefs/uxtab_A88271.d index fe27d4b..9c98102 100644 --- a/plugins/arm/v7/opdefs/uxtab_A88271.d +++ b/plugins/arm/v7/opdefs/uxtab_A88271.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title UXTAB -@desc Unsigned Extend and Add Byte extracts an 8-bit value from a register, zero-extends it to 32 bits, adds the result to the value in another register, and writes the final result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit value. +@id 270 + +@desc { + + Unsigned Extend and Add Byte extracts an 8-bit value from a register, zero-extends it to 32 bits, adds the result to the value in another register, and writes the final result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit value. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 0 1 0 1 Rn(4) 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?rotation> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') + } + + @asm uxtab ?reg_D reg_N reg_M ?rotation } @@ -46,20 +56,24 @@ @word cond(4) 0 1 1 0 1 1 1 0 Rn(4) Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?rotation> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') - } + } + + @asm uxtab ?reg_D reg_N reg_M ?rotation + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/uxtah_A88273.d b/plugins/arm/v7/opdefs/uxtah_A88273.d index 3c587d9..c1d0d36 100644 --- a/plugins/arm/v7/opdefs/uxtah_A88273.d +++ b/plugins/arm/v7/opdefs/uxtah_A88273.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title UXTAH -@desc Unsigned Extend and Add Halfword extracts a 16-bit value from a register, zero-extends it to 32 bits, adds the result to a value from another register, and writes the final result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 16-bit value. +@id 272 + +@desc { + + Unsigned Extend and Add Halfword extracts a 16-bit value from a register, zero-extends it to 32 bits, adds the result to a value from another register, and writes the final result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 16-bit value. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 0 0 0 1 Rn(4) 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?rotation> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') + } + + @asm uxtah ?reg_D reg_N reg_M ?rotation } @@ -46,20 +56,24 @@ @word cond(4) 0 1 1 0 1 1 1 1 Rn(4) Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?rotation> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') - } + } + + @asm uxtah ?reg_D reg_N reg_M ?rotation + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/uxtb16_A88275.d b/plugins/arm/v7/opdefs/uxtb16_A88275.d index a30d133..b2ac134 100644 --- a/plugins/arm/v7/opdefs/uxtb16_A88275.d +++ b/plugins/arm/v7/opdefs/uxtb16_A88275.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title UXTB16 -@desc Unsigned Extend Byte 16 extracts two 8-bit values from a register, zero-extends them to 16 bits each, and writes the results to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit values. +@id 274 + +@desc { + + Unsigned Extend Byte 16 extracts two 8-bit values from a register, zero-extends them to 16 bits each, and writes the results to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit values. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) - @syntax <reg_D> <reg_M> <?rotation> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') - reg_D = Register(Rd) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') + } + + @asm uxtb16 ?reg_D reg_M ?rotation } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 1 1 0 0 1 1 1 1 Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) - @syntax <reg_D> <reg_M> <?rotation> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') - } + } + + @asm uxtb16 ?reg_D reg_M ?rotation + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/uxtb_A88274.d b/plugins/arm/v7/opdefs/uxtb_A88274.d index f49ba83..ac5b421 100644 --- a/plugins/arm/v7/opdefs/uxtb_A88274.d +++ b/plugins/arm/v7/opdefs/uxtb_A88274.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,29 @@ @title UXTB -@desc Unsigned Extend Byte extracts an 8-bit value from a register, zero-extends it to 32 bits, and writes the result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit value. +@id 273 + +@desc { + + Unsigned Extend Byte extracts an 8-bit value from a register, zero-extends it to 32 bits, and writes the result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit value. + +} @encoding (t1) { @half 1 0 1 1 0 0 1 0 1 1 Rm(3) Rd(3) - @syntax <reg_D> <reg_M> + @syntax { + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(0) - @conv { + } - reg_D = Register(Rd) - reg_M = Register(Rm) + @asm uxtb ?reg_D reg_M ?rotation } @@ -44,13 +55,17 @@ @word 1 1 1 1 1 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) - @syntax ".W" <reg_D> <reg_M> <?rotation> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + + @asm uxtb.w ?reg_D reg_M ?rotation } @@ -60,19 +75,23 @@ @word cond(4) 0 1 1 0 1 1 1 0 1 1 1 1 Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) - @syntax <reg_D> <reg_M> <?rotation> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') - } + } + + @asm uxtb ?reg_D reg_M ?rotation + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/uxth_A88276.d b/plugins/arm/v7/opdefs/uxth_A88276.d index 5ae4f4f..b49360f 100644 --- a/plugins/arm/v7/opdefs/uxth_A88276.d +++ b/plugins/arm/v7/opdefs/uxth_A88276.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,29 @@ @title UXTH -@desc Unsigned Extend Halfword extracts a 16-bit value from a register, zero-extends it to 32 bits, and writes the result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 16-bit value. +@id 275 + +@desc { + + Unsigned Extend Halfword extracts a 16-bit value from a register, zero-extends it to 32 bits, and writes the result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 16-bit value. + +} @encoding (t1) { @half 1 0 1 1 0 0 1 0 1 0 Rm(3) Rd(3) - @syntax <reg_D> <reg_M> + @syntax { + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(0) - @conv { + } - reg_D = Register(Rd) - reg_M = Register(Rm) + @asm uxth ?reg_D reg_M ?rotation } @@ -44,13 +55,17 @@ @word 1 1 1 1 1 0 1 0 0 0 0 1 1 1 1 1 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) - @syntax ".W" <reg_D> <reg_M> <?rotation> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + + @asm uxth.w ?reg_D reg_M ?rotation } @@ -60,19 +75,23 @@ @word cond(4) 0 1 1 0 1 1 1 1 1 1 1 1 Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) - @syntax <reg_D> <reg_M> <?rotation> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') - } + } + + @asm uxth ?reg_D reg_M ?rotation + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/wfi_A88425.d b/plugins/arm/v7/opdefs/wfi_A88425.d index f11d033..0fd2552 100644 --- a/plugins/arm/v7/opdefs/wfi_A88425.d +++ b/plugins/arm/v7/opdefs/wfi_A88425.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,35 @@ @title WFI -@desc Wait For Interrupt is a hint instruction that permits the processor to enter a low-power state until one of a number of asynchronous events occurs. For more information, see Wait For Interrupt on page B1-1202. In an implementation that includes the Virtualization Extensions, if HCR.TWI is set to 1, execution of a WFI instruction in a Non-secure mode other than Hyp mode generates a Hyp Trap exception if, ignoring the value of the HCR.TWI bit, conditions permit the processor to suspend execution. For more information see Trapping use of the WFI and WFE instructions on page B1-1255. +@id 424 + +@desc { + + Wait For Interrupt is a hint instruction that permits the processor to enter a low-power state until one of a number of asynchronous events occurs. For more information, see Wait For Interrupt on page B1-1202. In an implementation that includes the Virtualization Extensions, if HCR.TWI is set to 1, execution of a WFI instruction in a Non-secure mode other than Hyp mode generates a Hyp Trap exception if, ignoring the value of the HCR.TWI bit, conditions permit the processor to suspend execution. For more information see Trapping use of the WFI and WFE instructions on page B1-1255. + +} @encoding (t1) { @half 1 0 1 1 1 1 1 1 0 0 1 1 0 0 0 0 + @syntax { + + @asm wfi + + } + } @encoding (T2) { @word 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 - @syntax ".W" + @syntax { + + @asm wfi.w + + } } @@ -43,9 +59,15 @@ @word cond(4) 0 0 1 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 - @rules { + @syntax { + + @asm wfi + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/yield_A88426.d b/plugins/arm/v7/opdefs/yield_A88426.d index 252c018..1ccee59 100644 --- a/plugins/arm/v7/opdefs/yield_A88426.d +++ b/plugins/arm/v7/opdefs/yield_A88426.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,35 @@ @title YIELD -@desc YIELD is a hint instruction. Software with a multithreading capability can use a YIELD instruction to indicate to the hardware that it is performing a task, for example a spin-lock, that could be swapped out to improve overall system performance. Hardware can use this hint to suspend and resume multiple software threads if it supports the capability. For more information about the recommended use of this instruction see The Yield instruction on page A4-178. +@id 425 + +@desc { + + YIELD is a hint instruction. Software with a multithreading capability can use a YIELD instruction to indicate to the hardware that it is performing a task, for example a spin-lock, that could be swapped out to improve overall system performance. Hardware can use this hint to suspend and resume multiple software threads if it supports the capability. For more information about the recommended use of this instruction see The Yield instruction on page A4-178. + +} @encoding (t1) { @half 1 0 1 1 1 1 1 1 0 0 0 1 0 0 0 0 + @syntax { + + @asm yield + + } + } @encoding (T2) { @word 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - @syntax ".W" + @syntax { + + @asm yield.w + + } } @@ -43,9 +59,15 @@ @word cond(4) 0 0 1 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 - @rules { + @syntax { + + @asm yield + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/operands/maccess.c b/plugins/arm/v7/operands/maccess.c index 043d801..24d5393 100644 --- a/plugins/arm/v7/operands/maccess.c +++ b/plugins/arm/v7/operands/maccess.c @@ -36,8 +36,8 @@ struct _GArmV7MAccessOperand GArchOperand *base; /* Base de l'accès en mémoire */ GArchOperand *offset; /* Décalage pour l'adresse */ - GArchOperand *shift; /* Décalage pour le décalage */ - bool not_post_indexed; /* Positio du décalage */ + GArchOperand *shift; /* Décalage pour le décallage */ + bool post_indexed; /* Position du décalage */ bool write_back; /* Mise à jour de la base */ }; @@ -194,7 +194,7 @@ static int g_armv7_maccess_operand_compare(const GArmV7MAccessOperand *a, const result = sort_pointer(a->shift, b->shift, (__compar_fn_t)g_arch_operand_compare); if (result != 0) goto gamoc_done; - result = sort_boolean(a->not_post_indexed, b->not_post_indexed); + result = sort_boolean(a->post_indexed, b->post_indexed); if (result != 0) goto gamoc_done; result = sort_boolean(a->write_back, b->write_back); @@ -226,7 +226,7 @@ static void g_armv7_maccess_operand_print(const GArmV7MAccessOperand *operand, G g_arch_operand_print(operand->base, line, syntax); - if (!operand->not_post_indexed) + if (operand->post_indexed) g_buffer_line_append_text(line, BLC_ASSEMBLY, "]", 1, RTT_HOOK, NULL); if (operand->offset != NULL) @@ -247,7 +247,7 @@ static void g_armv7_maccess_operand_print(const GArmV7MAccessOperand *operand, G } - if (operand->not_post_indexed) + if (!operand->post_indexed) g_buffer_line_append_text(line, BLC_ASSEMBLY, "]", 1, RTT_HOOK, NULL); if (operand->write_back) @@ -258,11 +258,19 @@ static void g_armv7_maccess_operand_print(const GArmV7MAccessOperand *operand, G /****************************************************************************** * * +<<<<<<< HEAD * Paramètres : base = représente le registre de la base d'accès. * * offset = détermine le décalage entre l'adresse et la base. * * shift = opération de décalage pour jouer sur le décalage. * * indexed = précise la forme donnée au décalage à appliquer. * * wback = indique une mise à jour de la base après usage. * +======= +* Paramètres : base = représente le registre de la base d'accès. * +* offset = détermine le décallage entre l'adresse et la base. * +* shift = opération de décallage pour jouer sur le décallage. * +* post = précise la forme donnée au décallage à appliquer. * +* wback = indique une mise à jour de la base après usage. * +>>>>>>> Rewritten the whole instruction definition format. * * * Description : Crée un accès à la mémoire depuis une base et un décalage. * * * @@ -272,7 +280,7 @@ static void g_armv7_maccess_operand_print(const GArmV7MAccessOperand *operand, G * * ******************************************************************************/ -GArchOperand *g_armv7_maccess_operand_new(GArchOperand *base, GArchOperand *offset, GArchOperand *shift, bool indexed, bool wback) +GArchOperand *g_armv7_maccess_operand_new(GArchOperand *base, GArchOperand *offset, GArchOperand *shift, bool post, bool wback) { GArmV7MAccessOperand *result; /* Structure à retourner */ @@ -282,7 +290,7 @@ GArchOperand *g_armv7_maccess_operand_new(GArchOperand *base, GArchOperand *offs result->offset = offset; result->shift = shift; - result->not_post_indexed = indexed; + result->post_indexed = post; result->write_back = wback; return G_ARCH_OPERAND(result); @@ -361,7 +369,7 @@ GArchOperand *g_armv7_maccess_operand_get_shift(const GArmV7MAccessOperand *oper bool g_armv7_maccess_operand_is_post_indexed(const GArmV7MAccessOperand *operand) { - return !operand->not_post_indexed; + return operand->post_indexed; } diff --git a/plugins/arm/v7/operands/reglist.c b/plugins/arm/v7/operands/reglist.c index 00c3b98..1f56249 100644 --- a/plugins/arm/v7/operands/reglist.c +++ b/plugins/arm/v7/operands/reglist.c @@ -255,7 +255,7 @@ static void g_armv7_reglist_operand_print(const GArmV7RegListOperand *operand, G /****************************************************************************** * * -* Paramètres : - * +* Paramètres : selected = masque de bits pour les registres à intégrer. * * * * Description : Crée une liste vierge de registres ARM. * * * @@ -265,48 +265,24 @@ static void g_armv7_reglist_operand_print(const GArmV7RegListOperand *operand, G * * ******************************************************************************/ -GArchOperand *g_armv7_reglist_operand_new(void) -{ - GArchOperand *result; /* Structure à retourner */ - - result = g_object_new(G_TYPE_ARMV7_REGLIST_OPERAND, NULL); - - return G_ARCH_OPERAND(result); - -} - - -/****************************************************************************** -* * -* Paramètres : operand = liste de registres à compléter. * -* selected = masque de bits pour les registres à intégrer. * -* * -* Description : Remplit une liste de registres de registres ARM. * -* * -* Retour : Bilan de l'opération. * -* * -* Remarques : - * -* * -******************************************************************************/ - -bool g_armv7_reglist_load_registers(GArmV7RegListOperand *operand, uint32_t selected) +GArchOperand *g_armv7_reglist_operand_new(uint16_t selected) { + GArmV7RegListOperand *result; /* Structure à retourner */ uint8_t i; /* Boucle de parcours */ GArmV7Register *reg; /* Nouveau registre à intégrer */ - for (i = 18; i < 32; i++) - if (selected & (1 << i)) return false; + result = g_object_new(G_TYPE_ARMV7_REGLIST_OPERAND, NULL); - for (i = 0; i < 18; i++) + for (i = 0; i < 16; i++) { if ((selected & (1 << i)) == 0) continue; reg = g_armv7_register_new(i); - g_armv7_reglist_add_register(operand, reg); + g_armv7_reglist_add_register(result, reg); } - return true; + return G_ARCH_OPERAND(result); } diff --git a/plugins/arm/v7/operands/reglist.h b/plugins/arm/v7/operands/reglist.h index 60b78a6..82f1a60 100644 --- a/plugins/arm/v7/operands/reglist.h +++ b/plugins/arm/v7/operands/reglist.h @@ -55,10 +55,7 @@ typedef struct _GArmV7RegListOperandClass GArmV7RegListOperandClass; GType g_armv7_reglist_operand_get_type(void); /* Crée une liste vierge de registres ARM. */ -GArchOperand *g_armv7_reglist_operand_new(void); - -/* Remplit une liste de registres de registres ARM. */ -bool g_armv7_reglist_load_registers(GArmV7RegListOperand *, uint32_t); +GArchOperand *g_armv7_reglist_operand_new(uint16_t); /* Ajoute un registre à une liste de registres ARM. */ void g_armv7_reglist_add_register(GArmV7RegListOperand *, GArmV7Register *); diff --git a/plugins/arm/v7/pseudo.c b/plugins/arm/v7/pseudo.c index e560f5d..12ad50b 100644 --- a/plugins/arm/v7/pseudo.c +++ b/plugins/arm/v7/pseudo.c @@ -483,7 +483,7 @@ bool armv7_thumb_expand_imm(uint32_t imm12, uint32_t *value) * * ******************************************************************************/ -bool armv7_decode_imm_shift(uint8_t type2, uint8_t imm5, SRType *type, uint32_t *value) +bool armv7_decode_imm_shift(uint8_t type2, uint8_t imm5, SRType *type, uint8_t *value) { bool result; /* Bilan à retourner */ @@ -681,3 +681,50 @@ uint32_t armv7_zero_extend(uint32_t x, unsigned int n, unsigned int i) return x; } + + +/****************************************************************************** +* * +* Paramètres : x = valeur sur 32 bits maximum à traiter. * +* t = bit de poids nombre de bits à prendre en compte. * +* i = taille finale à obtenir. * +* * +* Description : Fournit une aide pour la fonction 'SignExtend'. * +* * +* Retour : Nouvelle valeur calculée. * +* * +* Remarques : - * +* * +******************************************************************************/ + +uint32_t armv7_sign_extend(uint32_t x, unsigned int t, unsigned int i) +{ + uint32_t result; /* Valeur à retourner */ + bool set; /* Bit de poids fort à 1 ? */ + unsigned int k; /* Boucle de parcours */ + + result = 0; + + set = (x & (1 << t)); + + switch (i) + { + +#define SIGN_EXTEND_CASE(sz) \ + case sz: \ + result = x; \ + if (set) \ + for (k = t + 1; k < sz; k++) \ + result |= (1 << k); \ + break; + + SIGN_EXTEND_CASE(4); + SIGN_EXTEND_CASE(8); + SIGN_EXTEND_CASE(16); + SIGN_EXTEND_CASE(32); + + } + + return result; + +} diff --git a/plugins/arm/v7/pseudo.h b/plugins/arm/v7/pseudo.h index c918d57..d070bcd 100644 --- a/plugins/arm/v7/pseudo.h +++ b/plugins/arm/v7/pseudo.h @@ -110,7 +110,7 @@ typedef enum _SRType /* Traduit la fonction 'DecodeImmShift'. */ -bool armv7_decode_imm_shift(uint8_t, uint8_t, SRType *, uint32_t *); +bool armv7_decode_imm_shift(uint8_t, uint8_t, SRType *, uint8_t *); /* Traduit la fonction 'DecodeRegShift'. */ bool armv7_decode_reg_shift(uint8_t, SRType *); @@ -131,6 +131,9 @@ bool armv7_shift(uint32_t, unsigned int, SRType, unsigned int, bool, uint32_t *) /* Traduit la fonction 'ZeroExtend'. */ uint32_t armv7_zero_extend(uint32_t, unsigned int, unsigned int); +/* Fournit une aide pour la fonction 'SignExtend'. */ +uint32_t armv7_sign_extend(uint32_t, unsigned int, unsigned int); + #endif /* _PLUGINS_ARM_V7_PSEUDO_H */ |