1 files changed, 53 insertions, 12 deletions
diff --git a/plugins/arm/v7/opdefs/add_A8811.d b/plugins/arm/v7/opdefs/add_A8811.d
index 5b6c0d1..e70c33c 100644
--- a/plugins/arm/v7/opdefs/add_A8811.d
+++ b/plugins/arm/v7/opdefs/add_A8811.d
@@ -2,7 +2,7 @@
 /* Chrysalide - Outil d'analyse de fichiers binaires
  * ##FILE## - traduction d'instructions ARMv7
  *
- * Copyright (C) 2015 Cyrille Bagard
+ * Copyright (C) 2017 Cyrille Bagard
  *
  *  This file is part of Chrysalide.
  *
@@ -23,28 +23,69 @@
 
 @title ADD (SP plus register, ARM)
 
-@desc This instruction adds an optionally-shifted register value to the SP value, and writes the result to the destination register.
+@id 10
+
+@desc {
+
+	This instruction adds an optionally-shifted register value to the SP value, and writes the result to the destination register.
+
+}
 
 @encoding (A1) {
 
 	@word cond(4) 0 0 0 0 1 0 0 S(1) 1 1 0 1 Rd(4) imm5(5) type(2) 0 Rm(4)
 
-	@syntax <reg_D> <SP> <reg_M> <?shift>
+	@syntax {
+
+		@assert {
+
+			S == 0
+
+		}
+
+		@conv {
+
+			reg_D = Register(Rd)
+			reg_SP = Register(13)
+			reg_M = Register(Rm)
+			shift = DecodeImmShift(type, imm5)
+
+		}
+
+		@asm add ?reg_D reg_SP reg_M ?shift
 
-	@conv {
+		@rules {
 
-		reg_D = Register(Rd)
-		reg_M = Register(Rm)
-		setflags = (S == '1')
-		shift = DecodeImmShift(type, imm5)
-		SP = Register(13)
+			check g_arm_instruction_set_cond(cond)
+
+		}
 
 	}
 
-	@rules {
+	@syntax {
+
+		@assert {
+
+			S == 1
+
+		}
+
+		@conv {
+
+			reg_D = Register(Rd)
+			reg_SP = Register(13)
+			reg_M = Register(Rm)
+			shift = DecodeImmShift(type, imm5)
+
+		}
+
+		@asm adds ?reg_D reg_SP reg_M ?shift
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
 
-		if (setflags); chk_call ExtendKeyword("s")
-		chk_call StoreCondition(cond)
+		}
 
 	}