diff options
Diffstat (limited to 'plugins/arm/v7/opdefs/adr_A8812.d')
| -rw-r--r-- | plugins/arm/v7/opdefs/adr_A8812.d | 82 |
1 files changed, 54 insertions, 28 deletions
diff --git a/plugins/arm/v7/opdefs/adr_A8812.d b/plugins/arm/v7/opdefs/adr_A8812.d index 16615cb..ee5ed75 100644 --- a/plugins/arm/v7/opdefs/adr_A8812.d +++ b/plugins/arm/v7/opdefs/adr_A8812.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title ADR -@desc This instruction adds an immediate value to the PC value to form a PC-relative address, and writes the result to the destination register. +@id 11 + +@desc { + + This instruction adds an immediate value to the PC value to form a PC-relative address, and writes the result to the destination register. + +} @encoding (t1) { @half 1 0 1 0 0 Rd(3) imm8(8) - @syntax <reg_D> <imm32> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - imm32 = ZeroExtend(imm8:'00', 32) + reg_D = Register(Rd) + imm32 = ZeroExtend(imm8:'00', 32) + + } + + @asm adr reg_D imm32 } @@ -44,12 +54,16 @@ @word 1 1 1 1 0 i(1) 1 0 1 0 1 0 1 1 1 1 0 imm3(3) Rd(4) imm8(8) - @syntax ".W" <reg_D> <imm32> + @syntax { + + @conv { + + reg_D = Register(Rd) + imm32 = ZeroExtend(i:imm3:imm8, 32) - @conv { + } - reg_D = Register(Rd) - imm32 = ZeroExtend(i:imm3:imm8, 32) + @asm adr.w reg_D imm32 } @@ -59,12 +73,16 @@ @word 1 1 1 1 0 i(1) 1 0 0 0 0 0 1 1 1 1 0 imm3(3) Rd(4) imm8(8) - @syntax ".W" <reg_D> <imm32> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - imm32 = ZeroExtend(i:imm3:imm8, 32) + reg_D = Register(Rd) + imm32 = ZeroExtend(i:imm3:imm8, 32) + + } + + @asm adr.w reg_D imm32 } @@ -74,18 +92,22 @@ @word cond(4) 0 0 1 0 1 0 0 0 1 1 1 1 Rd(4) imm12(12) - @syntax <reg_D> <imm32> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - imm32 = ARMExpandImm(imm12) + reg_D = Register(Rd) + imm32 = ARMExpandImm(imm12) - } + } + + @asm adr reg_D imm32 - @rules { + @rules { - chk_call StoreCondition(cond) + check g_arm_instruction_set_cond(cond) + + } } @@ -95,18 +117,22 @@ @word cond(4) 0 0 1 0 0 1 0 0 1 1 1 1 Rd(4) imm12(12) - @syntax <reg_D> <imm32> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - imm32 = ARMExpandImm(imm12) + reg_D = Register(Rd) + imm32 = ARMExpandImm(imm12) - } + } + + @asm adr reg_D imm32 + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } |