1 files changed, 91 insertions, 25 deletions
diff --git a/plugins/arm/v7/opdefs/asr_A8816.d b/plugins/arm/v7/opdefs/asr_A8816.d
index 006a26c..87d4b3e 100644
--- a/plugins/arm/v7/opdefs/asr_A8816.d
+++ b/plugins/arm/v7/opdefs/asr_A8816.d
@@ -2,7 +2,7 @@
 /* Chrysalide - Outil d'analyse de fichiers binaires
  * ##FILE## - traduction d'instructions ARMv7
  *
- * Copyright (C) 2015 Cyrille Bagard
+ * Copyright (C) 2017 Cyrille Bagard
  *
  *  This file is part of Chrysalide.
  *
@@ -23,19 +23,29 @@
 
 @title ASR (immediate)
 
-@desc Arithmetic Shift Right (immediate) shifts a register value right by an immediate number of bits, shifting in copies of its sign bit, and writes the result to the destination register. It can optionally update the condition flags based on the result.
+@id 15
+
+@desc {
+
+	Arithmetic Shift Right (immediate) shifts a register value right by an immediate number of bits, shifting in copies of its sign bit, and writes the result to the destination register. It can optionally update the condition flags based on the result.
+
+}
 
 @encoding (t1) {
 
 	@half 0 0 0 1 0 imm5(5) Rm(3) Rd(3)
 
-	@syntax "asrs" <reg_D> <reg_M> <shift_imm>
+	@syntax {
+
+		@conv {
 
-	@conv {
+			reg_D = Register(Rd)
+			reg_M = Register(Rm)
+			shift_n = DecodeImmShiftAmount('10', imm5)
 
-		reg_D = Register(Rd)
-		reg_M = Register(Rm)
-		shift_imm = DecodeImmShift('10', imm5)
+		}
+
+		@asm asr ?reg_D reg_M shift_n
 
 	}
 
@@ -45,21 +55,43 @@
 
 	@word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm2(2) 1 0 Rm(4)
 
-	@syntax <reg_D> <reg_M> <shift_imm>
+	@syntax {
+
+		@assert {
+
+			S == 0
+
+		}
 
-	@conv {
+		@conv {
 
-		reg_D = Register(Rd)
-		reg_M = Register(Rm)
-		setflags = (S == '1')
-		shift_imm = DecodeImmShift('10', imm3:imm2)
+			reg_D = Register(Rd)
+			reg_M = Register(Rm)
+			shift_n = DecodeImmShiftAmount('10', imm3:imm2)
+
+		}
+
+		@asm asr.w ?reg_D reg_M shift_n
 
 	}
 
-	@rules {
+	@syntax {
+
+		@assert {
+
+			S == 1
+
+		}
+
+		@conv {
+
+			reg_D = Register(Rd)
+			reg_M = Register(Rm)
+			shift_n = DecodeImmShiftAmount('10', imm3:imm2)
+
+		}
 
-		if (setflags); chk_call ExtendKeyword("s")
-		chk_call ExtendKeyword(".w")
+		@asm asrs.w ?reg_D reg_M shift_n
 
 	}
 
@@ -69,21 +101,55 @@
 
 	@word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) imm5(5) 1 0 0 Rm(4)
 
-	@syntax <reg_D> <reg_M> <shift_imm>
+	@syntax {
 
-	@conv {
+		@assert {
 
-		reg_D = Register(Rd)
-		reg_M = Register(Rm)
-		setflags = (S == '1')
-		shift_imm = DecodeImmShift('10', imm5)
+			S == 0
+
+		}
+
+		@conv {
+
+			reg_D = Register(Rd)
+			reg_M = Register(Rm)
+			shift_n = DecodeImmShiftAmount('10', imm5)
+
+		}
+
+		@asm asr ?reg_D reg_M shift_n
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
+
+		}
 
 	}
 
-	@rules {
+	@syntax {
+
+		@assert {
+
+			S == 1
+
+		}
+
+		@conv {
+
+			reg_D = Register(Rd)
+			reg_M = Register(Rm)
+			shift_n = DecodeImmShiftAmount('10', imm5)
+
+		}
+
+		@asm asrs ?reg_D reg_M shift_n
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
 
-		if (setflags); chk_call ExtendKeyword("s")
-		chk_call StoreCondition(cond)
+		}
 
 	}