diff options
Diffstat (limited to 'plugins/arm/v7/opdefs/bl_A8825.d')
| -rw-r--r-- | plugins/arm/v7/opdefs/bl_A8825.d | 60 |
1 files changed, 39 insertions, 21 deletions
diff --git a/plugins/arm/v7/opdefs/bl_A8825.d b/plugins/arm/v7/opdefs/bl_A8825.d index da0def4..f584f0b 100644 --- a/plugins/arm/v7/opdefs/bl_A8825.d +++ b/plugins/arm/v7/opdefs/bl_A8825.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,27 @@ @title BL, BLX (immediate) -@desc Branch with Link calls a subroutine at a PC-relative address. Branch with Link and Exchange Instruction Sets (immediate) calls a subroutine at a PC-relative address, and changes instruction set from ARM to Thumb, or from Thumb to ARM. +@id 24 + +@desc { + + Branch with Link calls a subroutine at a PC-relative address. Branch with Link and Exchange Instruction Sets (immediate) calls a subroutine at a PC-relative address, and changes instruction set from ARM to Thumb, or from Thumb to ARM. + +} @encoding (T1) { @word 1 1 1 1 0 S(1) imm10(10) 1 1 J1(1) 1 J2(1) imm11(11) - @syntax <imm32> + @syntax { - @conv { + @conv { - I1 = NOT(J1 EOR S) - I2 = NOT(J2 EOR S) - imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', S & 0x1, 32) + imm32 = SignExtend(S:J2:J1:imm10:imm11:'0', 32, 24) + + } + + @asm bl imm32 } @@ -53,13 +61,15 @@ @word 1 1 1 1 0 S(1) imm10H(10) 1 1 J1(1) 0 J2(1) imm10L(10) H(1) - @syntax "blx" <imm32> + @syntax { + + @conv { - @conv { + imm32 = SignExtend(S:J1:J2:imm10H:imm10L:'00', 32, 24) - I1 = NOT(J1 EOR S) - I2 = NOT(J2 EOR S) - imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', S & 0x1, 32) + } + + @asm blx imm32 } @@ -77,17 +87,21 @@ @word cond(4) 1 0 1 1 imm24(24) - @syntax <imm32> + @syntax { - @conv { + @conv { - imm32 = SignExtend(imm24:'00', imm24 & 0x800000, 32) + imm32 = SignExtend(imm24:'00', 32, 25) - } + } + + @asm bl imm32 - @rules { + @rules { - chk_call StoreCondition(cond) + check g_arm_instruction_set_cond(cond) + + } } @@ -105,11 +119,15 @@ @word 1 1 1 1 1 0 1 H(1) imm24(24) - @syntax "blx" <imm32> + @syntax { + + @conv { + + imm32 = SignExtend(imm24:H:'0', 32, 25) - @conv { + } - imm32 = SignExtend(imm24:H:'0', imm24 & 0x800000, 32) + @asm blx imm32 } |