diff options
Diffstat (limited to 'plugins/arm/v7/opdefs/bxj_A8828.d')
| -rw-r--r-- | plugins/arm/v7/opdefs/bxj_A8828.d | 36 |
1 files changed, 25 insertions, 11 deletions
diff --git a/plugins/arm/v7/opdefs/bxj_A8828.d b/plugins/arm/v7/opdefs/bxj_A8828.d index efa2de2..0716a31 100644 --- a/plugins/arm/v7/opdefs/bxj_A8828.d +++ b/plugins/arm/v7/opdefs/bxj_A8828.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,17 +23,27 @@ @title BXJ -@desc Branch and Exchange Jazelle attempts to change to Jazelle state. If the attempt fails, it branches to an address and instruction set specified by a register as though it were a BX instruction. In an implementation that includes the Virtualization Extensions, if HSTR.TJDBX is set to 1, execution of a BXJ instruction in a Non-secure mode other than Hyp mode generates a Hyp Trap exception. For more information see Trapping accesses to Jazelle functionality on page B1-1255. +@id 27 + +@desc { + + Branch and Exchange Jazelle attempts to change to Jazelle state. If the attempt fails, it branches to an address and instruction set specified by a register as though it were a BX instruction. In an implementation that includes the Virtualization Extensions, if HSTR.TJDBX is set to 1, execution of a BXJ instruction in a Non-secure mode other than Hyp mode generates a Hyp Trap exception. For more information see Trapping accesses to Jazelle functionality on page B1-1255. + +} @encoding (T1) { @word 1 1 1 1 0 0 1 1 1 1 0 0 Rm(4) 1 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 - @syntax <reg_M> + @syntax { + + @conv { - @conv { + reg_M = Register(Rm) - reg_M = Register(Rm) + } + + @asm bxj reg_M } @@ -43,17 +53,21 @@ @word cond(4) 0 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 Rm(4) - @syntax <reg_M> + @syntax { - @conv { + @conv { - reg_M = Register(Rm) + reg_M = Register(Rm) - } + } + + @asm bxj reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } |