1 files changed, 83 insertions, 13 deletions
diff --git a/plugins/arm/v7/opdefs/ldr_A8863.d b/plugins/arm/v7/opdefs/ldr_A8863.d
index 0d0ce1f..3e1b255 100644
--- a/plugins/arm/v7/opdefs/ldr_A8863.d
+++ b/plugins/arm/v7/opdefs/ldr_A8863.d
@@ -2,7 +2,7 @@
 /* Chrysalide - Outil d'analyse de fichiers binaires
  * ##FILE## - traduction d'instructions ARMv7
  *
- * Copyright (C) 2015 Cyrille Bagard
+ * Copyright (C) 2017 Cyrille Bagard
  *
  *  This file is part of Chrysalide.
  *
@@ -23,29 +23,99 @@
 
 @title LDR (immediate, ARM)
 
-@desc Load Register (immediate) calculates an address from a base register value and an immediate offset, loads a word from memory, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294.
+@id 62
+
+@desc {
+
+	Load Register (immediate) calculates an address from a base register value and an immediate offset, loads a word from memory, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294.
+
+}
 
 @encoding (A1) {
 
 	@word cond(4) 0 1 0 P(1) U(1) 0 W(1) 1 Rn(4) Rt(4) imm12(12)
 
-	@syntax <reg_T> <mem_access>
+	@syntax {
+
+		@assert {
+
+			P == 1
+			P == 1 && W == 0
+
+		}
+
+		@conv {
+
+			reg_T = Register(Rt)
+			reg_N = Register(Rn)
+			imm32 = ZeroExtend(imm12, 32)
+			maccess = MemAccessOffset(reg_N, imm32)
+
+		}
+
+		@asm ldr reg_T maccess
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
+
+		}
+
+	}
+
+	@syntax {
 
-	@conv {
+		@assert {
 
-		reg_T = Register(Rt)
-		reg_N = Register(Rn)
-		imm32 = ZeroExtend(imm12, 32)
-		index = (P == '1')
-		add = (U == '1')
-		wback = (P == '0') || (W == '1')
-		mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback)
+			P == 1
+			P == 0 || W == 1
+
+		}
+
+		@conv {
+
+			reg_T = Register(Rt)
+			reg_N = Register(Rn)
+			imm32 = ZeroExtend(imm12, 32)
+			maccess = MemAccessPreIndexed(reg_N, imm32)
+
+		}
+
+		@asm ldr reg_T maccess
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
+
+		}
 
 	}
 
-	@rules {
+	@syntax {
+
+		@assert {
+
+			P == 0
+			P == 0 || W == 1
+
+		}
+
+		@conv {
+
+			reg_T = Register(Rt)
+			reg_N = Register(Rn)
+			imm32 = ZeroExtend(imm12, 32)
+			maccess = MemAccessPostIndexed(reg_N, imm32)
+
+		}
+
+		@asm ldr reg_T maccess
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
 
-		chk_call StoreCondition(cond)
+		}
 
 	}