diff options
Diffstat (limited to 'plugins/arm/v7/opdefs/ldr_A8864.d')
| -rw-r--r-- | plugins/arm/v7/opdefs/ldr_A8864.d | 52 |
1 files changed, 35 insertions, 17 deletions
diff --git a/plugins/arm/v7/opdefs/ldr_A8864.d b/plugins/arm/v7/opdefs/ldr_A8864.d index 74afa2d..7c78df5 100644 --- a/plugins/arm/v7/opdefs/ldr_A8864.d +++ b/plugins/arm/v7/opdefs/ldr_A8864.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title LDR (literal) -@desc Load Register (literal) calculates an address from the PC value and an immediate offset, loads a word from memory, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. +@id 63 + +@desc { + + Load Register (literal) calculates an address from the PC value and an immediate offset, loads a word from memory, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (t1) { @half 0 1 0 0 1 Rt(3) imm8(8) - @syntax <reg_T> <imm32> + @syntax { + + @conv { + + reg_T = Register(Rt) + imm32 = ZeroExtend(imm8:'00', 32) - @conv { + } - reg_T = Register(Rt) - imm32 = ZeroExtend(imm8:'00', 32) + @asm ldr reg_T imm32 } @@ -51,12 +61,16 @@ @word 1 1 1 1 1 0 0 0 U(1) 1 0 1 1 1 1 1 Rt(4) imm12(12) - @syntax ".W" <reg_T> <imm32> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - imm32 = ZeroExtend(imm12, 32) + reg_T = Register(Rt) + imm32 = ZeroExtend(imm12, 32) + + } + + @asm ldr.w reg_T imm32 } @@ -73,18 +87,22 @@ @word cond(4) 0 1 0 1 U(1) 0 0 1 1 1 1 1 Rt(4) imm12(12) - @syntax <reg_T> <imm32> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - imm32 = ZeroExtend(imm12, 32) + reg_T = Register(Rt) + imm32 = ZeroExtend(imm12, 32) - } + } + + @asm ldr reg_T imm32 + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } |