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-rw-r--r--plugins/arm/v7/opdefs/ldrsb_A8886.d130
1 files changed, 104 insertions, 26 deletions
diff --git a/plugins/arm/v7/opdefs/ldrsb_A8886.d b/plugins/arm/v7/opdefs/ldrsb_A8886.d
index 4a66278..e7da94f 100644
--- a/plugins/arm/v7/opdefs/ldrsb_A8886.d
+++ b/plugins/arm/v7/opdefs/ldrsb_A8886.d
@@ -2,7 +2,7 @@
/* Chrysalide - Outil d'analyse de fichiers binaires
* ##FILE## - traduction d'instructions ARMv7
*
- * Copyright (C) 2015 Cyrille Bagard
+ * Copyright (C) 2017 Cyrille Bagard
*
* This file is part of Chrysalide.
*
@@ -23,20 +23,30 @@
@title LDRSB (register)
-@desc Load Register Signed Byte (register) calculates an address from a base register value and an offset register value, loads a byte from memory, sign-extends it to form a 32-bit word, and writes it to a register. The offset register value can be shifted left by 0, 1, 2, or 3 bits. For information about memory accesses see Memory accesses on page A8-294.
+@id 85
+
+@desc {
+
+ Load Register Signed Byte (register) calculates an address from a base register value and an offset register value, loads a byte from memory, sign-extends it to form a 32-bit word, and writes it to a register. The offset register value can be shifted left by 0, 1, 2, or 3 bits. For information about memory accesses see Memory accesses on page A8-294.
+
+}
@encoding (t1) {
@half 0 1 0 1 0 1 1 Rm(3) Rn(3) Rt(3)
- @syntax <reg_T> <mem_access>
+ @syntax {
+
+ @conv {
- @conv {
+ reg_T = Register(Rt)
+ reg_N = Register(Rn)
+ reg_M = Register(Rm)
+ maccess = MemAccessOffset(reg_N, reg_M)
- reg_T = Register(Rt)
- reg_N = Register(Rn)
- reg_M = Register(Rm)
- mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, true, true, false)
+ }
+
+ @asm ldrsb reg_T maccess
}
@@ -46,15 +56,19 @@
@word 1 1 1 1 1 0 0 1 0 0 0 1 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4)
- @syntax ".W" <reg_T> <mem_access>
+ @syntax {
+
+ @conv {
+
+ reg_T = Register(Rt)
+ reg_N = Register(Rn)
+ reg_M = Register(Rm)
+ shift = FixedShift(SRType_LSL, imm2)
+ maccess = MemAccessOffsetExtended(reg_N, reg_M, shift)
- @conv {
+ }
- reg_T = Register(Rt)
- reg_N = Register(Rn)
- reg_M = Register(Rm)
- shift = DecodeImmShift(0, imm2)
- mem_access = MakeMemoryAccess(reg_N, reg_M, shift, true, true, false)
+ @asm ldrsb.w reg_T maccess
}
@@ -64,23 +78,87 @@
@word cond(4) 0 0 0 P(1) U(1) 0 W(1) 1 Rn(4) Rt(4) 0 0 0 0 1 1 0 1 Rm(4)
- @syntax <reg_T> <mem_access>
+ @syntax {
+
+ @assert {
+
+ P == 1
+ P == 1 && W == 0
+
+ }
+
+ @conv {
+
+ reg_T = Register(Rt)
+ reg_N = Register(Rn)
+ reg_M = Register(Rm)
+ maccess = MemAccessOffset(reg_N, reg_M)
+
+ }
+
+ @asm ldrsb reg_T maccess
+
+ @rules {
+
+ check g_arm_instruction_set_cond(cond)
+
+ }
+
+ }
+
+ @syntax {
+
+ @assert {
+
+ P == 1
+ P == 0 || W == 1
+
+ }
+
+ @conv {
+
+ reg_T = Register(Rt)
+ reg_N = Register(Rn)
+ reg_M = Register(Rm)
+ maccess = MemAccessPreIndexed(reg_N, reg_M)
+
+ }
+
+ @asm ldrsb reg_T maccess
+
+ @rules {
- @conv {
+ check g_arm_instruction_set_cond(cond)
- reg_T = Register(Rt)
- reg_N = Register(Rn)
- reg_M = Register(Rm)
- index = (P == '1')
- add = (U == '1')
- wback = (P == '0') || (W == '1')
- mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, index, add, wback)
+ }
}
- @rules {
+ @syntax {
+
+ @assert {
+
+ P == 0
+ P == 0 || W == 1
+
+ }
+
+ @conv {
+
+ reg_T = Register(Rt)
+ reg_N = Register(Rn)
+ reg_M = Register(Rm)
+ maccess = MemAccessPostIndexed(reg_N, reg_M)
+
+ }
+
+ @asm ldrsb reg_T maccess
+
+ @rules {
+
+ check g_arm_instruction_set_cond(cond)
- chk_call StoreCondition(cond)
+ }
}