diff options
Diffstat (limited to 'plugins/arm/v7/opdefs/ldrsh_A8889.d')
| -rw-r--r-- | plugins/arm/v7/opdefs/ldrsh_A8889.d | 40 |
1 files changed, 27 insertions, 13 deletions
diff --git a/plugins/arm/v7/opdefs/ldrsh_A8889.d b/plugins/arm/v7/opdefs/ldrsh_A8889.d index 074cd5c..ae8e458 100644 --- a/plugins/arm/v7/opdefs/ldrsh_A8889.d +++ b/plugins/arm/v7/opdefs/ldrsh_A8889.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title LDRSH (literal) -@desc Load Register Signed Halfword (literal) calculates an address from the PC value and an immediate offset, loads a halfword from memory, sign-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. +@id 88 + +@desc { + + Load Register Signed Halfword (literal) calculates an address from the PC value and an immediate offset, loads a halfword from memory, sign-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (T1) { @word 1 1 1 1 1 0 0 1 U(1) 0 1 1 1 1 1 1 Rt(4) imm12(12) - @syntax <reg_T> <imm32> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + imm32 = ZeroExtend(imm12, 32) - reg_T = Register(Rt) - imm32 = ZeroExtend(imm12, 32) + } + + @asm ldrsh reg_T imm32 } @@ -44,18 +54,22 @@ @word cond(4) 0 0 0 1 U(1) 1 0 1 1 1 1 1 Rt(4) imm4H(4) 1 1 1 1 imm4L(4) - @syntax <reg_T> <imm32> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - imm32 = ZeroExtend(imm4H:imm4L, 32) + reg_T = Register(Rt) + imm32 = ZeroExtend(imm4H:imm4L, 32) - } + } + + @asm ldrsh reg_T imm32 + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } |