diff options
Diffstat (limited to 'plugins/arm/v7/opdefs/ldrt_A8892.d')
| -rw-r--r-- | plugins/arm/v7/opdefs/ldrt_A8892.d | 74 |
1 files changed, 45 insertions, 29 deletions
diff --git a/plugins/arm/v7/opdefs/ldrt_A8892.d b/plugins/arm/v7/opdefs/ldrt_A8892.d index e13f0e7..aa92cad 100644 --- a/plugins/arm/v7/opdefs/ldrt_A8892.d +++ b/plugins/arm/v7/opdefs/ldrt_A8892.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title LDRT -@desc Load Register Unprivileged loads a word from memory, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. LDRT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or an optionally-shifted register value. +@id 91 + +@desc { + + Load Register Unprivileged loads a word from memory, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. LDRT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or an optionally-shifted register value. + +} @encoding (T1) { @word 1 1 1 1 1 0 0 0 0 1 0 1 Rn(4) Rt(4) 1 1 1 0 imm8(8) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + @asm ldrt reg_T maccess } @@ -46,21 +56,24 @@ @word cond(4) 0 1 0 0 U(1) 0 1 1 Rn(4) Rt(4) imm12(12) - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_N = Register(Rn) - add = (U == '1') - imm32 = ZeroExtend(imm12, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, false, add, false) + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) - } + } + + @asm ldrt reg_T maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } @@ -70,22 +83,25 @@ @word cond(4) 0 1 1 0 U(1) 0 1 1 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - add = (U == '1') - shift = DecodeImmShift(type, imm5) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, false, add, false) + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessPostIndexedExtended(reg_N, reg_M, shift) - } + } + + @asm ldrt reg_T maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } |