1 files changed, 91 insertions, 25 deletions
diff --git a/plugins/arm/v7/opdefs/lsr_A8896.d b/plugins/arm/v7/opdefs/lsr_A8896.d
index acb9e25..3ee0473 100644
--- a/plugins/arm/v7/opdefs/lsr_A8896.d
+++ b/plugins/arm/v7/opdefs/lsr_A8896.d
@@ -2,7 +2,7 @@
 /* Chrysalide - Outil d'analyse de fichiers binaires
  * ##FILE## - traduction d'instructions ARMv7
  *
- * Copyright (C) 2015 Cyrille Bagard
+ * Copyright (C) 2017 Cyrille Bagard
  *
  *  This file is part of Chrysalide.
  *
@@ -23,19 +23,29 @@
 
 @title LSR (immediate)
 
-@desc Logical Shift Right (immediate) shifts a register value right by an immediate number of bits, shifting in zeros, and writes the result to the destination register. It can optionally update the condition flags based on the result.
+@id 95
+
+@desc {
+
+	Logical Shift Right (immediate) shifts a register value right by an immediate number of bits, shifting in zeros, and writes the result to the destination register. It can optionally update the condition flags based on the result.
+
+}
 
 @encoding (t1) {
 
 	@half 0 0 0 0 1 imm5(5) Rm(3) Rd(3)
 
-	@syntax "lsrs" <reg_D> <reg_M> <shift_imm>
+	@syntax {
+
+		@conv {
 
-	@conv {
+			reg_D = Register(Rd)
+			reg_M = Register(Rm)
+			shift_n = DecodeImmShiftAmount('01', imm5)
 
-		reg_D = Register(Rd)
-		reg_M = Register(Rm)
-		shift_imm = DecodeImmShift('01', imm5)
+		}
+
+		@asm lsr ?reg_D reg_M shift_n
 
 	}
 
@@ -45,21 +55,43 @@
 
 	@word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm2(2) 0 1 Rm(4)
 
-	@syntax <reg_D> <reg_M> <shift_imm>
+	@syntax {
+
+		@assert {
+
+			S == 0
+
+		}
 
-	@conv {
+		@conv {
 
-		reg_D = Register(Rd)
-		reg_M = Register(Rm)
-		setflags = (S == '1')
-		shift_imm = DecodeImmShift('01', imm3:imm2)
+			reg_D = Register(Rd)
+			reg_M = Register(Rm)
+			shift_n = DecodeImmShiftAmount('01', imm3:imm2)
+
+		}
+
+		@asm lsr.w ?reg_D reg_M shift_n
 
 	}
 
-	@rules {
+	@syntax {
+
+		@assert {
+
+			S == 1
+
+		}
+
+		@conv {
+
+			reg_D = Register(Rd)
+			reg_M = Register(Rm)
+			shift_n = DecodeImmShiftAmount('01', imm3:imm2)
+
+		}
 
-		if (setflags); chk_call ExtendKeyword("s")
-		chk_call ExtendKeyword(".w")
+		@asm lsrs.w ?reg_D reg_M shift_n
 
 	}
 
@@ -69,21 +101,55 @@
 
 	@word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) imm5(5) 0 1 0 Rm(4)
 
-	@syntax <reg_D> <reg_M> <shift_imm>
+	@syntax {
 
-	@conv {
+		@assert {
 
-		reg_D = Register(Rd)
-		reg_M = Register(Rm)
-		setflags = (S == '1')
-		shift_imm = DecodeImmShift('01', imm5)
+			S == 0
+
+		}
+
+		@conv {
+
+			reg_D = Register(Rd)
+			reg_M = Register(Rm)
+			shift_n = DecodeImmShiftAmount('01', imm5)
+
+		}
+
+		@asm lsr ?reg_D reg_M shift_n
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
+
+		}
 
 	}
 
-	@rules {
+	@syntax {
+
+		@assert {
+
+			S == 1
+
+		}
+
+		@conv {
+
+			reg_D = Register(Rd)
+			reg_M = Register(Rm)
+			shift_n = DecodeImmShiftAmount('01', imm5)
+
+		}
+
+		@asm lsrs ?reg_D reg_M shift_n
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
 
-		if (setflags); chk_call ExtendKeyword("s")
-		chk_call StoreCondition(cond)
+		}
 
 	}