1 files changed, 63 insertions, 18 deletions
diff --git a/plugins/arm/v7/opdefs/mla_A88100.d b/plugins/arm/v7/opdefs/mla_A88100.d
index 5d4b4e4..654ae37 100644
--- a/plugins/arm/v7/opdefs/mla_A88100.d
+++ b/plugins/arm/v7/opdefs/mla_A88100.d
@@ -2,7 +2,7 @@
 /* Chrysalide - Outil d'analyse de fichiers binaires
  * ##FILE## - traduction d'instructions ARMv7
  *
- * Copyright (C) 2015 Cyrille Bagard
+ * Copyright (C) 2017 Cyrille Bagard
  *
  *  This file is part of Chrysalide.
  *
@@ -23,20 +23,30 @@
 
 @title MLA
 
-@desc Multiply Accumulate multiplies two register values, and adds a third register value. The least significant 32 bits of the result are written to the destination register. These 32 bits do not depend on whether the source register values are considered to be signed values or unsigned values. In an ARM instruction, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many processor implementations.
+@id 99
+
+@desc {
+
+	Multiply Accumulate multiplies two register values, and adds a third register value. The least significant 32 bits of the result are written to the destination register. These 32 bits do not depend on whether the source register values are considered to be signed values or unsigned values. In an ARM instruction, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many processor implementations.
+
+}
 
 @encoding (T1) {
 
 	@word 1 1 1 1 1 0 1 1 0 0 0 0 Rn(4) Ra(4) Rd(4) 0 0 0 0 Rm(4)
 
-	@syntax <reg_D> <reg_N> <reg_M> <reg_A>
+	@syntax {
+
+		@conv {
+
+			reg_D = Register(Rd)
+			reg_N = Register(Rn)
+			reg_M = Register(Rm)
+			reg_A = Register(Ra)
 
-	@conv {
+		}
 
-		reg_D = Register(Rd)
-		reg_N = Register(Rn)
-		reg_M = Register(Rm)
-		reg_A = Register(Ra)
+		@asm mla reg_D reg_N reg_M reg_A
 
 	}
 
@@ -46,22 +56,57 @@
 
 	@word cond(4) 0 0 0 0 0 0 1 S(1) Rd(4) Ra(4) Rm(4) 1 0 0 1 Rn(4)
 
-	@syntax <reg_D> <reg_N> <reg_M> <reg_A>
+	@syntax {
+
+		@assert {
+
+			S == 0
+
+		}
+
+		@conv {
+
+			reg_D = Register(Rd)
+			reg_N = Register(Rn)
+			reg_M = Register(Rm)
+			reg_A = Register(Ra)
+
+		}
 
-	@conv {
+		@asm mla reg_D reg_N reg_M reg_A
 
-		reg_D = Register(Rd)
-		reg_N = Register(Rn)
-		reg_M = Register(Rm)
-		reg_A = Register(Ra)
-		setflags = (S == '1')
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
+
+		}
 
 	}
 
-	@rules {
+	@syntax {
+
+		@assert {
+
+			S == 1
+
+		}
+
+		@conv {
+
+			reg_D = Register(Rd)
+			reg_N = Register(Rn)
+			reg_M = Register(Rm)
+			reg_A = Register(Ra)
+
+		}
+
+		@asm mlas reg_D reg_N reg_M reg_A
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
 
-		if (setflags); chk_call ExtendKeyword("s")
-		chk_call StoreCondition(cond)
+		}
 
 	}