diff options
Diffstat (limited to 'plugins/arm/v7/opdefs/mov_A88102.d')
| -rw-r--r-- | plugins/arm/v7/opdefs/mov_A88102.d | 138 |
1 files changed, 105 insertions, 33 deletions
diff --git a/plugins/arm/v7/opdefs/mov_A88102.d b/plugins/arm/v7/opdefs/mov_A88102.d index d96baab..e38442b 100644 --- a/plugins/arm/v7/opdefs/mov_A88102.d +++ b/plugins/arm/v7/opdefs/mov_A88102.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title MOV (immediate) -@desc Move (immediate) writes an immediate value to the destination register. It can optionally update the condition flags based on the value. +@id 101 + +@desc { + + Move (immediate) writes an immediate value to the destination register. It can optionally update the condition flags based on the value. + +} @encoding (t1) { @half 0 0 1 0 0 Rd(3) imm8(8) - @syntax "movs" <reg_D> <imm32> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + imm32 = ZeroExtend(imm8, 32) - reg_D = Register(Rd) - imm32 = ZeroExtend(imm8, 32) + } + + @asm mov reg_D imm32 } @@ -44,20 +54,41 @@ @word 1 1 1 1 0 i(1) 0 0 0 1 0 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm8(8) - @syntax <reg_D> <imm32> + @syntax { + + @assert { + + S == 0 + + } + + @conv { - @conv { + reg_D = Register(Rd) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) - reg_D = Register(Rd) - setflags = (S == '1') - imm32 = ThumbExpandImm_C(i:imm3:imm8, 0) + } + + @asm mov.w reg_D const } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + reg_D = Register(Rd) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) + + } + + @asm movs.w reg_D const } @@ -67,12 +98,16 @@ @word 1 1 1 1 0 i(1) 1 0 0 1 0 0 imm4(4) 0 imm3(3) Rd(4) imm8(8) - @syntax "movw" <reg_D> <imm32> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + imm32 = ZeroExtend(imm4:i:imm3:imm8, 32) - reg_D = Register(Rd) - imm32 = ZeroExtend(imm4:i:imm3:imm8, 32) + } + + @asm movw reg_D imm32 } @@ -82,20 +117,53 @@ @word cond(4) 0 0 1 1 1 0 1 S(1) 0 0 0 0 Rd(4) imm12(12) - @syntax <reg_D> <imm32> + @syntax { + + @assert { - @conv { + S == 0 - reg_D = Register(Rd) - setflags = (S == '1') - imm32 = ARMExpandImm_C(imm12, 0) + } + + @conv { + + reg_D = Register(Rd) + const = ARMExpandImm_C(imm12, APSR_C) + + } + + @asm mov reg_D const + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + @conv { + + reg_D = Register(Rd) + const = ARMExpandImm_C(imm12, APSR_C) + + } + + @asm movs reg_D const + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } @@ -105,18 +173,22 @@ @word cond(4) 0 0 1 1 0 0 0 0 imm4(4) Rd(4) imm12(12) - @syntax "movw" <reg_D> <imm32> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - imm32 = ZeroExtend(imm4:imm12, 32) + reg_D = Register(Rd) + imm32 = ZeroExtend(imm4:imm12, 32) - } + } + + @asm movw reg_D imm32 + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } |